FIELD PROGRAMMABLE GATE ARRAY
A field programmable gate array is disclosed, which comprises at least one logic element having at least one switching element. The switching element comprises a static support element and a movable connecting element for providing a non-volatile electrical connection.
The present invention relates to a field programmable gate array (FPGA) comprising a logic element having at least one switching element for providing a switchable electrical connection.
A field-programmable gate array (FPGA) is a semiconductor device that can be configured by the customer or the designer “in the field” after manufacturing. FPGAs are programmed using a logic circuit diagram or a source code in a hardware description language (HDL) to specify the functionality of the FPGA. Any logical function that an application specific integrated circuit (ASIC) could perform can be implemented. FPGAs contain programmable logic components called logic blocks. The main building blocks of FPGAs are so called standardized Basic Logic Elements (BLE).
Logic blocks typically comprise a variety of different logic elements that can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs the logic blocks also include memory elements, which may be simple flip-flops or more complex blocks of memory.
A hierarchy of reconfigurable interconnects allows the blocks to be wired together, comparable to a one-chip programmable breadboard. The interconnection between the BLEs is provided by so called Configurable Routing Channels (CRC). Each FPGA device consists of a huge amount of BLEs, which can be arbitrarily connected via the very flexible CRCs, thus forming complex sequential or combinatorial logical networks.
In common FPGAs the BLEs are built using common Complementary Metal Oxide Semiconductor (CMOS) circuit elements, comprising for example Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Since MOSFETs are volatile, i.e. they lose their status after power is switched off, such FPGAs have to be programmed every time when switched on. However, CMOS technology is approaching its scaling limits. Further, due to the fact that MOSFETs are used as switching elements in typical CMOS circuitry, the signal speed is comparably slow and leakage of current occurs in static mode.
Accordingly, it is an object of the present invention to provide a field programmable gate array that is improved with respect to the drawbacks know from prior art.
The problem is solved by the subject matter of claim 1. Advantageous embodiments are subject matter of the dependent claims.
A field programmable gate array according to the invention comprises at least one logic element for providing a logic function, wherein the logic element has at least one switching element. The switching element comprises a static support element and a movable connecting element, which provides a nonvolatile electrical connection.
Since the switching element provides a nonvolatile electrical connection, the field programmable gate array remains in its status even if the power supply is switched off. Consequently, the device, i.e. the field programmable gate array, will immediately resume processing in case the power supply is switched on again. Further, the device will resume processing exactly in the status in which it has been switched off. This feature is often called “instant-on”, because the rather long boot time of modern digital devices is avoided.
Advantageously, the logic element is one of an AND-, OR-, NOT-, NAND-, NOR-, XOR-, XNOR-element and a multiplexer. This means that the switching element is included in a logic gate. The aforementioned logic gates are building blocks for more complex circuitry, like e.g. a flip-flop. Advantageously, these building blocks are of a nonvolatile nature. Therefore, more complex logical blocks or gates that are based on the aforementioned logic gates provide an “instant-on” characteristic. No further adaptation like integration of memory cells or the like is necessary
It is further advantageous if the logic element comprises two alternately working switching elements. By applying two alternately working switching elements, the basic functionality of a non-volatile multiplexer is provided.
Alternatively, the switching element comprises a static support element that is connected to an output of the logic element and a movable connecting element adapted to establish a connection of the static support element to either the first input or a second input of said logical element. In other words, the aforementioned two alternately working switching elements are replaced by one switching element capable of providing an electrical connection to either a first or a second input. Due to the fact that only one movable connecting element is employed, the number of moving parts is advantageously reduced.
A further advantageous field programmable gate array comprises at least one switching element acting as a storage cell. The open/closed-state of said switching element is used to store bit information. Since the switching element provides a nonvolatile electrical connection, a nonvolatile storage cell is thus provided. It is further advantageous if a look-up table comprises at least one such storage cell.
Advantageously, the field programmable gate array comprises a basic logic element that is composed of at least one storage cell, a flip flop and a multiplexer, wherein the aforementioned elements are realized using said non-volatile switching elements.
An advantageous field programmable gate array comprises a switching element that is realized based on nanotube technology, preferably carbon nanotube technology. Appropriate switching elements will be referred to as carbon nanotube switches.
Preferably, the switching element comprises a telescoping nanotube, preferably a telescoping carbon nanotube. Such a telescoping nanotube comprises a movable core-nanotube and a static support-nanotube, wherein the core-nanotube surrounds the static support-nanotube or vice versa. Preferably, at least a segment of the core-nanotube and the support-nanotube form part of a conductive path that a switchable current takes through the switching element.
Signal speed of electrical signals is very fast in carbon nanotube switching elements. Consequently, a field programmable gate array based on such a switching element shows a high processing performance. The drawbacks known from CMOS-technology, like e.g. the comparably low signal transfer speed due to the charge carrier characteristic of solid state semiconductors like e.g. MOSFETs, is overcome. A further advantage is given by the fact that a carbon-nanotube switch disconnects the input and output terminal galvanically. Thereby, in contrast to common MOSFET-technology, the occurrence of leak currents is avoided. Consequently, a field programmable gate array based on carbon-nanotube switching elements has a very small static power dissipation. Consequently, it is perfectly suited for mobile-applications.
Advantageously, switching elements based on nanotube switches consist of less circuit elements compared to common CMOS-technology. This means that a field programmable gate array comprising nanotube switching elements is very compact and, therefore, occupies less chip area. At the same time the application of nanotube switches has only little effect on a chip production line. Nanotube switches can be fabricated using manufacturing tools known from MOEFET-technology. Therefore, a very densely packed electrical circuitry that can be fabricated in an economical way is provided.
For a better understanding the invention shall now be explained in more detail in the following description with reference to the figures. It is understood that the invention is not limited to this exemplary embodiment and that specified features can also expediently be combined and/or modified without departing from the scope of the present invention as defined in the appended claims. In the figures:
Depending on the voltage that is applied to the switching element 8 by the select line 22, a varying electrical field E is applied. The varying electrical field E causes the switching process, which is depicted in
Each of the aforementioned logic gates, in particular the multiplexer 18 (see
Claims
1-9. (canceled)
10. Field programmable gate array comprising at least one logic, element for providing a logical function, the logic element having at least one switching element, wherein said at least one switching element comprises a static support element and a displaceable connecting element providing a non-volatile electrical connection.
11. Field programmable gate array according to claim 10, wherein the logic element, is one of AND-, OR, NOT-, NAND-, NOR-, XOR-, XNOR-element and a multiplexer.
12. Field programmable gate array according to claim 11, wherein the logic element is one of AND-, OR, NOT-, NAND-, NOR-, XOR-, XNOR-element and a multiplexer.
13. Field programmable gate array according to claim 10, wherein the logic element comprises two alternately working switching elements.
14. Field programmable gate array according to claim 11, wherein the logic element comprises two alternately working switching elements.
15. Field programmable gate array according to claim 10, wherein the static support element is connected to an output of the logic element and the displaceable connecting element is adapted to establish a connection of the static support element to either a first input or a second input of the logic element.
16. Field programmable gate array according to claim 11, wherein the static support element is connected to an output of the logic element and the displaceable connecting element is adapted to establish a connection of the static support element to either a first input or a second input of the logic element.
17. Field programmable gate array according to claim 10, wherein the field programmable gate array further comprises at least one switching element acting as a storage cell, wherein bit information is stored in the form of an open/closed-state of the respective switching element.
18. Field programmable gate array according to claim 17, wherein multiple storage cells are combined to a look-up table.
19. Field programmable gate array according to claim 10, having a basic logic element composed of at least one storage cell, one flip-flop and one multiplexer realized with said switching elements.
20. Field programmable gate array according to claim 16, having a basic logic: element composed of at least one storage cell, one flip-flop and one multiplexer realized with said switching elements.
21. Field programmable gate array according to claim 10, wherein the switching element comprises a telescoping nanotube.
22. Field programmable gate array according to claim 17, wherein the switching element comprises a telescoping nanotube.
23. Field programmable gate array according to claim 20, wherein the switching element comprises a telescoping nanotube.
24. Field programmable gate array according to claim 21, wherein at least one segment of the static support element and the movable connecting element form part of a conductive path that a switchable current takes through the switching element.
25. Field programmable gate array according to claim 22, wherein at least one segment of the static support element and the movable connecting element form part of a conductive path that a switchable current takes through the switching element.
26. Field programmable gate array according to claim 23, wherein at least one segment of the static support element and the movable connecting element form part of a conductive path that a switchable current takes through the switching element.
27. Multiplexer comprising a first input line and a second input line and an output line, further comprising a first telescopic carbon nanotube and a second telescopic carbon nanotube, one connector of the first telescopic carbon nanotube being connected to the first input line, the other connector of the first telescopic carbon nanotube being connected to the output line, one connector of the second telescopic carbon nanotube being connected to the second input line, the other connector of the second telescopic carbon nanotube being connected to the output line, wherein the multiplexer is configured such that the first and the second telescopic carbon nanotubes work in phase opposition.
Type: Application
Filed: Feb 8, 2011
Publication Date: Dec 20, 2012
Inventors: Meinolf Blawat (Hannover), Holger Kropp (Wedemark)
Application Number: 13/582,114
International Classification: H03K 19/177 (20060101); G06G 7/12 (20060101);