Dynamic Random Access Memory Structures (dram) (epo) Patents (Class 257/E21.646)

  • Patent number: 10541243
    Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Do, Seungyoung Lee, Jonghoon Jung, Jinyoung Lim, Giyoung Yang, Sanghoon Baek, Taejoong Song
  • Patent number: 10083739
    Abstract: A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Kuei Lin, Hung-Jen Liao, Yen-Huei Chen, Ching-Wei Wu
  • Patent number: 10056482
    Abstract: A method for fabricating a semiconductor structure is provided that includes the steps of: forming a structure including a substrate, a counter-doped layer on the substrate, and a heavily doped source contact layer on a side of the counter-doped layer opposite the substrate; and forming an oxide layer on a side of the heavily doped source contact layer opposite the counter-doped layer, wherein the oxide layer has a vertical dimension that is a difference between a length of a long channel thick oxide device and a length of a short channel non-thick oxide device.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9941294
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The first gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other. The semiconductor device structure includes a ring structure surrounding the first gate stack. The ring structure is made of a conductive material.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yen Hsaio, Cheng-Ming Wu, Shih-Lu Hsu, Chien-Hsian Wang
  • Patent number: 9929264
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9793271
    Abstract: A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second fin, the first fin arranged a first distance from the second fin, the first fin and the second fin extending from a first source/drain region through a channel region and into a second source/drain region on the substrate. The method further includes forming a third fin on the substrate, the third fin arranged in parallel with the first fin and between the first fin and the second fin, the third fin arranged a second distance from the first fin, the second distance is less than the first distance, the third fin having two distal ends arranged in the first source/drain region. A gate stack is formed over the first fin and the second fin.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Terence B. Hook
  • Patent number: 9570681
    Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 14, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Cristina Casellato, Carmela Cupeta, Michele Magistretti, Fabio Pellizzer, Roberto Somaschini
  • Patent number: 9449963
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor structure includes a fin structure formed over a substrate and a first gate structure formed over the substrate. In addition, a first portion of the first gate structure overlaps with a portion of the fin structure. The first capacitor structure further includes a first hard mask structure formed over the first portion of the first gate structure and a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure. The first capacitor structure further includes a first contact formed on a second portion of the first gate structure. In addition, the first contact is in direct contact with the second portion of the first gate structure.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Huang-Kui Chen
  • Patent number: 9349468
    Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: May 24, 2016
    Assignee: SanDisk Technologies, Inc.
    Inventors: Kenneth Louie, Khanh Nguyen, Hao Nguyen
  • Patent number: 9305847
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: April 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chi Chen, Chih-Yueh Li, Shui-Yen Lu, Chi-Mao Hsu, Yuan-Chi Pai, Yu-Hong Kuo, Nien-Ting Ho
  • Patent number: 9305848
    Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Walter Blatchford, Scott William Jessen
  • Patent number: 9041154
    Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 26, 2015
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Chien-An Yu, Chih-Huang Wu
  • Patent number: 9012967
    Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
  • Patent number: 8999862
    Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Jung Hyung Lee, Hyun Kyung Shim, Chang Il Oh
  • Patent number: 8946019
    Abstract: In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dmytro Chumakov, Tino Hertzsch
  • Patent number: 8946855
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: February 3, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Ho Sohn
  • Patent number: 8940601
    Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Youichi Yamamoto, Masayuki Tachikawa, Yoshitake Kato
  • Patent number: 8916918
    Abstract: Disclosed is a semiconductor device including: an active region defined by an element isolation region; a gate trench going across the active region to define source/drain regions on both sides thereof, respectively, and to define, between the source/drain regions, the channel region having a first, second, and third protruding portions which are arranged in a gate width direction; and a gate electrode formed in the gate trench so as to cover the channel region through a gate insulating film.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: December 23, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Hiroo Nishi, Hiromitsu Oshima
  • Patent number: 8906763
    Abstract: A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Chul Park, Byung-Jin Kang, Sang-Sup Jeong
  • Patent number: 8907410
    Abstract: A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Sami Rosenblatt, Geng Wang
  • Patent number: 8901704
    Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8860117
    Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 8815743
    Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Uwe Hoeckele, Thomas Kunstmann, Uwe Seidel
  • Patent number: 8817534
    Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 26, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Serguei Okhonin, Viktor I Koldiaev, Mikhail Nagoga, Yogesh Luthra
  • Patent number: 8790975
    Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser, Vivien Schroeder
  • Patent number: 8791512
    Abstract: An imaging device is formed in a semiconductor substrate. The device includes a matrix array of photosites. Each photosite is formed of a semiconductor region for storing charge, a semiconductor region for reading charge specific to said photosite, and a charge transfer circuit configured so as to permit a transfer of charge between the charge storage region and the charge reading region. Each photosite further includes at least one buried first electrode. At least one part of that buried first electrode bounds at least one part of the charge storage region. The charge transfer circuit for each photosite includes at least one second buried electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 29, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Francois Roy, Julien Michelot
  • Patent number: 8772841
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 8759944
    Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Du Li
  • Patent number: 8753966
    Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 17, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jum-Yong Park, Jong-Han Shin
  • Patent number: 8742483
    Abstract: The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Mark Fischer
  • Patent number: 8716138
    Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 6, 2014
    Assignee: FlashSilicon Incorporation
    Inventor: Lee Wang
  • Patent number: 8703566
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8703552
    Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 8698209
    Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: April 15, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8686486
    Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Toshihiko Saito
  • Patent number: 8680596
    Abstract: There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai
  • Patent number: 8673729
    Abstract: A method of forming a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor comprises forming a buried oxide layer in a substrate, the buried oxide layer defining an SOI layer on a surface of the substrate; forming a deep trench through the SOI layer and the buried oxide layer in the substrate; forming a storage capacitor in a lower portion of the deep trench; conformally doping a sidewall of an upper portion of the deep trench; depositing a metal strap on the conformally doped sidewall and on the storage capacitor; forming at least one fin in the SOI layer, the fin being in communication with the metal strap; forming a spacer over the metal strap and over a juncture of the fin and the metal strap; and depositing a passive word line on the spacer.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8658538
    Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 25, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
  • Patent number: 8648403
    Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wing K. Luk, Jin Cai
  • Patent number: 8647988
    Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: February 11, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
  • Patent number: 8637376
    Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening with etching depth Hd, while remaining a first region that is a distance Lr in a horizontal direction from a rising point of a projected portion of the interlayer insulating film periphery to the capacitor array onto a part of the capacitor array, wherein an aspect ratio (Hd/Lr) of the Hd to the Lr is equal to or less than 0.6.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: January 28, 2014
    Inventors: Shigeru Sugioka, Nobuyuki Sako, Ryoichi Tanabe
  • Patent number: 8637363
    Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a preliminary mask pattern on an etch target layer. The preliminary mask pattern includes wave line type patterns, and each of the wave line type patterns includes main pattern portions and connection bar pattern portions. Node separation walls are formed on sidewalls of the preliminary mask patterns. The etch target layer is etched using the node separation walls as etch masks to form through holes penetrating the etch target layer. Nodes are formed in respective ones of the through holes.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 28, 2014
    Assignee: SK hynix Inc.
    Inventor: Yong Soon Jung
  • Publication number: 20140021523
    Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Babar A. Khan, Effendi Leobandung
  • Patent number: 8624350
    Abstract: The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 7, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Do Hyung Kim, Young Man Cho
  • Patent number: 8624313
    Abstract: A semiconductor device includes a semiconductor substrate, a non-volatile semiconductor memory element formed over the semiconductor substrate, including a variable resistance element including a laminate comprising a first electrode, a variable resistance layer, and a second electrode, and a volatile semiconductor memory element formed over the semiconductor substrate, including a capacitance element including a laminate comprising a third electrode, a dielectric layer including a same material as the variable resistance layer, and a fourth electrode.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 7, 2014
    Inventor: Kazuhiko Kajigaya
  • Patent number: 8617949
    Abstract: A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
  • Patent number: 8618615
    Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 31, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Se hyun Kim
  • Publication number: 20130328116
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Application
    Filed: June 7, 2012
    Publication date: December 12, 2013
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Patent number: 8604532
    Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Win K. Luk, Jin Cai
  • Publication number: 20130320422
    Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Babar A. Khan, Paul C. Parries, Xinhui Wang