Dynamic Random Access Memory Structures (dram) (epo) Patents (Class 257/E21.646)
- Ferroelectric nonvolatile memory structures (EPO) (Class 257/E21.663)
- Magnetic nonvolatile memory structures, e.g., MRAM (EPO) (Class 257/E21.665)
- PROM (EPO) (Class 257/E21.666)
- ROM only (EPO) (Class 257/E21.667)
- With source and drain on same level, e.g., lateral channel (EPO) (Class 257/E21.668)
- Source or drain contact programmed (EPO) (Class 257/E21.669)
- Gate contact programmed (EPO) (Class 257/E21.67)
- Doping programmed, e.g., mask ROM (EPO) (Class 257/E21.671)
- Gate programmed, e.g., different gate material or no gate (EPO) (Class 257/E21.674)
- Gate dielectric programmed, e.g., different thickness (EPO) (Class 257/E21.675)
- With source and drain on different levels, e.g., vertical channel (EPO) (Class 257/E21.676)
- With FETs on different levels, e.g., 3D ROM (EPO) (Class 257/E21.677)
- Simultaneous fabrication of periphery and memory cells (EPO) (Class 257/E21.678)
- Charge trapping insulator nonvolatile memory structures (EPO) (Class 257/E21.679)
- Electrically programmable (EPROM), i.e., floating gate memory structures (EPO) (Class 257/E21.68)
- With conductive layer as control gate (EPO) (Class 257/E21.681)
- With source and drain on same level and without cell select transistor (EPO) (Class 257/E21.682)
- With source and drain on same level and with cell select transistor (EPO) (Class 257/E21.69)
- With source and drain on different levels, e.g., sloping channel (EPO) (Class 257/E21.692)
- With doped region as control gate (EPO) (Class 257/E21.694)