MEMORY CELL AND MEMORY CELL ARRAY USING THE SAME
A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.
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The present invention relates to a memory technique field, and more particularly to a memory cell and a memory cell array using the same.
BACKGROUND OF THE INVENTIONThe object of present invention is to provide a memory cell having higher anti-noise ability and consequently being capable of preventing errors from occurring while performing data access.
Another object of present invention is to provide a memory cell array using the aforementioned memory cell.
An embodiment of the present invention provides a memory cell, which includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor and a fourth N-type transistor. The first P-type transistor is configured to have the first source/drain thereof electrically coupled to a first voltage. The second P-type transistor is configured to have the first source/drain thereof electrically coupled to the first voltage. The first N-type transistor is configured to have the first source/drain thereof electrically coupled to the second source/drain of the first P-type transistor, the second source/drain thereof electrically coupled to a second voltage, and the gate thereof electrically coupled to the gate of the first P-type transistor. The second N-type transistor is configured to have the first source/drain thereof electrically coupled to the second source/drain of the second P-type transistor, the second source/drain thereof electrically coupled to the second voltage, and the gate thereof electrically coupled to the gate of the second P-type transistor. The third N-type transistor is configured to have the first source/drain thereof electrically coupled to a write word line, the second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate thereof electrically coupled to a first write bit line. The fourth N-type transistor is configured to have the first source/drain thereof electrically coupled to the write word line, the second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and the gate thereof electrically coupled to a second write bit line.
Another embodiment of the present invention provides a memory cell array, which includes a plurality of write word lines, a plurality of first write bit lines, a plurality of second write bit lines and a plurality of memory cells. The memory cells are arranged in a matrix form and each one of the memory cells is electrically coupled to one of the write word lines, one of the first write bit lines and one of the second write bit lines. Each one of the memory cells includes a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor and a fourth N-type transistor. The first P-type transistor is configured to have the first source/drain thereof electrically coupled to a first voltage. The second P-type transistor is configured to have the first source/drain thereof electrically coupled to the first voltage. The first N-type transistor is configured to have the first source/drain thereof electrically coupled to the second source/drain of the first P-type transistor, the second source/drain thereof electrically coupled to a second voltage, and the gate thereof electrically coupled to the gate of the first P-type transistor. The second N-type transistor is configured to have the first source/drain thereof electrically coupled to the second source/drain of the second P-type transistor, the second source/drain thereof electrically coupled to the second voltage, and the gate thereof electrically coupled to the gate of the second P-type transistor. The third N-type transistor is configured to have the first source/drain thereof electrically coupled to one of the write word lines, the second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate thereof electrically coupled to one of the first write bit lines. The fourth N-type transistor is configured to have the first source/drain thereof electrically coupled to one of the write word lines, the second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and the gate thereof electrically coupled to one of the second write bit lines.
In summary, through controlling the third and fourth N-type transistors to be turned on at different times by the first write bit line and the second write bit line, respectively, the memory cell as well as the memory cell array using the same of the present invention accordingly can have higher anti-noise ability and consequently is capable of preventing errors from occurring while performing data access.
The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
Specifically, the P-type transistors P1, P2 each are configured to have the first source/drain thereof electrically coupled to a first voltage VDD. The N-type transistor Ni is configured to have the first source/drain thereof electrically coupled to the second source/drain of the P-type transistor P1, the second source/drain thereof electrically coupled to a second voltage VSS, and the gate thereof electrically coupled to the gate of the P-type transistor P1. The N-type transistor N2 is configured to have the first source/drain thereof electrically coupled to the second source/drain of the P-type transistor P2, the second source/drain thereof electrically coupled to the second voltage VSS, and the gate thereof electrically coupled to the gate of the P-type transistor P2. The N-type transistor N3 is configured to have the first source/drain thereof electrically coupled to a write word line WWL, the second source/drain thereof electrically coupled to the first source/drain of the N-type transistor Ni and the gate of the N-type transistor N2, and the gate thereof electrically coupled to a first write bit line WBL. The N-type transistor N4 is configured to have the first source/drain thereof electrically coupled to the write word line WWL, the second source/drain thereof electrically coupled to the first source/drain of the N-type transistor N2 and the gate of the N-type transistor N1, and the gate thereof electrically coupled to a second write bit line WBLB. The N-type transistor N5 is configured to have the first source/drain thereof electrically coupled to a read bit line RBL, and the gate thereof electrically coupled to a read word line RWL. The N-type transistor N6 is configured to have the first source/drain thereof electrically coupled to the second source/drain of the N-type transistor N5, the second source/drain thereof electrically coupled to the second voltage VSS, and the gate thereof electrically coupled to the gate of the N-type transistor N1. In this embodiment, the first voltage VDD is configured to have a value greater than that of the second voltage VSS. Additionally, in this embodiment, the transistors N3, N4 each are exemplified by an N-type transistor; however, it is understood that the two transistors N3, N4 each can be realized by a P-type transistor in an alternative embodiment.
According to the circuit structure of the memory cell 30 shown in
In summary, through controlling the N-type transistors N3, N4 to be turned on at different times by the first write bit line WBL and the second write bit line WBLB, respectively, the memory cell 30 as well as the memory cell array 60 using the same memory cell of the embodiment of the present invention accordingly can have higher anti-noise ability and consequently is capable of preventing errors from occurring while performing data access.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Claims
1. A memory cell, comprising:
- a first P-type transistor configured to have the first source/drain thereof electrically coupled to a first voltage;
- a second P-type transistor configured to have the first source/drain thereof electrically coupled to the first voltage;
- a first N-type transistor configured to have the first source/drain thereof electrically coupled to the second source/drain of the first P-type transistor, the second source/drain thereof electrically coupled to a second voltage, and the gate thereof electrically coupled to the gate of the first P-type transistor;
- a second N-type transistor configured to have the first source/drain thereof electrically coupled to the second source/drain of the second P-type transistor, the second source/drain thereof electrically coupled to the second voltage, and the gate thereof electrically coupled to the gate of the second P-type transistor;
- a third N-type transistor configured to have the first source/drain thereof electrically coupled to a write word line, the second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate thereof electrically coupled to a first write bit line; and
- a fourth N-type transistor configured to have the first source/drain thereof electrically coupled to the write word line, the second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and the gate thereof electrically coupled to a second write bit line.
2. The memory cell according to claim 1, further comprising:
- a fifth N-type transistor configured to have the first source/drain thereof electrically coupled to a read bit line, and the gate thereof electrically coupled to a read word line; and
- a sixth N-type transistor configured to have the first source/drain thereof electrically coupled to the second source/drain of the fifth N-type transistor, the second source/drain thereof electrically coupled to the second voltage, and the gate thereof electrically coupled to the gate of the first N-type transistor.
3. The memory cell according to claim 1, wherein the first voltage is configured to have a value greater than that of the second voltage.
4. The memory cell according to claim 1, wherein the first write bit line is configured to turn on or turn off the third N-type transistor, the second write bit line is configured to turn on or turn off the fourth N-type transistor.
5. The memory cell according to claim 4, wherein the third and fourth N-type transistors are controlled to be turned on at different times.
6. The memory cell according to claim 4, wherein the write word line is configured to have a low voltage level thereon when the first write bit line has a high voltage level thereon and the second write bit line has a low voltage level thereon.
7. The memory cell according to claim 4, wherein the write word line is configured to have a low voltage level thereon when the first write bit line has a low voltage level thereon and the second write bit line has a high voltage level thereon.
8. The memory cell according to claim 1, wherein each of the third and fourth N-type transistors is replaced by a P-type transistor.
9. A memory cell array, comprising:
- a plurality of write word lines;
- a plurality of first write bit lines;
- a plurality of second write bit lines; and
- a plurality of memory cells arranged in a matrix form, each one of the memory cells being electrically coupled to one of the write word lines, one of the first write bit lines and one of the second write bit lines, each one of the memory cells comprising: a first P-type transistor configured to have the first source/drain thereof electrically coupled to a first voltage; a second P-type transistor configured to have the first source/drain thereof electrically coupled to the first voltage; a first N-type transistor configured to have the first source/drain thereof electrically coupled to the second source/drain of the first P-type transistor, the second source/drain thereof electrically coupled to a second voltage, and the gate thereof electrically coupled to the gate of the first P-type transistor; a second N-type transistor configured to have the first source/drain thereof electrically coupled to the second source/drain of the second P-type transistor, the second source/drain thereof electrically coupled to the second voltage, and the gate thereof electrically coupled to the gate of the second P-type transistor; a third N-type transistor configured to have the first source/drain thereof electrically coupled to one of the write word lines, the second source/drain thereof electrically coupled to the first source/drain of the first N-type transistor and the gate of the second N-type transistor, and the gate thereof electrically coupled to one of the first write bit lines; and a fourth N-type transistor configured to have the first source/drain thereof electrically coupled to one of the write word lines, the second source/drain thereof electrically coupled to the first source/drain of the second N-type transistor and the gate of the first N-type transistor, and the gate thereof electrically coupled to one of the second write bit lines.
10. The memory cell array according to claim 9, wherein each one of the memory cells further comprises:
- a fifth N-type transistor configured to have the first source/drain thereof electrically coupled to one of the read bit lines, and the gate thereof electrically coupled to one of the read word lines; and
- a sixth N-type transistor configured to have the first source/drain thereof electrically coupled to the second source/drain of the fifth N-type transistor, the second source/drain thereof electrically coupled to the second voltage, and the gate thereof electrically coupled to the gate of the first N-type transistor.
11. The memory cell array according to claim 9, wherein the first voltage is configured to have a value greater than that of the second voltage.
12. The memory cell array according to claim 9, wherein one of the first write bit lines is configured to turn on or turn off the third N-type transistor, one of the second write bit lines is configured to turn on or turn off the fourth N-type transistor.
13. The memory cell array according to claim 12, wherein the third and fourth N-type transistors are controlled to be turned on at different times.
14. The memory cell array according to claim 12, wherein one of the write word lines is configured to have a low voltage level thereon when one of the first write bit lines has a high voltage level thereon and one of the second write bit lines has a low voltage level thereon.
15. The memory cell array according to claim 12, wherein one of the write word lines is configured to have a low voltage level thereon when one of the first write bit lines has a low voltage level thereon and one of the second write bit lines has a high voltage level thereon.
16. The memory cell array according to claim 9, wherein each of the third and fourth N-type transistors is replaced by a P-type transistor.
Type: Application
Filed: Nov 21, 2012
Publication Date: May 22, 2014
Applicant: United Microelectronics Corporation (Hsinchu)
Inventors: Hsin-Wen CHEN (Kaohsiung City), Chi-Chang SHUAI (Hsinchu City), Shih-Chin LIN (Hsinchu County)
Application Number: 13/682,742
International Classification: G11C 5/06 (20060101);