PFET DEVICES WITH DIFFERENT STRUCTURES AND PERFORMANCE CHARACTERISTICS
Disclosed herein is a device that includes a first PFET transistor formed in and above a first active region of a semiconducting substrate, a second PFET transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different.
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1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming PFET devices with different structures and performance characteristics.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. A basic field effect transistor comprises a source region, a gate region and a channel region positioned between the source and drain regions. Such a transistor further includes a gate insulation layer positioned above the channel region and a gate electrode positioned above the gate insulation layer. When an appropriate voltage is applied to the gate electrode, the channel region becomes conductive and current may flow from the source region to the drain region. In many cases, the gate electrodes are made of polysilicon. The basic structure of a field effect transistor is typically formed by forming various layers of material and thereafter patterning those layers of material using known photolithography and etching processes. Various doped regions, e.g., source regions, drain regions, halo regions, etc., are typically formed by performing one or more ion implantation processes through a patterned mask layer using an appropriate dopant material, e.g., an N-type dopant or a P-type dopant, to implant the desired dopant material into the substrate. The particular dopant selected depends on the specific implant region being formed and the type of device under construction, i.e., an NFET transistor or a PFET transistor. During the fabrication of complex integrated circuits millions of transistors, e.g., NFET transistors and/or PFET transistors are formed on a substrate by performing a number of process operations.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NFET transistors and create a compressive stress in the channel region for PFET transistors). One performance-enhancing technique that has been employed in manufacturing PFET transistors involves the use of a silicon germanium channel layer. Such a silicon germanium channel layer is typically formed by forming a recess in an active region of a substrate where such a PFET transistor will be formed and thereafter, performing an epitaxial deposition process to form a layer of silicon germanium in the recess. Other semiconductor devices, such as NFET transistors that are being formed on the same substrate, are typically masked while the silicon germanium channel layer is being formed for the PFET transistors. The incorporation of the silicon germanium channel layer enhances the performance of the PFET transistor by bringing the threshold voltage of the device to a desired level (adjusting the work function to the needs of high-K metal gates).
As noted earlier, a typical integrated circuit product may include millions of PFET transistors. However, not all of the PFET transistors perform the same function. That is, in some cases, it would be desirable for the PFET transistors on a substrate to have different performance characteristics. For example, by adjusting the threshold voltage of the PFET transistors with implantations and different mask layers, one can either form a high threshold voltage (low off-current, low performance due to the reduced on-current) device or a low threshold voltage device (high on-current, high performance, but also higher off-current). For high-K metal gate PFETs this approach has the drawback that very high implant doses and counter-doping are required and still the threshold voltage shift attributed to the dose and thickness chosen for the silicon germanium region would present the major and limiting factor for the achievable threshold voltage range and the transistor performance.
To avoid the drawbacks of high implant doses like e.g. high cost, long processing times and high implant damage of the substrate and to allow a wider range of achievable threshold voltages for the high-K metal gate PFETs, the formation of individual silicon germanium regions tailored for the individual performance requirements of the PFETs is needed.
The present disclosure is directed to various methods of forming PFET devices with different structures and performance characteristics that may at least reduce or eliminate one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming PFET devices with different structures and performance characteristics. In one example, the method includes forming a first recess in a first active region of the semiconducting substrate while masking a second active region of the substrate, forming a first layer of channel semiconductor material for a first PFET transistor in the first recess, performing a first thermal oxidation process to form a first protective layer on the first layer of channel semiconductor material and forming a second recess in the second active region of the semiconducting substrate. The method concludes with the steps of forming a second layer of channel semiconductor material for the second PFET transistor in the second recess and performing a second thermal oxidation process to form a second protective layer on the second layer of channel semiconductor material, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different.
In another example, an illustrative device disclosed herein include a first PFET transistor formed in and above a first active region of a semiconducting substrate, wherein the first PFET transistor comprises a first layer of channel semiconductor material, and a second PFET transistor formed in and above a second active region of the semiconducting substrate, wherein the second PFET transistor comprises a second layer of channel semiconductor material, and wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming PFET devices with different structures and performance characteristics. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to
In general, illustrative trench isolation structures 12 separate the substrate 10 in to two P-active regions 10PA, 10PB wherein PFET transistors 10A, 10B, respectively, will be formed. The trench isolation regions 12 may be formed by performing well known etching, deposition and polishing processes. Although the regions 10PA and 10PB are depicted in the drawings as being adjacent to one another, in practice the regions 10A, 10B may be spaced apart from one another on the substrate 10. In some cases, other types of semiconductor devices, such as NFET devices, memory devices, resistors, etc., may be positioned between the illustrative active regions 10PA, 10PB. Moreover, the size and configurations of the active regions may vary depending upon the particular application, and the active regions 10PA, 10PB need not be of the same size and configuration, although they may be so configured. Although not depicted in the drawings, one or more ion implantation processes may have been performed on the substrate 10 to introduce the desired dopant materials into the active regions 10PA, 10PB such that PFET transistors may be formed in and above the active regions 10PA, 10PB.
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As will be recognized by those skilled in the art after a complete reading of the present application, the methods disclosed herein enable the formation of PFET transistors on a substrate 10 having different structures and difference performance characteristics. For example, the thickness of the semiconductor materials 18, 28 may intentional made to be different so as to change the electrical characteristics of the transistors 10A, 10B. In one illustrative embodiment, the semiconductor material 18 may have a thickness of about 20 nm while the semiconductor material 28 may have thickness of about 10 nm. In general, all other things being equal, a PFET transistor with thicker layer of semiconductor material will tend to exhibit a lower threshold voltage and higher performance as compared to a PFET transistor with a semiconductor material having a lesser thickness. It should also be noted that in some embodiments it may generally be desirable to form the thicker of the semiconductor materials 18, 28 first.
Similarly, the germanium concentration in the semiconductor materials 18, 28 may intentional made to be different so as to change the electrical characteristics of the transistors 10A, 10B. In one illustrative embodiment, the semiconductor material 18 may have a germanium concentration of about 20-25% while the semiconductor material 28 may have a germanium concentration of about 35-40%. In general, all other things being equal, a PFET transistor with a semiconductor material having higher germanium concentration will tend to exhibit a lower threshold voltage and higher performance as compared to PFET transistor with a semiconductor material having a lesser germanium concentration. These two “control knobs”—thickness and germanium concentration of the channel semiconductor materials for the PFET transistors—may be employed in combination or separately to impart the desired electrical performance characteristics on the subject PFET transistors.
More specifically, when the isolation structures 12 were formed, they separated the substrate 10 in to two active regions 10PA, 10PB wherein PFET transistors 10A, 10B, respectively, will be formed, and they also defined an N-active region 10N and a memory region 10M. In the illustrative embodiment described in
At the point of fabrication depicted in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1-19. (canceled)
20. A device, comprising
- a first PFET transistor formed in and above a first active region of a semiconducting substrate, said first PFET transistor comprising a first layer of channel semiconductor material; and
- a second PFET transistor formed in and above a second active region of said semiconducting substrate, said second PFET transistor comprising a second layer of channel semiconductor material, wherein at least one of a thickness of said first and second channel semiconductor materials or a concentration of germanium in said first and second channel semiconductor materials are different.
21. The device of claim 20, wherein said first channel semiconductor material is thicker than said second channel semiconductor material and said concentration of said germanium in said first channel semiconductor material is greater than said concentration of said germanium in said second channel semiconductor material.
22. The device of claim 20, wherein said first channel semiconductor material is thicker than said second channel semiconductor material and said concentration of said germanium in said first channel semiconductor material is less than said concentration of said germanium in said second channel semiconductor material.
23. The device of claim 20, wherein said first channel semiconductor material is thinner than said second channel semiconductor material and said concentration of said germanium in said first channel semiconductor material is greater than said concentration of said germanium in said second channel semiconductor material.
24. The device of claim 20, wherein said first channel semiconductor material is thinner than said second channel semiconductor material and said concentration of said germanium in said first channel semiconductor material is less than said concentration of said germanium in said second channel semiconductor material.
25. The device of claim 20, wherein said concentration of said germanium in said first channel semiconductor material is less than said concentration of said germanium in said second channel semiconductor material.
26. The device of claim 20, wherein said concentration of said germanium in said first channel semiconductor material is greater than said concentration of said germanium in said second channel semiconductor material.
27. The device of claim 20, wherein said first channel semiconductor material is thicker than said second channel semiconductor material.
28. The device of claim 20, wherein said first channel semiconductor material is thinner than said second channel semiconductor material.
29. The device of claim 20, wherein said first and second channel semiconductor materials are comprised of silicon germanium.
30. The device of claim 20, further comprising an embedded DRAM device formed in and above said substrate, said embedded DRAM device having a channel formed in said substrate.
31. A device, comprising
- a first PFET transistor formed in and above a first active region of a semiconducting substrate, said first PFET transistor comprising a first layer of silicon germanium; and
- a second PFET transistor formed in and above a second active region of said semiconducting substrate, said second PFET transistor comprising a second layer of silicon germanium, wherein at least one of a thickness of said first and second layers of silicon germanium or a concentration of germanium in said first and second layers of silicon germanium are different.
32. The device of claim 31, wherein said first layer of silicon germanium is thicker than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is greater than said concentration of said germanium in said second layer of silicon germanium.
33. The device of claim 31, wherein said first layer of silicon germanium is thicker than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is less than said concentration of said germanium in said second layer of silicon germanium.
34. The device of claim 31, wherein said first layer of silicon germanium is thinner than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is greater than said concentration of said germanium in said second layer of silicon germanium.
35. The device of claim 31, wherein said first layer of silicon germanium is thinner than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is less than said concentration of said germanium in said second layer of silicon germanium.
36. The device of claim 31, wherein said concentration of said germanium in said first layer of silicon germanium is less than said concentration of said germanium in said second layer of silicon germanium.
37. The device of claim 31, wherein said concentration of said germanium in said first layer of silicon germanium is greater than said concentration of said germanium in said second layer of silicon germanium.
38. The device of claim 37, wherein said first layer of silicon germanium is thicker than said second layer of silicon germanium.
39. The device of claim 31, wherein said first layer of silicon germanium is thinner than said second layer of silicon germanium.
40. The device of claim 31, further comprising an embedded DRAM device formed in and above said substrate, said embedded DRAM device having a channel formed in said substrate.
41. A device, comprising
- a first PFET transistor formed in and above a first active region of a semiconducting substrate, said first PFET transistor comprising a first layer of silicon germanium; and
- a second PFET transistor formed in and above a second active region of said semiconducting substrate, said second PFET transistor comprising a second layer of silicon germanium, wherein a thickness of said first and second layers of silicon germanium are different and a concentration of germanium in said first and second layers of silicon germanium are different.
42. The device of claim 41, wherein said first layer of silicon germanium is thicker than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is greater than said concentration of said germanium in said second layer of silicon germanium.
43. The device of claim 41, wherein said first layer of silicon germanium is thicker than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is less than said concentration of said germanium in said second layer of silicon germanium.
44. The device of claim 41, wherein said first layer of silicon germanium is thinner than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is greater than said concentration of said germanium in said second layer of silicon germanium.
45. The device of claim 41, wherein said first layer of silicon germanium is thinner than said second layer of silicon germanium and said concentration of said germanium in said first layer of silicon germanium is less than said concentration of said germanium in said second layer of silicon germanium.
46. The device of claim 41, wherein said concentration of said germanium in said first layer of silicon germanium is less than said concentration of said germanium in said second layer of silicon germanium.
47. The device of claim 41, wherein said concentration of said germanium in said first layer of silicon germanium is greater than said concentration of said germanium in said second layer of silicon germanium.
48. The device of claim 47, wherein said first layer of silicon germanium is thicker than said second layer of silicon germanium.
49. The device of claim 41, wherein said first layer of silicon germanium is thinner than said second layer of silicon germanium.
Type: Application
Filed: Mar 13, 2014
Publication Date: Jul 10, 2014
Applicant: GLOBALFOUNDRIES Inc. (Grand Cayman)
Inventors: Hans-Juergen Thees (Dresden), Stephan Kronholz (Dresden), Peter Javorka (Radeburg)
Application Number: 14/208,423
International Classification: H01L 27/088 (20060101); H01L 29/10 (20060101); H01L 27/108 (20060101);