Insulated Gate Field Effect Transistors Of Different Threshold Voltages In Same Integrated Circuit (e.g., Enhancement And Depletion Mode) Patents (Class 257/392)
  • Patent number: 10446686
    Abstract: Techniques that facilitate an asymmetric dual gate fully depleted transistor are provided. In one example, a transistor device includes a semiconductor channel structure, a first gate structure and a second gate structure. The first gate structure comprises a first length. The second gate structure comprises a second length that is different than the first length. The first gate structure is disposed on a first surface of the semiconductor channel structure and the second gate structure is disposed on a second surface of the semiconductor channel structure.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Terry Hook, Kangguo Cheng, Yi Song, Chen Zhang, Xin Miao, Peng Xu
  • Patent number: 10446399
    Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Hoon Kim
  • Patent number: 10446236
    Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The stringer driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 10411088
    Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 10, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
  • Patent number: 10388514
    Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lars Mueller-Meskamp, Stefan Duenkel
  • Patent number: 10388577
    Abstract: A technique relates to a semiconductor device. A first work function metal is in first stack and second stacks, each having nanowires separated by the first work function metal. A mask is on the first stack such that the first work function metal in the first stack is protected while the first work function metal in the second stack is exposed. The mask is undercut by removing a portion of first work function metal in first stack, leaving a gap. A plug is formed in the gap underneath the mask so as to protect the first work function metal in first stack. First work function metal in the second stack is removed, thereby removing the first work function metal from in between the nanowires of the second stack. The mask and plug are removed from first stack. A second work function metal is formed on first and second stacks.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10361193
    Abstract: The present invention provides an integrated circuit formed of tunneling field-effect transistors that includes a first tunneling field-effect transistor in which one of a first P-type region and a first N-type region operates as a source region and the other one operates as a drain region; and a second tunneling field-effect transistor in which one of a second P-type region and a second N-type region operates as a source region and the other one operates as a drain region, the first and second tunneling field-effect transistors being formed in one active region to have the same polarity, the first P-type region and the second N-type region being formed adjacently, the adjacent first P-type region and second N-type region being electrically connected through metal semiconductor alloy film.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 23, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventor: Takahiro Mori
  • Patent number: 10332804
    Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 25, 2019
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Budong You, Zheng Lyu, Xianguo Huang, Chuan Peng
  • Patent number: 10312353
    Abstract: A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10312072
    Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate; a fin extending from the semiconductor substrate; a first charged dielectric layer covering a bottom portion of the fin, the first charged dielectric layer having net fixed first-type charges; a second charged dielectric layer covering the first charged dielectric layer, the second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges; and a gate structure engaging a top portion of the fin.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jin Cai
  • Patent number: 10269917
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Patent number: 10229855
    Abstract: A device includes a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity. The first gate electrode structure includes a first gate insulation layer, a first barrier layer, a first work function material layer formed above the first barrier layer, a second barrier layer formed above the first work function material layer, and a first conductive material formed above the second barrier layer. A second transistor device has a second threshold voltage different than the first threshold voltage and includes a second gate electrode structure positioned in a second cavity defined in the dielectric layer. The second gate electrode structure includes a second gate insulation layer, a second work function material layer, the second barrier layer formed above the second work function material layer, and a second conductive material formed above the second barrier layer.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hoon Kim, Ruilong Xie, Min Gyu Sung, Chanro Park
  • Patent number: 10229910
    Abstract: A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A protective conformal mask layer is deposited over the plurality of fins in the second region, the second region is blocked, and a plurality of fins are formed in the first region of the wafer using a variety of wet and/or dry etching procedures. The protective conformal mask layer protects the plurality of fins in the second region from the variety of wet and/or dry etching procedures that are used to form the plurality of fins in the first region.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isabel C. Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie, Deepika Priyadarshini, Nicole A. Saulnier, Indira P. Seshadri
  • Patent number: 10224244
    Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 5, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Scott E. Thompson, Damodar R. Thummalapally
  • Patent number: 10217841
    Abstract: A method of forming a vertical transport fin field effect transistor (VT FinFET), including, forming a plurality of vertical fins on a substrate, forming a sacrificial liner on at least two of the plurality of vertical fins, forming sidewall spacers on the vertical surfaces of the sacrificial liner, wherein the sidewall spacers are on opposite sides of the at least two of the plurality of vertical fins, and removing a portion of the sacrificial liner to form an l-shaped channel adjacent to each of the at least two of the plurality of vertical fins.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu, Jingyun Zhang
  • Patent number: 10217781
    Abstract: A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 26, 2019
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Mihai Adrian Ionescu, Nilay Dagtekin
  • Patent number: 10170577
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10163621
    Abstract: A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jin Cai
  • Patent number: 10134902
    Abstract: A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10115642
    Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 30, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Yoshikazu Moriwaki
  • Patent number: 10084066
    Abstract: A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first direction. A channel layer is formed on the fin structure. A gate stack including a gate electrode layer and a gate dielectric layer extending in a second direction perpendicular to the first direction is formed over the channel layer covering a portion of the length of the fin structure. The source and drain contacts are formed over trenches that extend into a portion of a height of the fin structure.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ming Lin, Ken-Ichi Goto
  • Patent number: 10074429
    Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 11, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Julien Delalleau
  • Patent number: 10074715
    Abstract: A method for forming a semiconductor device includes determining at least one electrical parameter for each semiconductor device of a plurality of semiconductor devices to be formed in a semiconductor wafer. The method further includes implanting doping ions into device areas of the semiconductor wafer used for forming the plurality of semiconductor devices with laterally varying implantation doses based on the at least one electrical parameter of the plurality of semiconductor devices.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Werner Schustereder, Hans-Joachim Schulze, Hans Weber
  • Patent number: 10068901
    Abstract: A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju Youn Kim, Gi Gwan Park
  • Patent number: 10062764
    Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang, Chun-Ting Chiang, Chih-Wei Lin, Bo-Yu Su, Chi-Ju Lee
  • Patent number: 10062618
    Abstract: Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Takashi Ando, Aritra Dasgupta, Balaji Kannan, Unoh Kwon
  • Patent number: 10056302
    Abstract: A semiconductor device may include a substrate, a p-channel device, and an n-channel device. The p-channel device may include a first metal member, a first dielectric layer positioned between the substrate and the first metal member, a first barrier layer positioned between the first dielectric layer and the first metal member, a first first-type work function layer directly contacting the first barrier layer and positioned between the first barrier layer and the first metal member, and a first second-type work function layer directly contacting both the first first-type work function layer and the first metal member. The n-channel device may include a second metal member, a second dielectric layer positioned between the substrate and the second metal member, and a second second-type work function layer directly contacting both the second dielectric layer and the second metal member.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: August 21, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jie Zhao, Jia Lei Liu, Liang Wang
  • Patent number: 10056935
    Abstract: Switching circuits for wireless applications. In some embodiments, a switching circuit can include a common node and a plurality of series arm switches with each being capable of connecting the common node and a respective signal node. The switching circuit can further include a shunt arm switch for each of the series arm switches. The shunt arm switch can be capable of connecting the signal node of the respective series arm switch to a ground. The switching circuit can further include a compensation circuit coupled to the common node and configured to compensate for a parasitic effect resulting from some or all of the series arm switches and the shunt arm switches.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 21, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Junhyung Lee
  • Patent number: 10020309
    Abstract: At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 10020228
    Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 9966468
    Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Chen Chan, Yi-Fan Li, Li-Wei Feng, Ming-Hua Chang, Yu-Shu Lin, Shu-Yen Chan
  • Patent number: 9960170
    Abstract: Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeik Kim, Kiseok Lee, Keunnam Kim, Bong-Soo Kim, Jemin Park, Chan-Sic Yoon, Yoosang Hwang
  • Patent number: 9947771
    Abstract: A method of fabricating a thin film transistor includes forming a substrate having first and second regions, a semiconductor layer pattern formed in the first region and the second region, and a first gate insulating layer pattern formed on a channel region of the semiconductor layer pattern of the first region. A second gate insulating layer is formed on the substrate, a first conductive layer pattern is formed above the channel region of the first region and above the semiconductor layer pattern of the second region, and an inter-layer insulating layer is formed on the substrate. A second conductive layer pattern is formed in the first region and above the first conductive layer pattern of the second region. The second conductive layer pattern of the first region is coupled to the semiconductor layer pattern of the first region through the second gate insulating layer and the inter-layer insulating layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 17, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Byoung-Keon Park
  • Patent number: 9922984
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Patent number: 9875940
    Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: January 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hoon Kim, Ruilong Xie, Min Gyu Sung, Chanro Park
  • Patent number: 9859375
    Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9837553
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (VFETs) and methods of manufacture. The VFET includes: one or more vertical fin structures; a source region positioned at a first location on a top surface of the one or more vertical fin structures; a drain region positioned at a second location on the top surface of the one or more vertical fin structures at a predetermined distance away from the source region, along a length thereof; and a gate channel along the predetermined distance and in electrical contact with the source region and the drain region.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, John H. Zhang, Haigou Huang
  • Patent number: 9805990
    Abstract: An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andres Bryant, Edward J. Nowak, Robert R. Robison
  • Patent number: 9773680
    Abstract: Devices and methods of fabricating scaled SRAM with flexible active pitch are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a first portion and a second portion, including a plurality of layers and a patterned mandrel; forming a first set of spacers surrounding the patterned mandrel; etching the dielectric layer; depositing a photoresist layer; opening the photoresist layer over the first portion and not the second portion, removing the patterned mandrel in the open areas; etching the dielectric layer in the open areas; removing the photoresist layer, the remaining patterned mandrels, and the first set of spacers in the first and second portion, etching the silicon layer and MTO layer to form a pattern; forming a second set of spacers around the pattern; and etching a set of fins into the substrate and oxide layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: September 26, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Jinping Liu
  • Patent number: 9748152
    Abstract: Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second spacer height of a second sidewall spacer adjacent the dummy gate based upon a height of a photoresist as measured using optical critical dimension (OCD) spectroscopy. When the photoresist is sufficiently uniform, a hard mask etch is performed to remove a hard mask from the dummy gate and to remove portions of sidewall spacers of the dummy gate. A gate electrode is formed between the first sidewall spacer and the second sidewall spacer to form a substantially uniform gate. Controlling gate formation based upon photoresist height as measured by OCD spectroscopy provides a non-destructive manner of promoting uniformity.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Lun Lu, Tzu-Chung Wang
  • Patent number: 9712146
    Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 18, 2017
    Assignee: University of Notre Dame du Lac
    Inventors: Behnam Sedighi, Michael Niemier, Xiaobo Sharon Hu, Indranil Palit
  • Patent number: 9685520
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shuo-Lin Hsu, Hsin-Ta Hsieh, Chun-Chia Chen, Chen-Chien Li, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
  • Patent number: 9679817
    Abstract: A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Po-Nien Chen, Bao-Ru Young
  • Patent number: 9673207
    Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: June 6, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Yusuke Yoshida
  • Patent number: 9666574
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Yi Lee, Shih-Fen Huang, Pei-Lun Wang, Dah-Chuen Ho, Yu-Chang Jong, Mohammad Al-Shyoukh, Alexander Kalnitsky
  • Patent number: 9659929
    Abstract: A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating first semiconductor fins. The depletion FinFET cells include second gate structures separating second semiconductor fins. Between the first and second gate structures a connection structure separates the first semiconductor fins from the second semiconductor fins. The connection structure has a specific conductance which is higher than a specific conductance in the second semiconductor fins.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Dresden GmbH
    Inventor: Rolf Weis
  • Patent number: 9640540
    Abstract: An integrated circuit includes first and second SRAM cells. The first SRAM cell includes first and second pull-up devices, first and second pull-down devices configured with the first and second pull-up devices to form first and second cross-coupled inverters, first and second pass-gate devices configured with the first and second cross-coupled inverters for writing data, a read pull-down device coupled to the first inverter, and a read pass-gate device coupled to the read pull-down device. The second SRAM cell includes third and fourth pull-up devices, and third and fourth pull-down devices configured with the third and fourth pull-up devices to form third and fourth cross-coupled inverters. Work function layers of gates of the first pull-up device, first pull-down device, and third pull-up device have a first work function, a second work function, and a third work function respectively. The first, second, and third work functions are different from each other.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 2, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9640524
    Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
  • Patent number: 9634124
    Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Sameer Pradhan, Jeanne Luce
  • Patent number: RE47640
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama