Insulated Gate Field Effect Transistors Of Different Threshold Voltages In Same Integrated Circuit (e.g., Enhancement And Depletion Mode) Patents (Class 257/392)
  • Patent number: 11330526
    Abstract: The present invention provides a system and method for optimizing power consumption in video communication in mobile devices. The system comprises a video codec encoder module, a video codec decoder module and post-processing filtering module (Deblocking filter) modules. The post-processing modules are implemented on a DSP/VLIW processor, while the video encoder and decoder modules are implemented on a CPU with SIMD extensions. This pipelined implementation of modules in multi-core reduces current consumption in the SoC by up to 50 percent compared to an implementation of the modules in a single/multiple DSP/VLIW core. The significant reduction in current consumption of the modules enables reduction of power consumption in the video call time. Thus, the invention provides a simple method of optimizing power consumption by multi core implementation of the modules in a video call in mobile devices.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 10, 2022
    Assignee: TriSpace Technologies (OPC) Pvt. Ltd.
    Inventor: Narasimhan Vijay Anand
  • Patent number: 11309387
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11302691
    Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
  • Patent number: 11282842
    Abstract: A static random access memory device includes a first gate, a second gate, and a third gate. The first gate extends in a first direction from a standard threshold voltage region of a substrate to a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. The second gate is disposed in the standard threshold voltage region of the substrate. The third gate is disposed in the low threshold voltage region of the substrate. The standard threshold voltage region has a boundary at an edge of the second gate. The boundary extends in a second direction different from the first direction and is crossed by the first gate. A distance between the boundary and the first gate is different from a distance between the boundary and the second gate.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo
  • Patent number: 11201059
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Patent number: 11195918
    Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • Patent number: 11189522
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan Hsiao, Yee-Chia Yeo, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 11165424
    Abstract: A field-effect transistor system is provided that comprises a field-effect transistor having a back-gate terminal that can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage additionally being present at the field-effect transistor, and a drain current flowing through the field-effect transistor. In addition, the field-effect transistor system includes a control unit connected to the back-gate terminal, which unit is set up to set the drain current flowing through the field-effect transistor to a setpoint current via a controlling of the back-gate voltage at the back-gate terminal, the controlling of the back-gate voltage taking place as a function of at least the gate-source voltage. In addition, a method is provided for setting a drain current of a field-effect transistor.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 2, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Gregor Tretter, Reiner Schnitzer, Thomas Schwarzenberger
  • Patent number: 11152250
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Patent number: 11145536
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Patent number: 11145646
    Abstract: Restraining a reduction in an electric current detection accuracy, which is due to the temperature difference between an output MOS transistor and a sense MOS transistor, and easing a limitation on the layout of the sense MOS transistor. A semiconductor device includes: an output MOS transistor that has an output transistor portion including a source, a gate, and a drain formed on a semiconductor chip, and outputs an electric current for driving an external load; and a sense MOS transistor that has a sense transistor portion including a source, a gate, and a drain formed on the semiconductor chip, and having a width equal to a transverse width of the output transistor portion, and that detects the electric current output from the output MOS transistor.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 12, 2021
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Shinichirou Wada, Katsumi Ikegaya
  • Patent number: 11145677
    Abstract: According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shawn P. Fetterolf
  • Patent number: 11043491
    Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shun-Jang Liao, Chia-Chun Liao, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 11031397
    Abstract: Integrated circuit having an integration layout and the manufacturing method thereof are disclosed herein. An exemplary integrated circuit (IC) comprises a first cell including one or more first type gate-all-around (GAA) transistors located in a first region of the integrated circuit; a second cell including one or more second type GAA transistors located in the first region of the integrated circuit, wherein the second cell is disposed adjacently to the first cell, wherein the first type GAA transistors are one of nanosheet transistors or nanowire transistors and the second type GAA transistors are the other one of nanosheet transistors or nanowire transistors; and a third cell including one or more fin-like field effect transistors (FinFETs) located in a second region of the integrated circuit, wherein the second region is disposed a distance from the first region of the integrated circuit.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11018137
    Abstract: A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Beomyong Hwang, Min Hee Cho, Hei Seung Kim, Mirco Cantoro, Hyunmog Park, Woo Bin Song, Sang Woo Lee
  • Patent number: 10872968
    Abstract: A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10847424
    Abstract: A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara Tapily, Jeffrey Smith, Gerrit Leusink
  • Patent number: 10797151
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
  • Patent number: 10797174
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Patent number: 10777552
    Abstract: The disclosure relates to a method of simultaneous fabrication of an MOS transistor of SOI type, and of first and second transistors on bulk substrate, comprising: a) providing a semiconductor layer on an insulating layer covering a semiconductor substrate; b) forming a mask comprising, above the location of the second transistor, a central opening which is less wide than the second transistor to be formed; c) plumb with the opening, entirely etching the semiconductor layer and insulating layer, hence resulting in remaining portions of the insulating layer at the location of the second transistor; d) growing the semiconductor by epitaxy as far as the upper level of the semiconductor layer; e) forming isolating trenches; and f) forming the gate insulators of the transistors, the gate insulator of the second transistor comprising at least one part of the said remaining portions of the insulating layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 15, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Franck Julien
  • Patent number: 10756087
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 10741449
    Abstract: A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 11, 2020
    Assignee: Tessera, Inc.
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthiharan, John Zhang
  • Patent number: 10720516
    Abstract: Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 10714619
    Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10699940
    Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Yuan Ku, Chih-Ming Sun, Chun-Fai Cheng
  • Patent number: 10692990
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • Patent number: 10692778
    Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Junli Wang, Heng Wu
  • Patent number: 10686058
    Abstract: A method of manufacturing a trench MOSFET can include: forming an epitaxial semiconductor layer having a first doping type on a semiconductor substrate; forming a trench extending from a first surface of the epitaxial semiconductor layer to an internal portion of the epitaxial semiconductor layer; forming a first insulating layer and a shield conductor occupying a lower portion of said trench, where the first insulating layer is located on a lower sidewall surface and a bottom surface of the trench and separates the shield conductor from the epitaxial semiconductor layer; forming a second insulating layer covering a top surface of said shield conductor, where the second insulating layer is patterned by using a hard mask; forming a gate dielectric layer and a gate conductor occupying an upper portion of the trench; and forming a body region, a source region, and a drain electrode.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: June 16, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Jinyong Cai, Zhongping Liao
  • Patent number: 10658247
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu
  • Patent number: 10637472
    Abstract: A reference voltage generation circuit for use with current mode logic includes a first transistor of a first conductivity type configured to operate as a diode-connected resistor with a source terminal coupled to a first voltage supply terminal for conducting a supply voltage and a gate terminal coupled to a drain terminal. Second and third transistors of a second conductivity type are coupled in series between the drain terminal of the first transistor and a second voltage supply terminal. Gate terminals of the second and third transistors coupled to the gate terminal of the first transistor. A reference voltage is obtained between the second and third transistors. The first and second NMOS transistors are sized such that they remain in sub-threshold mode operation during operation with an expected range of the supply voltage. Current mode logic circuits are also provided using the reference voltage generation circuit.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: April 28, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aditya Mitra, Animesh Jain
  • Patent number: 10629700
    Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Shun Liao, Huai-Tei Yang, Wang Chun-Chieh, Yueh-Ching Pai, Chun-I Wu
  • Patent number: 10629620
    Abstract: According to embodiments of the present invention, a semiconductor device includes a first transistor located on a first fixed charge dielectric layer and a second transistor located on a second fixed charge dielectric layer. The first fixed charge dielectric layer and the second fixed charge dielectric layer are differently charged such that the first transistor and the second transistor have different threshold voltages.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shawn P. Fetterolf
  • Patent number: 10622264
    Abstract: A technique relates to a semiconductor device. A first work function metal is in first stack and second stacks, each having nanowires separated by the first work function metal. A mask is on the first stack such that the first work function metal in the first stack is protected while the first work function metal in the second stack is exposed. The mask is undercut by removing a portion of first work function metal in first stack, leaving a gap. A plug is formed in the gap underneath the mask so as to protect the first work function metal in first stack. First work function metal in the second stack is removed, thereby removing the first work function metal from in between the nanowires of the second stack. The mask and plug are removed from first stack. A second work function metal is formed on first and second stacks.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10587233
    Abstract: An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 10, 2020
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Roda Kanawati
  • Patent number: 10546787
    Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • Patent number: 10510750
    Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first transistor gate stack is disposed in a low voltage region defined on a substrate. The first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate. A third transistor gate stack is disposed in a high voltage region defined on the substrate. The third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate. The third gate dielectric comprises an oxide component and a first interlayer dielectric layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
  • Patent number: 10510621
    Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zoe Chen, Ching-Hwanq Su, Cheng-Lung Hung, Cheng-Yen Tsai, Da-Yuan Lee, Hsin-Yi Lee, Weng Chang, Wei-Chin Lee
  • Patent number: 10510617
    Abstract: Embodiments are directed to a complementary metal oxide semiconductor having source and drain contacts formed using trench. An n-type field effect transistor (NFET) includes a p-type semiconductor fin vertically extending from an n-type bottom source or drain region disposed on the substrate. A p-type FET (PFET) includes an n-type semiconductor fin vertically extending from a p-type bottom source or drain region disposed on the substrate. A first gate of the NFET is formed around a channel region of the p-type semiconductor fin and a second gate of the PFET is formed around a channel region of the n-type semiconductor fin. The first gate and the second gate include a dipole layer. The NFET and PFET each has a threshold voltage of about 150 mV to about 250 mV and a difference between the threshold voltages of the NFET and PFET is less than about 50 mV.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita
  • Patent number: 10497571
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Patent number: 10446686
    Abstract: Techniques that facilitate an asymmetric dual gate fully depleted transistor are provided. In one example, a transistor device includes a semiconductor channel structure, a first gate structure and a second gate structure. The first gate structure comprises a first length. The second gate structure comprises a second length that is different than the first length. The first gate structure is disposed on a first surface of the semiconductor channel structure and the second gate structure is disposed on a second surface of the semiconductor channel structure.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Terry Hook, Kangguo Cheng, Yi Song, Chen Zhang, Xin Miao, Peng Xu
  • Patent number: 10446236
    Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The stringer driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 10446399
    Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Hoon Kim
  • Patent number: 10411088
    Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 10, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
  • Patent number: 10388577
    Abstract: A technique relates to a semiconductor device. A first work function metal is in first stack and second stacks, each having nanowires separated by the first work function metal. A mask is on the first stack such that the first work function metal in the first stack is protected while the first work function metal in the second stack is exposed. The mask is undercut by removing a portion of first work function metal in first stack, leaving a gap. A plug is formed in the gap underneath the mask so as to protect the first work function metal in first stack. First work function metal in the second stack is removed, thereby removing the first work function metal from in between the nanowires of the second stack. The mask and plug are removed from first stack. A second work function metal is formed on first and second stacks.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10388514
    Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lars Mueller-Meskamp, Stefan Duenkel
  • Patent number: 10361193
    Abstract: The present invention provides an integrated circuit formed of tunneling field-effect transistors that includes a first tunneling field-effect transistor in which one of a first P-type region and a first N-type region operates as a source region and the other one operates as a drain region; and a second tunneling field-effect transistor in which one of a second P-type region and a second N-type region operates as a source region and the other one operates as a drain region, the first and second tunneling field-effect transistors being formed in one active region to have the same polarity, the first P-type region and the second N-type region being formed adjacently, the adjacent first P-type region and second N-type region being electrically connected through metal semiconductor alloy film.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 23, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventor: Takahiro Mori
  • Patent number: 10332804
    Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 25, 2019
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Budong You, Zheng Lyu, Xianguo Huang, Chuan Peng
  • Patent number: 10312072
    Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate; a fin extending from the semiconductor substrate; a first charged dielectric layer covering a bottom portion of the fin, the first charged dielectric layer having net fixed first-type charges; a second charged dielectric layer covering the first charged dielectric layer, the second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges; and a gate structure engaging a top portion of the fin.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jin Cai
  • Patent number: 10312353
    Abstract: A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: RE47640
    Abstract: A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Reika Ichihara, Yoshinori Tsuchiya, Masato Koyama, Akira Nishiyama