PHASED-ARRAY CHARGE PUMP SUPPLY
A charge pump system and method that may provide large supply voltages and currents with reduced ripple voltage at reduced ripple frequency. The charge pump system may include an array of charge pumps and a delay pipeline. The array of charge pumps may include a plurality of charge pumps. The delay pipeline may include a plurality of delay elements. The delay elements may respond to a global trigger signal to output a trigger signal to the array of charge pumps. Respective charge pumps may fire in response to the trigger signal.
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This application is a continuation of U.S. application Ser. No. 13/214,904 filed on Aug. 22, 2011, which claims the benefit of U.S. Provisional Application Ser. No. 61/454,744 filed on Mar. 21, 2011, the entire contents of which are incorporated herein by reference.
FIELDCharge pumps are well known devices. In integrated circuit (IC) implementations, components on the IC may have voltage or current requirements that differ from supply voltage or current sources supplied to the IC. Charge pumps may be used to convert the supplied current or voltage to a different voltage or current from the IC supply voltage. This is beneficial because it reduces customer cost, and power requirements for the IC. Charge pumps can be used to create supplies greater or less than the supply voltage or negative supplies generated from positive supply voltages.
BACKGROUNDHowever, at times a large voltage or current value may be required for a particular application. This is typically accomplished using a large capacitor or inductor external to the IC. Commonly, as the voltage and current outputs rise, the respective noise also rises. In addition, as loads to the IC change, the voltage droop may become excessive due to the large voltages and/or currents being provided. Alternatively, fluctuation, or more commonly, “ripple”, in the output current or voltage value may be significant. If the ripple is significant, it can cause errors in the loads supplied with the output voltages or currents. The rate of change of the ripple voltage is the ripple frequency.
One known method of reducing voltage or current ripple is to interleave a number of charge pumps. The number of charge pumps maintains the output voltage or current supply as each charge pump discharges and recharges according to a clock signal. Interleaving requires a number of clock signals to control the firing of the number of charge pumps. The firing of the number of charge pumps may actually increase the voltage ripple as each individual charge pump fires imprecisely due to failure to synchronize the number of clock signals. The management of the number of different clock signals requires a complex control device. Furthermore, the additional clock inputs and related connections also consume additional real estate on the IC, which increases cost as well as makes for a larger IC. Also, interleaving may not provide a large voltage or current that may be needed by a particular circuit application or configuration.
Accordingly, there is a need for a charge pump configuration that supplies large voltage or current without the complex control and multitude of inputs of an interleaved solution.
A charge pump system may include a plurality of charge pumps connected in an array, and a plurality of delay elements also connected in an array. A respective one of the delay elements connected to an enabling input of a respective one of the plurality of charge pumps. The respective delay elements may be supplied with a trigger signal according to which the charge pumps may be enabled to fire in a cascaded manner after some time delay to separately output a voltage to a common output connection of the plurality of charge pumps. The trigger signal supplied to the delay elements may be a single one-time input signal, or a single clock signal. The trigger signal may repeat only after all of the charge pumps have provided an output signal.
The delay pipeline 120 may have an input to receive the trigger signal TRG. The trigger signal TRG may be a periodic clock signal, a single impulse signal (e.g., a “one-shot”), or any form of signal suitable to initiate the firing of the charge pumps 110.1 to 110.N. The delay pipeline 120 may include a plurality of outputs 120.1 to 120.N for outputting a firing signal output from respective delay elements 130.0 to 130.N−1 to each of the respective charge pumps 110.1 to 110.N. For example, the delay elements 130.0 to 130.N−1 may be connected in series to provide incremented delay to the input global trigger signal TRG. As a result, the delayed trigger signal (e.g., TRG1, TRG2 . . . ) may be offset from each other by a time period (a). The charge pumps 110.1 to 110.N may be characterized by a decay time that is longer than a delay time of the delay elements 130.0 to 130.N−1. In other words, the output voltage or current may overlap for a time period from each charge pump 110.1 to 110.N as each charge pump fires. As a result, the output voltage or current may remain substantially constant.
The delay elements 130.0 to 130.N may be implemented using inverters, switches, delay lines or other circuit components (e.g., RC delay). For example, a single inverter has an inherent delay in the transistor switching of the inverter; the delay elements 130.0-130.N−1 each may be made of one or more inverters. When the system 100 is fabricated as an integrated chip, the inverters will share common circuit characteristics, and hence a similar time delay.
The delay elements 130.0 to 130.N−1 may be configured either in an open loop configuration as shown, or as a ring oscillator. The cascaded delay elements 130.0 to 130.N−1 may be arranged, for example, individually in series, or in groups of delay elements. Each delay element 130.0 to 130.N−1 may provide the same delay period of Δt.
During operation, the global trigger signal TRG may be applied to the input to the delay pipeline 120. In response to the application of global trigger signal TRG, a trigger signal TRG1 may be output from delay element 130.0 of the delay pipeline 120 via the output 120.1. After a predetermined delay (Δt) due to delay element 130.0, the timing signal TRG1 may cause the first charge pump 110.1 to fire, and output a signal VOUT. The timing signal TRG1 may be applied to delay element 130.1, and, after a predetermined delay (Δt), output a trigger signal TRG2 from the output 120.2 of the delay pipeline 120. The trigger signal TRG2 may now be delayed a time period of 2Δt from the initial application of the global trigger signal TRG to the delay pipeline 120. The output 120.2 may provide the output trigger signal TRG2 to the charge pump 110.2 and to delay element 130.2. The charge pump 110.2 may fire in response to the trigger signal TRG2, and output a signal VOUT. The delay element 130.2 may also respond to the output signal from delay element 130.1 and after an inherent delay, output a trigger signal TRG3 via delay pipeline output 120.3 to the charge pump 110.3 and to delay element 130.3. As a result, charge pump 110.3 may fire and output a signal VOUT, and delay element 130.3 may output a trigger signal after a delay an output signal. This process may continue until delay element 130.N−1 outputs delayed signal TRGN, which is output from delay pipeline output 120.N to charge pump 110.N. The charge pump 110.N may fire in response to the trigger signal TRGN, and output a signal VOUT.
Operation of the charge pump system 100 may be arranged such that all of the charge pumps 110.1 to 110.N fire within one clock cycle, or some other predetermined period of time. In certain embodiments, the charge pumps 110.1 to 110.N may be characterized by a decay time that is longer than a delay time of the delay elements 130.1-130N−1. With this configuration and timing for the firing of each respective charge pump, a voltage, or current, of sufficient magnitude can be supplied to the load with minimal ripple and substantially no droop. If the delay elements 130.1 to 130.N−1 are arranged in a ring oscillator configuration, the above sequence may repeat until interrupted by another control signal, for example.
In certain situations, the delay elements and charge pumps may not provide consistent performance from one delay element to the next, or one charge pump to the next for various reasons. If the non-consistent performance occurs at a regular interval, it may generate an error that may be propagated upstream, and may, perhaps, be amplified. As a result, errors may occur at the output of the charge pump system. Different techniques may be applied to mitigate the potential for these types of errors to occur. For example, a first technique may be to randomize the selection a respective charge pump to be fired, and a second may be to randomize the delay applied to the firing signals applied to respective charge pumps.
In the embodiment illustrated in
The delay pipeline 210 may include inputs for a timing signal TRG and a bias signal BIAS.
The timing signal TRG may begin the firing sequence for the charge pump array 230. The bias signal BIAS may be applied to the delay elements D0-DN to adjust the delay of each delay element D0-DN. For example, the bias signal BIAS may be applied to a back gate of transistor used in an inverter implementation of the delay element D0-DN. Although shown as a single delay signal, each delay element D0-DN could have an individual bias signal applied to it. The choice of a particular bias level may be randomized. The delay pipeline 210 may be coupled to routing system 220. Routing system 220 may have inputs for signals TRG1-TRGN output from the delay pipeline 210, and an input for a routing control signal RC. The routing system 220 may be coupled to the charge pump array 230. The routing system 220 may be configured to change the firing of the respective charge pumps from cycle to cycle to provide better error mitigation.
In response to the TRG signal, the delay pipeline 210 may sequentially generate trigger signals TRG1-TRGN that are input to the routing system 220. The routing system 220 may include a controller 225, an input of a routing control RC signal, a plurality of inputs from the delay pipeline 210, a plurality of outputs to the charge pump array 230, logic devices 220.1-220.N, which may be multiplexers. The routing control signal RC may be a digital code word. The controller 225 may interpret the digital code word and, based on the interpretation, route a trigger signal (e.g., TRG1) to a respective charge pump in the charge pump array 230.
For example with reference to
The routing control signal RC may be provided by an external or internal controller, and may change so charge pumps within the charge pump array 230 may fire sequentially or non-sequentially (i.e., randomized) to provide either a voltage or current signal.
The cascaded delay elements 320.0-320.N−1 may provide a delayed trigger signal from one delay element to the next. The time delay of each delay element 320.0-320. N may be the same, or may be adjusted by application of a delay adjust signal, such as delay adjust X-0 to delay adjust X-N−1. Each delay element 320.0-320.N−1 may have an individual delay adjustment that allows the delay for each delay element to be individually set. For example, in an implementation in which the delay elements 320.0-320.N−1 are implemented using inverters, the delay of delay element 320.0 may be adjusted by applying the delay adjust X-0 signal to a back gate of a transistor in the inverter of delay element 320.0. Alternatively, in a delay line implementation, the delay adjust X-0 signal may actuate a switch that adds or deletes additional delay line segments to the overall delay line. As shown, each delay element 320.0-320.N−1 may have an individual delay adjust X-0-delay adjust X-N−1. The delay elements 320.0-320.N−1 may be implemented using inverters, delay lines or RC circuits.
The trigger signal TRG1-TRGN output from delay pipeline 320 may be input to intermediate delay 315, which may be coupled to the delay pipeline 320 and to respective charge pumps 310.1 to 310.N. The intermediate delay 315 may include delay elements 315.1 to 315.N. The delay elements 315.1 to 315.N may be implemented using inverters, delay lines or RC circuits. Similar to the delay elements 320.0-320.N-1, each of the delay elements 315.1 to 315.N may also have individual delay adjustments, such as delay adjust Y-0 to delay adjust Y-N−1.
In operation, the global trigger signal TRG may be applied to the delay pipeline 320. The delay element 320.0 may delay the global trigger signal TRG for a predetermined time delay based the delay element's 320.0 preset delay including any adjustment (increase or reduction) to the delay in response to the delay adjust X-0 signal. After the predetermined time delay, the delay element 320.0 may output a delayed trigger signal TRG1 to intermediate delay 315 and to delay element 320.1. The delayed trigger signal TRG1 may be received at an input to intermediate delay element 315.1 of the intermediate delay 315. After a preset delay (which may be individually adjusted by the delay adjust Y-1 signal), the intermediate delay element 315.1 may output a delayed trigger signal TRG1″ for firing the charge pump 310.1. In response to receiving the delayed trigger signal TRG1″, the charge pump 310.1 may fire and output a voltage/current signal VOUT. The voltage/current signal VOUT may be provided to a load. With respect to the delayed trigger signal TRG1 applied to delay element 330.1, delay element 330.1 may further delay trigger signal TRG1 for a predetermined time period including any delay adjustment in response to the delay adjust X-1 signal. Delay element 330.1 may output a delayed trigger signal TRG2 to the intermediate delay 315 and to delay element 330.2. The delayed trigger signal TRG2 applied to intermediate delay 315 may be input to intermediate delay element 315.2. Intermediate delay element 315.2 may delay outputting a trigger signal to charge pump 310.2 in response to its set delay including any adjustment (increase or reduction) to the delay in response to the delay adjust Y-1 signal. After the predetermined time period, the intermediate delay element 315.2 may output a delayed trigger signal TRG2″ for firing the charge pump 310.2. This process may continue for the firing of charge pumps 310.3-310.N that may have delayed trigger signals TRG3″-TRGN″ applied to them.
The individual delay adjustments delay adjust Y-0 to delay adjust Y-N−1 signals may set the individual delays of the intermediate delay elements 315.1-315.N. For example, the delay elements 315.1-315.N may be implemented using transistors configured as inverters, and the respective delay adjust signal may be applied to a back gate of the respective transistors thereby effecting operation of the inverter and the inverter's delay. The plurality of different combinations of delay adjustment of the delay elements 320.0-320.N−1 in the delay pipeline 320 with the delay adjustment of the delay elements 315.1-315.N of the intermediate delay 315 provide numerous possibilities for overcoming the effects of erroneous signals in the signal chain.
Several features and aspects of the present invention have been illustrated and described in detail with reference to particular embodiments by way of example only, and not by way of limitation. Those of skill in the art will appreciate that alternative implementations and various modifications to the disclosed embodiments are within the scope and contemplation of the present disclosure.
Claims
1. A charge pump system, comprising:
- a first delay element and a second delay element, the first delay element having an input to receive a global trigger signal and an output coupled to an input of the second delay element;
- a first intermediate delay element and a second intermediate delay element having inputs coupled to outputs of the first and second delay elements, respectively;
- a first charge pump and a second charge pump having outputs coupled to a common output node and inputs coupled to outputs of the first and second intermediate delay elements, respectively, wherein each delay element includes an input for separately setting an individual delay for each respective delay element independently of the delay set for any other delay element.
2. The charge pump system of claim 1, wherein the first and second delay elements impose delays on the received global trigger signal based on the individually set delays of the first and second delay elements, respectively.
3. The charge pump system of claim 1, wherein the first and second intermediate delay elements impose delays on signals outputted by the first and second delay elements based on the individually set delays of the first and second intermediate delay elements, respectively.
4. The charge pump system of claim 1, wherein the set delay for at least one delay element is not equal to the set delay of at least one other delay element.
5. The charge pump system of claim 1, wherein the set delay for at least one delay element is adjusted for a subsequently received global trigger signal.
6. The charge pump system of claim 1, wherein the inputs of the first and second charge pumps are directly coupled to the outputs of the first and second intermediate delay elements, respectively.
7. The charge pump system of claim 1, wherein the inputs of the first and second intermediate delay elements are directly coupled to the outputs of the first and second delay elements, respectively.
8. A charge pump system, comprising:
- a plurality of charge pumps each having an output connected to a common node and having an input for a trigger signal,
- a chain of delay elements, a first delay element having an input for a global trigger signal, each delay element to impose an incremental delay on propagation of the trigger signal as it progresses through the chain;
- a plurality of intermediate delay elements coupled between the charge pumps and the chain of delay elements to provide an additional delay to the trigger signal output from respective delay elements in the chain of delay elements prior to outputting a delayed trigger signal to inputs of the charge pumps,
- wherein the delay elements in the chain of delay elements and the intermediate delay elements in the plurality of intermediate delay elements each have an individual delay adjustment input that allows the respective delay of each delay element to be separately adjusted independently of the delay set for any other delay element.
9. The charge pump system of claim 8, wherein the delay set for at least one delay element is not equal to the delay set for any other delay element.
10. A method of controlling a charge pump system, comprising:
- applying a global trigger signal to a delay pipeline, the delay pipeline including a plurality of delay elements;
- delaying the global trigger signal for a predetermined delay time period by a first delay element in the delay pipeline;
- outputting a first delayed trigger signal from the delay pipeline, and to a second delay element in the delay pipeline;
- in response to the first delayed trigger signal firing a first charge pump to generate an output signal for a time duration;
- outputting a second delayed trigger signal from the delay pipeline to a second charge pump in the charge pump array; and
- in response to the second delayed trigger signal, firing the second charge pump to generate an output signal for a time duration,
- further comprising separately adjusting delay time periods of each of the plurality of delay elements independently from one another with individual delay adjustments of each of the plurality of delay elements.
11. The method of claim 10, further comprising:
- applying the first delayed trigger signal to the first charge pump indicated by a routing control signal, wherein the first charge pump is randomly selected based on the routing control signal.
12. The method of claim 10, further comprising:
- reapplying the global trigger signal after all charge pumps in the charge pump array have received a trigger signal to fire.
13. The method of claim 10, wherein the time duration in which the first charge pump generates an output signal is longer than the predetermined delay time period.
14. The method of claim 10, wherein the first delayed trigger signal output from the delay pipeline is output to a first charge pump in a charge pump array.
15. The method of claim 10, further comprising:
- receiving at an intermediate delay a trigger signal output from the delay pipeline, wherein the intermediate delay includes a plurality of delay elements;
- delaying the trigger signal for an additional delay period; and
- outputting additionally delayed trigger signals to respective charge pumps in a charge pump array.
16. The method of claim 15, wherein a pseudo-random adjustment of each of the delay elements in the delay pipeline and/or the delay elements in the intermediate delay is performed by separately adjusting the individual delay on each delay element in both the delay pipeline and the intermediate delay independently.
17. The method of claim 15, wherein a pseudo-random adjustment of the delay elements in the delay pipeline and/or the delay elements in the intermediate delay is performed by separately adjusting the delay on all of the delay elements at once in both the delay pipeline and the intermediate delay.
18. The method of claim 10, wherein separately adjusting delay periods further comprises setting a delay of at least one delay element of the plurality of delay elements to be different from a delay of at least one other delay element of the plurality of delay elements.
19. A charge pump system, comprising:
- a plurality of charge pumps each having an output connected to a common node and having an input for a trigger signal,
- a chain of delay elements, a first delay element having an input for a global trigger signal, each delay element to impose an incremental delay on the propagation of the trigger signal as it progresses through the chain;
- a routing system coupled between the charge pumps and the chain of delay elements to route the trigger signal from an output of respective delay elements to inputs of the charge pumps according to a control signal, wherein the routing system comprises a plurality of multiplexors, each multiplexor coupled to all outputs of the chain of delay elements and having an output coupled to a corresponding one of the plurality of charge pumps.
20. The charge pump system of claim 19, wherein the routing control signal determines which multiplexor is to pass the trigger signal received from one of the outputs of the chain of delay elements to the corresponding one of the plurality of charge pumps.
Type: Application
Filed: Aug 4, 2014
Publication Date: Nov 20, 2014
Applicant: ANALOG DEVICES, INC. (Norwood, MA)
Inventors: Eric SIRAGUSA (Poway, CA), Franklin MURDEN (Roan Mountain, TN), Jonathan AUDY (Monte Sereno, CA)
Application Number: 14/450,380
International Classification: G05F 3/02 (20060101);