Abstract: This application relates to methods and apparatus for DC voltage conversion. A DC converter (100) is described, with a charge pump circuit comprising a plurality of charge pump stages (1401, 1402-1, 1402-2) each charge pump stage comprising connections for respective first and second capacitors for that stage (C1A, C1B; C2A, C2B; C3A, C3B). The charge pump also has a switch network, wherein the switch network comprises, between each successive stage, four switching paths (S7AA, S7AB, S7Ba, S7BB; S6AA, S6AB, S6Ba, S6BB) for separately connecting a respective first electrode of each of the first and second capacitors of one stage to a first electrode either of the first and second capacitors of the preceding stage, so that the relevant capacitor of the one stage can be charged by the relevant capacitor of the preceding stage.

Abstract: The disclosure relates to a transducer assembly like a microphone including a bias circuit having a charge pump and a filter circuit coupled to a transducer. The filter circuit includes a voltage-controlled resistor located between an output of the charge pump and the transducer, and a capacitor coupled to the voltage-controlled resistor opposite the charge pump, wherein the bias circuit is configured with a larger bandwidth for faster settling during transient operation than during steady-state operation.

Abstract: In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.

Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

Abstract: Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

Abstract: In an anti-fuse programming control circuit based on a master-slave charge pump structure, a master charge pump module obtains an external voltage and is connected to a plurality of slave charge pump modules. Each slave charge pump module is connected to an anti-fuse bank. The distance between the layout position of each slave charge pump module and the layout position of the connected anti-fuse bank does not exceed a predetermined distance. Based on a programming voltage output by each slave charge pump module to the connected anti-fuse bank, the feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module. Based on the feedback signal corresponding to each slave charge pump module, the master charge pump module adjusts a master drive signal provided to the slave charge pump module to stabilize the programming voltage output by the slave charge pump module.

Abstract: The present invention relates to an electrical power energy converter unit for converting Direct Current to Direct Current, DC-DC, with improved efficiency and cold-start capability.

Abstract: The present disclosure relates to driver circuitry for driving a piezoelectric transducer. The circuitry comprises: output stage circuitry configured to receive an input signal and to drive the piezoelectric transducer to produce the output signal; variable voltage power supply circuitry configured to output a supply voltage for the charge drive output stage circuitry, wherein the supply voltage output by the variable voltage power supply circuitry varies based on the input signal; a supply capacitor for receiving the supply voltage output by the variable voltage power supply circuitry; a reservoir capacitor; and circuitry for transferring charge between the reservoir capacitor and the supply capacitor.

Abstract: A driving circuit includes a cross coupled circuit, a first conducting device, a second conducting device, a first switching device, a second switching device, a first selecting device and a second selecting device. The first conducting device is connected between a first node and a second node. The second conducting device is connected between a third node and a fourth node. The cross coupled circuit receives a first supply voltage and is connected with the first node and the second node. The first switching device is connected between the second node and a fifth node. The second switching device is connected between the fourth node and a sixth node. The first and second selecting devices are respectively connected with the fifth node and the sixth node. Each of the first and second selecting devices receives a second supply voltage and a third supply voltage.

Abstract: A configurable voltage regulating circuit includes first through fourth switches. A flying capacitor is coupled between a common mode node and a pump node, and a sense resistance network is coupled between an output node and an input of an error amplifier and configured to provide a sensed output voltage. The error amplifier receives at another input a reference voltage and generates an error signal. A charging circuit supplies a charging current to the pump node, and controls the value of the charging current as a function of the error signal. A switch command signals generator generates respective first, second, third, and fourth switch signals to control the first switch, second switch, third switch, and fourth switch. The generator sets the configurable voltage regulating circuit as either a charge pump or a linear regulator based the input voltage being less than a first threshold or greater than a second threshold.

Abstract: A charge pump circuit is provided. The charge pump circuit includes a first switch configured to have a first end connected to an input terminal that receives a power voltage; a second switch configured to have a first end connected to the input terminal; a first capacitor configured to have a first end connected to a second end of the first switch; a second capacitor connected between a second end of the first capacitor and a second end of the second switch; a third switch connected between the second end of the second switch and ground; a fourth switch connected between the first end of the first capacitor and a first output terminal and configured to output a first output voltage; and a fifth switch connected between a second output terminal and a node between the first capacitor and the second capacitor, and configured to output a second output voltage.

Abstract: The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption.

Abstract: An apparatus for converting a first voltage into a second voltage includes a reconfigurable switched capacitor power converter having a selectable conversion gain. The power converter has switch elements configured to electrically interconnect capacitors to one another and/or to the first or second voltage in successive states. The switch elements are configured to interconnect at least some capacitors to one another through the switch elements. A controller causes the reconfigurable switched capacitor power converter to transition between first and second operation modes. The controller minimizes electrical transients arising from transition between modes. In the first operating mode, the power converter operates with a first conversion gain. In the second operating mode, it operates with a second conversion gain.

Abstract: An apparatus for power conversion comprises a voltage transformation element, a regulating element, and a controller; wherein, a period of the voltage transformation element is equal to a product of a coefficient and a period of the regulating circuit, and wherein the coefficient is selected from a group consisting of a positive integer and a reciprocal of said integer.

Abstract: A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is supplied to the PUT as an input current. A second number of CEs of a clock signal supplied to the first charge pump is determined over the same period of time for the same predetermined output current from the PUT. The efficiency of the PUT can then be determined as the ratio of the first number of CEs to the second number of CEs, or vice versa.

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

Abstract: An apparatus is disclosed for adaptive multi-mode charging. In an example aspect, the apparatus includes at least one charger having a first node and a second node. The at least one charger is configured to accept an input voltage at the first node. The at least one charger is also configured to selectively operate in a first mode to generate a first output voltage at the second node that is greater than or less than the input voltage or operate in a second mode to generate a second output voltage at the second node that is substantially equal to the input voltage.

Abstract: In an embodiment, A switched-mode power supply includes: a first node; a second node configured to receive a DC input voltage; a third node configured to receive a reference voltage; first and second switching transistors; a first circuit configured to control the first switching transistor; and a second circuit configured to control the second switching transistor, wherein the switched-mode power supply is configured to deliver a regulated output voltage at the first node from the DC input voltage, and wherein the first and second circuits are configured to be powered from the output voltage.

Abstract: A PWM-based (pulse width modulation-based) overcurrent protection circuit and an operating method for the same are provided. The PWM-based overcurrent protection circuit includes a pulse-width-modulation circuit that is connected to a charge pump and a load detection circuit of a power-switch circuit. The charge pump outputs a voltage to the power-switch circuit according to a clock-voltage signal. The load detection circuit is used to detect an overcurrent flowing through the power-switch circuit according to a load at an output end of the power-switch circuit. Thus, when the load detection circuit detects the overcurrent, the pulse-width-modulation circuit controls a duty-cycle width of the charge pump, so as to suppress the voltage outputted by the charge pump. Therefore, an output voltage from the power-switch circuit can be corrected for preventing or reducing the overcurrent.

Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Abstract: The present disclosure discloses a direct current (DC)-DC boost converter, which includes a battery terminal providing a battery voltage, a charge pump coupled between the battery terminal and an interior node, and a power inductor coupled between the interior node and a power supply terminal that provides a power voltage to a radio frequency transceiver. The charge pump is configured to provide an interior voltage at the interior node based on the battery voltage. Herein, the interior voltage toggles between the battery voltage and two times the battery voltage. The charge pump includes a first switch coupled between the battery terminal and the interior node, a second switch coupled between the battery terminal and a connecting node, a third switch coupled between the connecting node and ground, and a flying capacitor coupled between the interior node and the connecting node of the second switch and the third switch.

Abstract: A booster apparatus includes a voltage conversion control circuit configured to generate second power supply voltage, based on the ground voltage, first power supply voltage, and a driving clock signal. The voltage conversion control circuit includes: a booster circuit configured to generate the second power supply voltage based on an input booster clock signal; a clock buffer configured to generate the booster clock signal and output the generated booster clock signal to the booster circuit; and a voltage comparator that includes: a first voltage generation circuit configured to generate a first signal with a first voltage level; a second voltage generation circuit configured to generate a second signal with a second voltage level; and a comparator configured to compare the first voltage level and the second voltage level and control input of the driving clock signal to be supplied to the clock buffer based on a comparison result.

Abstract: A radio frequency (RF) device and a voltage generation and harmonic suppressor thereof are provided. The RF device includes the voltage generation and harmonic suppressor and a RF circuit. The voltage generation and harmonic suppressor is configured to receive a RF signal to output at least one direct current (DC) voltage related to the RF signal, and configured to suppress a harmonic generated by the RF signal in the voltage generation and harmonic suppressor. The RF circuit is configured to receive the RF signal, and configured to perform an operation according to the at least one DC voltage.

Abstract: A light driver includes a converter configured to generate a drive signal for powering a light source based on a control signal, a modular controller board electrically coupled to a sensor board and configured to receive sensor data from the sensor board and to generate a first sensor control signal corresponding to the sensor data, and a primary controller configured to control the converter by generating the control signal based on the first sensor control signal.

Abstract: Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.

Abstract: A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.

Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Abstract: A converter includes a first phase comprising a plurality of first phase switches connected in series between an input power source and ground, a second phase comprising a plurality of second phase switches connected in series between the input power source and ground, and a first flying capacitor of the first phase and a first flying capacitor of the second phase cross-coupled between the first phase and the second phase, wherein switches of the first phase and switches of the second phase are configured such that a ratio of an input voltage of the hybrid dual-phase step-down power converter to an output voltage of the hybrid dual-phase step-down power converter is equal to N/D, and wherein N is an integer, and D is a duty cycle of the hybrid dual-phase step-down power converter.

Abstract: An apparatus is disclosed for implementing a multi-mode direct-current (DC)-to-DC power converter. In an example aspect, the apparatus includes a DC-to-DC power converter with a flying capacitor, an inductor, and four switches. The inductor is coupled between a second node and a battery node. A first switch is coupled between a first node and a first terminal of the flying capacitor. A second switch is coupled between the first terminal and the second node. A third switch is coupled between a second terminal of the flying capacitor and the second node. A fourth switch is coupled between the second terminal and a ground node. The DC-to-DC power converter is configured to selectively transfer power from the first node to the battery node according to a first operational mode and transfer other power from the battery node to the first node according to a second operational mode.

Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

Abstract: Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).

Abstract: A method includes providing a current flowing through a first flying capacitor of a switched-capacitor power converter, measuring a first voltage at one terminal of the first flying capacitor at a first voltage measurement time instant, measuring a second voltage at the one terminal of the first flying capacitor at a second voltage measurement time instant, and calculating a capacitance value of the first flying capacitor based on the first voltage, the second voltage, the first voltage measurement time instant and the second voltage measurement time instant.

Abstract: A voltage converter including first to fourth switches between a first voltage node and ground, fifth to eighth switches between the first voltage node and the ground, a first floating capacitor between a first node between the first and second switches and a second node between the third and fourth switches, a second floating capacitor between a third node between the fifth and sixth switches and a fourth node between the seventh and eighth switches, a ninth switch between a second voltage node and a center node, a first inductor between the second node and a third voltage node, a center capacitor between the center node and the ground, a tenth switch between the second voltage node and the third voltage node, a first capacitor between the third voltage node and the ground, and a second capacitor between the second voltage node and the ground may be provided.

Abstract: A charge pump circuit is provided. The charge pump circuit includes a first transistor, a first capacitor, a second transistor, and a second capacitor. The first transistor has a first end and a second end. The first capacitor has a first end and a second end. The second end of the first capacitor is electrically connected to the second end of the first transistor. The second transistor has a first end and a second end. The first end of the second transistor is electrically connected to the second of the first transistor. The second capacitor has a first end and a second end. The first end of the second capacitor is electrically connected to the second end of the second transistor.

Abstract: Charge pumps of integrated circuit devices might include an input configured to receive an internally-generated first voltage level, an output, and a plurality of stages between its input and output. A particular stage might include a voltage isolation device, a voltage driver, and a capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to the voltage isolation device. The voltage driver might be responsive to a clock signal and to a voltage level of the output of the voltage driver to selectively connect the output of the voltage driver to either a first voltage node configured to receive the first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, or a third voltage node configured to receive a third voltage level lower than the second voltage level.

Abstract: A voltage detection circuit and a charge pump circuit using the voltage detection circuit are provided. The voltage detection circuit includes: a voltage raising circuit configured to adjust a voltage to be measured and then output an adjusted voltage, where the adjusted voltage is equal to the sum of the voltage to be measured and a reference voltage; and the reference voltage is generated by a combination of a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient.

Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.

Abstract: An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.

Abstract: Low noise charge pumps are disclosed. In certain embodiments, a charge pump includes a charge pump output terminal configured to provide a charge pump voltage, a switched capacitor, an inverter having an output electrically connected to a first end of the switched capacitor, a pair of charging switches connected between a second end of the switched capacitor and a reference voltage, and a pair of discharging switches connected between the second end of the switched capacitor and the charge pump output terminal. The pair of charging switches is closed during a charging operation and open during a discharging operation, while the pair of discharging switches closed during the discharging operation and open during the charging operation.

Abstract: A power supply structure and an electronic cigarette having same are provided. The power supply structure includes at least two rechargeable batteries connected in series, a charging circuit connected to the rechargeable batteries and used to charge the rechargeable batteries, and a switching circuit connected to the at least two rechargeable batteries. The switching circuit is used to switch the at least two rechargeable batteries into battery series circuits having different number of rechargeable batteries connected in series. The charging circuit is used to detect the voltages of the battery series circuits and convert a standard charging voltage into different charging voltages for charging the battery series circuits according to the detected voltages.

Abstract: In a power converter, a switching network having switches that operate at a common frequency and duty cycle interconnects circuit elements. These circuit elements include capacitors that are in a capacitor network and a magnetic filter. When connected to the capacitors by a switch from the switching network, the magnetic filter imposes a constraint upon inter-capacitor charge transfer between the capacitors to maintain the filter's second terminal at a voltage. The switching network transitions between states. These states include a first state, a second state, and a third state. In both the first state and the third state, the first magnetic-filter terminal couples to the capacitor network. In the second state, which occurs between the first and third state, the switches ground the first magnetic-filter terminal.

Abstract: A method of updating firmware in a chip in a stable and effective manner receives firmware outputted by a controller. The received firmware is burned into the chip. A voltage level of a controlling signal outputted by a controlling pin of the chip is latched to a certain level based on a latching signal at a first voltage level outputted by the controller. The storage medium is refreshed for making the burned firmware effective based on refresh instruction outputted by the controller. The latching signal at a second voltage level for unlatching the voltage level of the controlling signal is outputted by the controller if operations of the chip are stable. An updating operation of the chip by the method does not interrupt other operations being executed by the chip. A firmware updating apparatus and a computer readable storage medium applying the method are also disclosed.

Abstract: A charge pump circuit includes a sub-circuit, which is a pumping stage circuit or an output stage circuit. The sub-circuit includes an input terminal, an output terminal, a transistor, a first capacitive device, a first diode device, and a second diode device. The transistor has a first source/drain (S/D) terminal coupled with the input terminal, a second S/D terminal coupled with the output terminal, and a gate terminal. The first capacitive device has a first end coupled with the gate terminal of the transistor and a second end configured to receive a first driving signal. The first diode device has a cathode coupled with the second S/D terminal of the transistor and an anode coupled with the gate terminal of the transistor. The second diode device has a cathode coupled with the gate terminal of the transistor and an anode coupled with the second S/D terminal of the transistor.

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

Abstract: A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.

Abstract: The present disclosure provides step-down rectifier circuit includes a rectifier module, a charge pump module, a filter unit, and a control unit. The rectifier module includes a first bridge arm unit connected to in-phase output terminal of an alternating current signal and a second bridge arm unit connected to out-of-phase output terminal of the alternating current signal. The charge pump module includes a first voltage converter unit and a second voltage converter unit in parallel. The control unit is configured to output a first pulse width modulation signal to control the on and off of the switch transistors in the rectifier module, and output a second pulse width modulation signal to control the on and off of the switch transistors in the charge pump module, such that an operating frequency of the charge pump module is a positive integer multiple of the frequency of the alternating current signal.

Abstract: An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.

Abstract: A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) charging the capacitor causing a current to flow in the inductor and (2) discharging the capacitor causing current to flow in the inductor. The power regulator circuit may be configured to operate with zero current switching at frequencies in the range of 100 MHz, enabling it to be fabricated on a unitary silicon die along with the load that it powers.

Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Abstract: An integrated circuit (IC) includes an input/output (I/O) circuitry with a first circuitry section including I/O pins and a second circuitry section including I/O pins. The first and second circuitry sections are mutually exclusive sections of the I/O ring. The first circuitry section includes a first I/O pin configured to receive an input voltage from a first energy source and a second I/O pin connectable to an external startup capacitor. A startup circuit is coupled to the first I/O pin and the second I/O pin. Upon receiving the input voltage from the first energy source, the startup circuit enters a during the startup phase and isolates the first circuitry section from the second circuitry section, and provides charge to the external startup capacitor. In response to achieving a predetermined minimum charge on the external startup capacitor, the first circuitry section is connected to the second circuitry section, and the startup phase ends and the IC transitions to a functional mode of operation.