Charge Pump Details Patents (Class 327/536)
  • Patent number: 11927635
    Abstract: A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is supplied to the PUT as an input current. A second number of CEs of a clock signal supplied to the first charge pump is determined over the same period of time for the same predetermined output current from the PUT. The efficiency of the PUT can then be determined as the ratio of the first number of CEs to the second number of CEs, or vice versa.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: March 12, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keyur Payak, Naveen Thomas
  • Patent number: 11929663
    Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 12, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Juan Qiao, Chenxiao Ren, Yue Wang
  • Patent number: 11923715
    Abstract: An apparatus is disclosed for adaptive multi-mode charging. In an example aspect, the apparatus includes at least one charger having a first node and a second node. The at least one charger is configured to accept an input voltage at the first node. The at least one charger is also configured to selectively operate in a first mode to generate a first output voltage at the second node that is greater than or less than the input voltage or operate in a second mode to generate a second output voltage at the second node that is substantially equal to the input voltage.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 5, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chunping Song, Cheong Kun, Xiaolin Gao, Sanghwa Jung, Yue Jing
  • Patent number: 11916480
    Abstract: In an embodiment, A switched-mode power supply includes: a first node; a second node configured to receive a DC input voltage; a third node configured to receive a reference voltage; first and second switching transistors; a first circuit configured to control the first switching transistor; and a second circuit configured to control the second switching transistor, wherein the switched-mode power supply is configured to deliver a regulated output voltage at the first node from the DC input voltage, and wherein the first and second circuits are configured to be powered from the output voltage.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 27, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Vincent Pinon
  • Patent number: 11901885
    Abstract: A PWM-based (pulse width modulation-based) overcurrent protection circuit and an operating method for the same are provided. The PWM-based overcurrent protection circuit includes a pulse-width-modulation circuit that is connected to a charge pump and a load detection circuit of a power-switch circuit. The charge pump outputs a voltage to the power-switch circuit according to a clock-voltage signal. The load detection circuit is used to detect an overcurrent flowing through the power-switch circuit according to a load at an output end of the power-switch circuit. Thus, when the load detection circuit detects the overcurrent, the pulse-width-modulation circuit controls a duty-cycle width of the charge pump, so as to suppress the voltage outputted by the charge pump. Therefore, an output voltage from the power-switch circuit can be corrected for preventing or reducing the overcurrent.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: February 13, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Li-Cheng Chu
  • Patent number: 11901818
    Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: February 13, 2024
    Assignee: pSemi Corporation
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 11876488
    Abstract: The present disclosure discloses a direct current (DC)-DC boost converter, which includes a battery terminal providing a battery voltage, a charge pump coupled between the battery terminal and an interior node, and a power inductor coupled between the interior node and a power supply terminal that provides a power voltage to a radio frequency transceiver. The charge pump is configured to provide an interior voltage at the interior node based on the battery voltage. Herein, the interior voltage toggles between the battery voltage and two times the battery voltage. The charge pump includes a first switch coupled between the battery terminal and the interior node, a second switch coupled between the battery terminal and a connecting node, a third switch coupled between the connecting node and ground, and a flying capacitor coupled between the interior node and the connecting node of the second switch and the third switch.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: January 16, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Michael R. Kay, Jeffrey D. Potts, Michael J. Murphy
  • Patent number: 11877053
    Abstract: A booster apparatus includes a voltage conversion control circuit configured to generate second power supply voltage, based on the ground voltage, first power supply voltage, and a driving clock signal. The voltage conversion control circuit includes: a booster circuit configured to generate the second power supply voltage based on an input booster clock signal; a clock buffer configured to generate the booster clock signal and output the generated booster clock signal to the booster circuit; and a voltage comparator that includes: a first voltage generation circuit configured to generate a first signal with a first voltage level; a second voltage generation circuit configured to generate a second signal with a second voltage level; and a comparator configured to compare the first voltage level and the second voltage level and control input of the driving clock signal to be supplied to the clock buffer based on a comparison result.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 16, 2024
    Assignee: OLYMPUS CORPORATION
    Inventor: Yoshio Hagihara
  • Patent number: 11870445
    Abstract: A radio frequency (RF) device and a voltage generation and harmonic suppressor thereof are provided. The RF device includes the voltage generation and harmonic suppressor and a RF circuit. The voltage generation and harmonic suppressor is configured to receive a RF signal to output at least one direct current (DC) voltage related to the RF signal, and configured to suppress a harmonic generated by the RF signal in the voltage generation and harmonic suppressor. The RF circuit is configured to receive the RF signal, and configured to perform an operation according to the at least one DC voltage.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 9, 2024
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Yu-Hsiang Chu
  • Patent number: 11864289
    Abstract: A light driver includes a converter configured to generate a drive signal for powering a light source based on a control signal, a modular controller board electrically coupled to a sensor board and configured to receive sensor data from the sensor board and to generate a first sensor control signal corresponding to the sensor data, and a primary controller configured to control the converter by generating the control signal based on the first sensor control signal.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: January 2, 2024
    Assignee: ERP POWER, LLC
    Inventors: Vachik Javadian, Steven C. Krattiger
  • Patent number: 11854599
    Abstract: Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 26, 2023
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takahiko Ishizu, Yuto Yakubo, Tatsuya Onuki, Shunpei Yamazaki
  • Patent number: 11842789
    Abstract: A capacitor string structure, a memory device and a charge pump circuit thereof are provided. The capacitor string structure includes a plurality of conductive plates. The conductive plates are disposed in the memory device. The conductive plates are stacked to each other, and respectively form a plurality of word lines of the memory device, where two neighbored conductive plates form a capacitor.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: December 12, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Tzeng-Huei Shiau
  • Patent number: 11837954
    Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: December 5, 2023
    Assignee: pSemi Corporation
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 11817770
    Abstract: A converter includes a first phase comprising a plurality of first phase switches connected in series between an input power source and ground, a second phase comprising a plurality of second phase switches connected in series between the input power source and ground, and a first flying capacitor of the first phase and a first flying capacitor of the second phase cross-coupled between the first phase and the second phase, wherein switches of the first phase and switches of the second phase are configured such that a ratio of an input voltage of the hybrid dual-phase step-down power converter to an output voltage of the hybrid dual-phase step-down power converter is equal to N/D, and wherein N is an integer, and D is a duty cycle of the hybrid dual-phase step-down power converter.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: November 14, 2023
    Assignee: Halo Microelectronics International
    Inventors: Rui Liu, Thomas Liu, Songnan Yang
  • Patent number: 11791721
    Abstract: An apparatus is disclosed for implementing a multi-mode direct-current (DC)-to-DC power converter. In an example aspect, the apparatus includes a DC-to-DC power converter with a flying capacitor, an inductor, and four switches. The inductor is coupled between a second node and a battery node. A first switch is coupled between a first node and a first terminal of the flying capacitor. A second switch is coupled between the first terminal and the second node. A third switch is coupled between a second terminal of the flying capacitor and the second node. A fourth switch is coupled between the second terminal and a ground node. The DC-to-DC power converter is configured to selectively transfer power from the first node to the battery node according to a first operational mode and transfer other power from the battery node to the first node according to a second operational mode.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 17, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jiwei Chen, Guoyong Guo, Yue Jing
  • Patent number: 11784651
    Abstract: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 10, 2023
    Assignee: NXP B.V.
    Inventors: Ravichandar Reddy Geetla, Deependra Kumar Jain, Gaurav Agrawal, Ravi Kumar
  • Patent number: 11776625
    Abstract: Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Hongmei Wang, Hari Giduturi
  • Patent number: 11770070
    Abstract: A method includes providing a current flowing through a first flying capacitor of a switched-capacitor power converter, measuring a first voltage at one terminal of the first flying capacitor at a first voltage measurement time instant, measuring a second voltage at the one terminal of the first flying capacitor at a second voltage measurement time instant, and calculating a capacitance value of the first flying capacitor based on the first voltage, the second voltage, the first voltage measurement time instant and the second voltage measurement time instant.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: September 26, 2023
    Assignee: NUVOLTA TECHNOLOGIES (SHANGHAI) CO., LTD.
    Inventors: Ikgyoo Song, Xiaoming Xia
  • Patent number: 11764671
    Abstract: A voltage converter including first to fourth switches between a first voltage node and ground, fifth to eighth switches between the first voltage node and the ground, a first floating capacitor between a first node between the first and second switches and a second node between the third and fourth switches, a second floating capacitor between a third node between the fifth and sixth switches and a fourth node between the seventh and eighth switches, a ninth switch between a second voltage node and a center node, a first inductor between the second node and a third voltage node, a center capacitor between the center node and the ground, a tenth switch between the second voltage node and the third voltage node, a first capacitor between the third voltage node and the ground, and a second capacitor between the second voltage node and the ground may be provided.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: September 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Chan Lee, Hyoungseok Oh, Hojun Yu, Jeongkwang Lee, Jungwook Heo
  • Patent number: 11757354
    Abstract: A charge pump circuit is provided. The charge pump circuit includes a first transistor, a first capacitor, a second transistor, and a second capacitor. The first transistor has a first end and a second end. The first capacitor has a first end and a second end. The second end of the first capacitor is electrically connected to the second end of the first transistor. The second transistor has a first end and a second end. The first end of the second transistor is electrically connected to the second of the first transistor. The second capacitor has a first end and a second end. The first end of the second capacitor is electrically connected to the second end of the second transistor.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: September 12, 2023
    Assignee: Innolux Corporation
    Inventor: Kazuyuki Hashimoto
  • Patent number: 11715502
    Abstract: Charge pumps of integrated circuit devices might include an input configured to receive an internally-generated first voltage level, an output, and a plurality of stages between its input and output. A particular stage might include a voltage isolation device, a voltage driver, and a capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to the voltage isolation device. The voltage driver might be responsive to a clock signal and to a voltage level of the output of the voltage driver to selectively connect the output of the voltage driver to either a first voltage node configured to receive the first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, or a third voltage node configured to receive a third voltage level lower than the second voltage level.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Marco-Domenico Tiburzi, Stefano Perugini
  • Patent number: 11703527
    Abstract: A voltage detection circuit and a charge pump circuit using the voltage detection circuit are provided. The voltage detection circuit includes: a voltage raising circuit configured to adjust a voltage to be measured and then output an adjusted voltage, where the adjusted voltage is equal to the sum of the voltage to be measured and a reference voltage; and the reference voltage is generated by a combination of a first voltage with a positive temperature coefficient and a second voltage with a negative temperature coefficient.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 18, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Rumin Ji
  • Patent number: 11689100
    Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: June 27, 2023
    Assignee: NXP USA, Inc.
    Inventors: Mohammad Nizam Kabir, Madan Mohan Reddy Vemula, Xu Jason Ma
  • Patent number: 11662755
    Abstract: An apparatus for generating a steady state positive voltage (PVS) signal and a steady state negative voltage (NVS) signal is presented. The apparatus includes a bias signal generation module for generating a steady state reference voltage signal (RVS) based on a varying supply voltage signal (VDD), the RVS having a voltage level less than the PVS. The apparatus further includes a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS. The apparatus further includes a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: May 30, 2023
    Assignee: pSemi Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk
  • Patent number: 11658568
    Abstract: Low noise charge pumps are disclosed. In certain embodiments, a charge pump includes a charge pump output terminal configured to provide a charge pump voltage, a switched capacitor, an inverter having an output electrically connected to a first end of the switched capacitor, a pair of charging switches connected between a second end of the switched capacitor and a reference voltage, and a pair of discharging switches connected between the second end of the switched capacitor and the charge pump output terminal. The pair of charging switches is closed during a charging operation and open during a discharging operation, while the pair of discharging switches closed during the discharging operation and open during the charging operation.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: May 23, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Lui Ray Lam
  • Patent number: 11641881
    Abstract: A power supply structure and an electronic cigarette having same are provided. The power supply structure includes at least two rechargeable batteries connected in series, a charging circuit connected to the rechargeable batteries and used to charge the rechargeable batteries, and a switching circuit connected to the at least two rechargeable batteries. The switching circuit is used to switch the at least two rechargeable batteries into battery series circuits having different number of rechargeable batteries connected in series. The charging circuit is used to detect the voltages of the battery series circuits and convert a standard charging voltage into different charging voltages for charging the battery series circuits according to the detected voltages.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: May 9, 2023
    Assignee: CHANGZHOU PATENT ELECTRONIC TECHNOLOGY CO., LTD.
    Inventor: Weihua Qiu
  • Patent number: 11646657
    Abstract: In a power converter, a switching network having switches that operate at a common frequency and duty cycle interconnects circuit elements. These circuit elements include capacitors that are in a capacitor network and a magnetic filter. When connected to the capacitors by a switch from the switching network, the magnetic filter imposes a constraint upon inter-capacitor charge transfer between the capacitors to maintain the filter's second terminal at a voltage. The switching network transitions between states. These states include a first state, a second state, and a third state. In both the first state and the third state, the first magnetic-filter terminal couples to the capacitor network. In the second state, which occurs between the first and third state, the switches ground the first magnetic-filter terminal.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: May 9, 2023
    Assignee: pSemi Corporation
    Inventor: David Giuliano
  • Patent number: 11630732
    Abstract: A method of updating firmware in a chip in a stable and effective manner receives firmware outputted by a controller. The received firmware is burned into the chip. A voltage level of a controlling signal outputted by a controlling pin of the chip is latched to a certain level based on a latching signal at a first voltage level outputted by the controller. The storage medium is refreshed for making the burned firmware effective based on refresh instruction outputted by the controller. The latching signal at a second voltage level for unlatching the voltage level of the controlling signal is outputted by the controller if operations of the chip are stable. An updating operation of the chip by the method does not interrupt other operations being executed by the chip. A firmware updating apparatus and a computer readable storage medium applying the method are also disclosed.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 18, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventor: Li-Yun Hao
  • Patent number: 11611276
    Abstract: A charge pump circuit includes a sub-circuit, which is a pumping stage circuit or an output stage circuit. The sub-circuit includes an input terminal, an output terminal, a transistor, a first capacitive device, a first diode device, and a second diode device. The transistor has a first source/drain (S/D) terminal coupled with the input terminal, a second S/D terminal coupled with the output terminal, and a gate terminal. The first capacitive device has a first end coupled with the gate terminal of the transistor and a second end configured to receive a first driving signal. The first diode device has a cathode coupled with the second S/D terminal of the transistor and an anode coupled with the gate terminal of the transistor. The second diode device has a cathode coupled with the gate terminal of the transistor and an anode coupled with the second S/D terminal of the transistor.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Alan Roth, Eric Soenen
  • Patent number: 11605431
    Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: March 14, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Feng Lin, Su-Chueh Lo, Teng-Hao Yeh, Hang-Ting Lue
  • Patent number: 11563373
    Abstract: A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: January 24, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Neha Dalal
  • Patent number: 11557964
    Abstract: An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 17, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Stuart Pullen, Jialei Xu, Chunping Song, Ta-Tung Yen
  • Patent number: 11557966
    Abstract: The present disclosure provides step-down rectifier circuit includes a rectifier module, a charge pump module, a filter unit, and a control unit. The rectifier module includes a first bridge arm unit connected to in-phase output terminal of an alternating current signal and a second bridge arm unit connected to out-of-phase output terminal of the alternating current signal. The charge pump module includes a first voltage converter unit and a second voltage converter unit in parallel. The control unit is configured to output a first pulse width modulation signal to control the on and off of the switch transistors in the rectifier module, and output a second pulse width modulation signal to control the on and off of the switch transistors in the charge pump module, such that an operating frequency of the charge pump module is a positive integer multiple of the frequency of the alternating current signal.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: January 17, 2023
    Assignee: Halo Microelectronics Co., Ltd.
    Inventors: Shuang Han, Songnan Yang, Rui Liu
  • Patent number: 11552564
    Abstract: A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) charging the capacitor causing a current to flow in the inductor and (2) discharging the capacitor causing current to flow in the inductor. The power regulator circuit may be configured to operate with zero current switching at frequencies in the range of 100 MHz, enabling it to be fabricated on a unitary silicon die along with the load that it powers.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 10, 2023
    Assignee: Empower Semiconductor, Inc.
    Inventors: David Lidsky, Timothy Alan Phillips
  • Patent number: 11552560
    Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: January 10, 2023
    Assignee: PSEMI CORPORATION
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 11545967
    Abstract: An integrated circuit (IC) includes an input/output (I/O) circuitry with a first circuitry section including I/O pins and a second circuitry section including I/O pins. The first and second circuitry sections are mutually exclusive sections of the I/O ring. The first circuitry section includes a first I/O pin configured to receive an input voltage from a first energy source and a second I/O pin connectable to an external startup capacitor. A startup circuit is coupled to the first I/O pin and the second I/O pin. Upon receiving the input voltage from the first energy source, the startup circuit enters a during the startup phase and isolates the first circuitry section from the second circuitry section, and provides charge to the external startup capacitor. In response to achieving a predetermined minimum charge on the external startup capacitor, the first circuitry section is connected to the second circuitry section, and the startup phase ends and the IC transitions to a functional mode of operation.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 3, 2023
    Assignee: NXP B.V.
    Inventors: Edwin Schapendonk, Wouter van der Heijden, Oswald Moonen, Henri Verhoeven, Ton van Deursen
  • Patent number: 11527951
    Abstract: Certain aspects of the present disclosure generally relate to soft starting a switched-mode power supply (SMPS) circuit operating as a charge pump in a reverse multiply-by-two mode. One example SMPS circuit generally includes a plurality of transistors, a capacitive element coupled to the plurality of transistors, and a current sink coupled between the capacitive element and a reference potential node for the SMPS circuit. For certain aspects, the current sink is configured to be enabled during a first phase of a soft start operation for the SMPS circuit, but is configured to be disabled during a second phase of the soft start operation and during normal operation for the SMPS circuit.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: December 13, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Yue Jing, Sanghwa Jung, David Wong
  • Patent number: 11527416
    Abstract: A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming a plurality of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing a first etch step; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth metal layer above; forming a connection to the second metal layer which includes a via through the second level; forming a fifth metal layer above, where some second transistors include a metal gate, and the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: December 13, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 11514978
    Abstract: An electronic device includes a flag generation circuit and a delay circuit. The flag generation circuit is configured to generate a flag signal, wherein a level of the flag signal changes based on a first internal command. The delay circuit is configured to generate a delay signal by delaying one of an operation signal and the flag signal by a predetermined period according to whether a predetermined operation is performed.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11509214
    Abstract: An apparatus and a method that provide a bias voltage to a charge pump circuit are described. An example apparatus includes: a bias voltage generator that receives a first voltage and provides a second voltage responsive to the first voltage; a charge pump circuit that receives an input signal and provides the first voltage. The charge pump circuit includes an inverter and a bias transistor. The inverter receives the input signal and provides a third voltage. The bias transistor coupled between a power node having a power supply voltage and a slew rate driver of the inverter. The bias transistor receives the second voltage and provides a power supply voltage to the slew rate driver responsive to the second voltage less than a threshold voltage and stops providing the power supply voltage to the slew rate driver responsive to the second voltage greater than the threshold voltage.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Takamasa Suzuki
  • Patent number: 11507123
    Abstract: A constant voltage circuit includes a depletion transistor having a drain, a gate, and a source, the drain connected to a first power supply terminal, and the gate connected to the source, a voltage division circuit connected between the first power supply terminal and an output terminal, a first enhancement transistor having a drain connected to the source of the depletion transistor, a source connected to the output terminal, and a gate connected to an output terminal of the voltage division circuit, a second enhancement transistor having a source connected to the first power supply terminal, a drain connected to the output terminal, and a gate connected to the drain of the first enhancement transistor, and a pull-down element having one end connected to the output terminal and the other end connected to a second power supply terminal.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 22, 2022
    Assignee: ABLIC INC.
    Inventor: Kosuke Takada
  • Patent number: 11509220
    Abstract: An electronic device comprises a switching regulator. Here, the switching regulator has a first wiring portion (including a parasitic inductance) coupling the high-side element and the low-side element, and a second wiring portion (including a parasitic inductance) coupled with the low-side element. Also, the switching regulator has a first region in where the first wiring portion and the second wiring portion are lined up with each other. As a result, the performance of the electronic device can be improved.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: November 22, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuaki Tsukuda
  • Patent number: 11507642
    Abstract: Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari, Mark Reiten, Nhan Do
  • Patent number: 11469671
    Abstract: The integrated circuit includes a first node intended to be biased at a first voltage, a second node intended to be biased at a second voltage and having a non-negligible capacitive coupling with the first node. A power supply management device comprises a voltage booster configured to boost a power supply voltage and comprising boost stages configured to generate intermediate voltages on intermediate nodes. A compatibility detection circuit is configured to detect compatibility between the second voltage and one of the intermediate voltages, and, if the second voltage is compatible with an intermediate voltage, to couple the at least one second node to the compatible intermediate node.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: October 11, 2022
    Assignee: STMicroelectronics (Alps) SAS
    Inventor: Thomas Jouanneau
  • Patent number: 11456664
    Abstract: The present invention provides a technique for a power supply, and particularly, a buck-boost DC-DC converter which is advantageous for energy harvesting from a low voltage. An LC resonant unit generates a pair of clock type signals having phases opposite to each other from an input signal. These signals are supplied to the clock input terminals of the Dickson charge pumps connected in series and converted into power signals having an amplified voltage so as to match the rated input specification of the buck-boost DC-DC converter of a post-stage.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: September 27, 2022
    Assignees: SKAIChipsCo., Ltd., Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Kang Yoon Lee, Reza Eftekhari Rad, Qurat ul Ain, Jong Wan Jo, Kyung Duk Choi, Young Gun Pu
  • Patent number: 11451151
    Abstract: A hybrid dual-phase step-up power conversion system includes a first leg including a first switch, a second switch and a third switch connected in series between an output terminal of the hybrid dual-phase step-up power conversion system and ground, a second leg including a fourth switch, a fifth switch and a sixth switch connected in series between the output terminal of the hybrid dual-phase step-up power conversion system and ground, and a first capacitor and a second capacitor cross-coupled between the first leg and the second leg, wherein switches of the first leg and switches of the second leg are configured such that a sum of a voltage across the first capacitor and a voltage across the second capacitor is fed into the output terminal of the hybrid dual-phase step-up power conversion system.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: September 20, 2022
    Assignee: Halo Microelectronics International
    Inventor: Thomas Liu
  • Patent number: 11411566
    Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: August 9, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Salvatore Luciano Finocchiaro, Tolga Dine, Gerd Schuppener, Siraj Akhtar, Swaminathan Sankaran, Baher Haroun
  • Patent number: 11404960
    Abstract: An electronic circuit includes a charge pump circuit, which includes a drive power supply; a flying capacitor; and a pump capacitor that is coupled in parallel to the drive power supply and the flying capacitor in response to a first control signal being in first state and is configured to receive charge from the flying capacitor to boost a pump voltage across the pump capacitor to a value that exceeds a drive voltage provided by the drive power supply responsive to a transition of the first control signal from the first state to a second state. The electronic circuit further includes a gate drive circuit coupled to the charge pump circuit.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: August 2, 2022
    Assignee: UNIVERSITY OF TENNESSEE RESEARCH FOUNDATION
    Inventors: Handong Gui, Leon M. Tolbert
  • Patent number: 11398778
    Abstract: A charge pump structure is disclosed. In an embodiment a regulated charge pump structure includes an output terminal configured to provide a regulated output voltage, a first charge pump configured to generate the output voltage as a function of an input supply voltage and a control circuit configured to limit a level of the output voltage and to generate a control voltage, wherein the level of the output voltage is controlled by the control voltage such that the output voltage does not exceed a threshold value.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: July 26, 2022
    Assignee: SCIOSENSE B.V.
    Inventors: Stefan Kern, Torben Weng
  • Patent number: RE49175
    Abstract: According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 16, 2022
    Assignee: Kioxia Corporation
    Inventors: Takeshi Nakano, Mikio Ogawa