Charge Pump Details Patents (Class 327/536)
  • Patent number: 10840856
    Abstract: Components of a power amplifier controller may support lower voltages than the power amplifier itself. As a result, a surge protection circuit that prevents a power amplifier from being damaged due to a power surge may not effectively protect the power amplifier controller. Embodiments disclosed herein present an overvoltage protection circuit that prevents a charge-pump from providing a voltage to a power amplifier controller during a detected surge event. By separately detecting and preventing a voltage from being provided to the power amplifier controller during a surge event, the power amplifier controller can be protected regardless of whether the surge event results in a voltage that may damage the power amplifier. Further, embodiments of the overvoltage protection circuit can prevent a surge voltage from being provided to a power amplifier operating in 2G mode.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Wendy Ng, Wei Long, Kevin Cho
  • Patent number: 10833677
    Abstract: According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output. This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: November 10, 2020
    Inventor: Ari Paasio
  • Patent number: 10833581
    Abstract: A control system, and corresponding method, for a Multi-Level Hybrid Flying Capacitor (MLHFC) converter. The control system includes a controller configured to control an output of the MLHFC converter; a feedback region detector configured to detect a change in a feedback region of the MLHFC converter; and a controller adjuster configured to, in response to the detected change, adjust the control system to counteract instability.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Nicolo Zilio, Andreas Berger, Marc Kanzian
  • Patent number: 10826738
    Abstract: A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: November 3, 2020
    Assignee: INNOPHASE INC.
    Inventors: Jun Pan, Yang Xu
  • Patent number: 10818368
    Abstract: A level shifter circuit configured to shift an input signal switching within a first voltage range to generate a first output signal correspondingly switching within a second voltage range higher than the first voltage range. The level shifter circuit including a latching core having latching input and output terminals and a supply line configured to be supplied by a supply voltage, and a reference line configured to be coupled to a reference voltage. Capacitive coupling elements are coupled to the latching input and output terminals of the latching core. A driving stage is configured to bias the capacitive coupling elements with biasing signals generated based on the input signal. A decoupling stage is configured to be driven by the driving stage through the capacitive coupling elements to decouple the supply line from the supply voltage and the reference line from the reference voltage during switching of the input signal.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 27, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Conte, Leopoldo Maria Marino, Maurizio Francesco Perroni, Salvatore Polizzi
  • Patent number: 10811961
    Abstract: A charge pump includes a first power source having a voltage VREG generated from a regulated and circuit-limiter supply, a second power source having a voltage VBRG and a top-off capacitor adapted to be charged to a voltage of the high of VREG or VBRG to a limit of a voltage clamp across the top-off capacitor.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 20, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Thomas Ross, Aldo Togneri, James McIntosh, Gianluca Allegrini
  • Patent number: 10804797
    Abstract: The present invention is directed to electrical circuits. According to an embodiment, the present invention provides a charge pump circuit with a bias section and a switch section. The switch section includes a first switch coupled to an early signal and a second switch coupled to a late signal. The charge pump additionally includes a low-pass filter. The switch section includes a first resistor and a second resistor. The first resistor is directly coupled to the first switch and the low-pass filter. The second resistor is directly coupled to the second switch and the first resistor. There are other embodiments as well.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 13, 2020
    Assignee: INPHI CORPORATION
    Inventors: Rajasekhar Nagulapalli, Simon Forey, Parmanand Mishra
  • Patent number: 10804794
    Abstract: A charge pump controller for controlling a charge pump adapted to convert an input voltage into an output voltage with a conversion ratio is presented. The charge pump is operable in a plurality of modes corresponding to different conversion ratios. The controller includes a first selector for selecting a mode of operation of the charge pump. The first selector comprises a first input for coupling to a voltage supply; and a second input for coupling to a source signal. The first selector identifies a target value of the output voltage. The selector calculates a product of the conversion ratio and the input voltage. The selector compares the product with the target value and selects a mode of operation of the charge pump by increasing or decreasing the conversion ratio based on the comparison. The selector maintains the conversion ratio for a length of time before decreasing the conversion ratio.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Guillaume de Cremoux
  • Patent number: 10790781
    Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an oscillation circuit, a charge pump circuit, a smoothing circuit, and a negative feedback circuit. The charge pump circuit is arranged between each of a power supply input terminal and the oscillation circuit and a power supply output terminal. The smoothing circuit is arranged between the charge pump circuit and the power supply output terminal. The negative feedback circuit is arranged on a path returning from the smoothing circuit to the oscillation circuit. The smoothing circuit includes a first zero point generation circuit.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 29, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hironori Nagasawa
  • Patent number: 10790017
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: 10778093
    Abstract: An electronic device includes: a clock booster circuit configured to store charges on doubler capacitors therein, wherein each doubler capacitor is connected to a corresponding clock signal; secondary booster circuit including booster capacitors that are each coupled to one of the doubler capacitors, the secondary booster circuit configured to provide one or more stage outputs based on boosting the charges stored on the doubler capacitors; and connecting switches that each connect one of the doubler capacitors to one of the booster capacitors during recycling durations, wherein the recycling duration occurs after generating the one or more stage outputs; wherein the clock signals correspond to a state during the recycling duration.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10778094
    Abstract: A charge pump controller for controlling a charge pump adapted to convert an input voltage into an output voltage with a conversion ratio is presented. The charge pump is operable in a plurality of modes corresponding to different conversion ratios. The controller includes a first selector for selecting a mode of operation of the charge pump. The first selector comprises a first input for coupling to a voltage supply; and a second input for coupling to a source signal. The first selector identifies a target value of the output voltage. The selector calculates a product of the conversion ratio and the input voltage. The selector compares the product with the target value and selects a mode of operation of the charge pump by increasing or decreasing the conversion ratio based on the comparison. The selector maintains the conversion ratio for a length of time before decreasing the conversion ratio.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Guillaume de Cremoux
  • Patent number: 10763737
    Abstract: A waveform shaping circuit includes a first variable gate voltage circuit that controls a minimum voltage of a pulse voltage based on a drain current or a source current of a field effect transistor, the pulse voltage having a positive or negative value and being applied to a gate of the field effect transistor, and a second variable gate voltage circuit that controls a maximum voltage of the pulse voltage based on the drain current or the source current.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 1, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Tatsuya Hirose
  • Patent number: 10756713
    Abstract: A clock signal boost circuit includes a first NMOS transistor having a drain to a power terminal, a source to a first node, and a gate to a first terminal, a second NMOS transistor having a drain to the first node, a source to a GND, and a gate to a second terminal, a third NMOS transistor having a drain to the power terminal, a source to a second node, and a gate to the second terminal, a capacitor between the first node and the second node, a PMOS transistor having a source to the second node, a drain to an output terminal, and a gate to the second terminal, and a fourth NMOS transistor having a drain to the output terminal, a source to the GND, and a gate to the second terminal. The first and the third NMOS transistors are depletion type NMOS transistors.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 25, 2020
    Assignee: ABLIC INC.
    Inventor: Fumiyasu Utsunomiya
  • Patent number: 10756615
    Abstract: A power supply conversion circuit is provided, which includes: a first voltage clamping module configured to decrease an input voltage to a preset low voltage; a boost module configured to increase the input voltage or the preset low voltage to a target voltage; a second voltage clamping module configured to maintain the target voltage within a preset voltage range; a filter module configured to filter out ripples in the target voltage; and at least one output module, each of which is configured to supply power to a load. Compared with a conventional LDO integrated circuit, the circuit can provide multiple output power supplies, and it is only required to additionally arrange one field effect transistor for one more output power supply. Therefore, the power supply conversion circuit has a simple structure, is expandable easily and is applicable to an analog integrated circuit requiring multiple output power supplies.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 25, 2020
    Assignee: Shanghai Awinic Technology Co., LTD
    Inventors: Xucheng Luo, Jianwei Hu, Jiantao Cheng
  • Patent number: 10755657
    Abstract: Disclosed are a data driver, a display, and a method of driving a display. The data driver for driving a data line which is a capacitive load having one end electrically connected to a unit pixel includes an energy retrieving unit configured to drive the data line by applying a voltage to the data line, and a data driving unit configured to finely tune a voltage and drive the data line with an end voltage. The energy retrieving unit retrieves energy charged up in the data line in stages by driving the data line with voltages from a start voltage to the end voltage through an intermediate voltage.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 25, 2020
    Assignee: INNOAXIS CO., LTD
    Inventor: Hwi-Cheol Kim
  • Patent number: 10720842
    Abstract: Multi-level DC-to-DC converter circuits and methods that permit a full range of output voltages, including near and at zone boundaries. Embodiments alternate among adjacent or near-by zones, operating in a first zone for a selected time and then in a second zone for a selected time. Embodiments may include a parallel capacitor voltage balancing circuit that connects a capacitor to a source voltage to charge that capacitor, or couples two or more capacitors together to transfer charge, all under the control of real-time capacitor voltage measurements. Embodiments may include a lossless voltage balancing solution where out-of-order state transitions are allowed, thus increasing or decreasing the voltage across specific capacitors to prevent voltage overstress on the converter main switches. Restrictions may be placed on the overall sequence of state transitions to reduce or avoid transition state toggling, allowing each capacitor an opportunity to have its voltage steered as necessary for balancing.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: July 21, 2020
    Assignee: pSemi Corporation
    Inventors: Gary Chunshien Wu, David M. Giuliano, Gregory Szczeszynski
  • Patent number: 10720834
    Abstract: A charge pump, applied to an OLED display panel and coupled to an output capacitor, includes a first switch to a tenth switch and a first capacitor to a third capacitor. The first switch and second switch are coupled in series between a first voltage and a second voltage lower than first voltage. The third switch is coupled to second voltage. The sixth switch is coupled to first voltage. The seventh switch is coupled to second voltage. The fourth switch, eighth switch and tenth switch are coupled to output capacitor. The first capacitor is coupled between first switch and second switch. The second capacitor is coupled between fifth switch and sixth switch. The third capacitor is coupled between seventh switch and eighth switch. The charge pump is operated in a first phase, a second-A phase, the first phase and a second-B phase in order to provide negative output voltage.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: July 21, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Pei-Kai Tseng, Chen-Pin Lo, Shen-Xiang Lin, Chih-Jen Hung
  • Patent number: 10720832
    Abstract: Circuits comprising: a capacitor; switches that, when State0, couple the capacitor in parallel with the load and, when State1, couple the capacitor in series with the load, wherein a first of the switches connects the capacitor to ground when in State0 and wherein a second of the switches connects the capacitor to an input voltage when in State1; a third switch, wherein a first side of the third switch is connected to the capacitor identically to one of the first switch and the second switch (OFWSW), wherein the third switch switches identically to the OFWSW, wherein the third switch is smaller than the OFWSW; a first resistor connected to the second side of the third switch; and a hardware processor that measures a current flowing through the first resistor and estimates the current provided to the load based on the current measured as flowing through the first resistor.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 21, 2020
    Assignee: Lion Semiconductor Inc.
    Inventors: Hans Meyvaert, Thomas Li, Fred Chen, John Crossley, Zhipeng Li, Bertram J. Rodgers
  • Patent number: 10713549
    Abstract: Embodiments are directed to rectifiers using a single bias current or bias current path to bias multiple rectifying elements. A rectifier that has multiple rectifier stages coupled together serially includes a bias current path coupled to each of the rectifier stages. Thee bias current path is configured to simultaneously bias rectifying elements in each of the rectifier stages by using a bias current to bias a first rectifying element and reusing the bias current to bias other rectifying elements.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Impinj, Inc.
    Inventors: Charles J. T. Peach, John D. Hyde, Jay A. Kuhn, Theron Stanford, Amita Patil
  • Patent number: 10707751
    Abstract: An electronic circuit includes a first switch circuit, a second switch circuit, a pumping circuit, and a main charge pump. The first switch circuit transfers a first driving voltage to a first node based on a first clock. The second switch circuit transfers a second driving voltage to a second node based on the first driving voltage of the first node. The pumping circuit outputs a pumping voltage having a level corresponding to a sum of a level of the second driving voltage and a first operation level of a second clock, based on the second driving voltage of the second node and the first operation level. The main charge pump converts an input voltage based on the pumping voltage.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bilal Ahmad Janjua, Sungwhan Seo, Vivek Venkata Kalluru
  • Patent number: 10699771
    Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Fifield, Dale E. Pontius
  • Patent number: 10686371
    Abstract: A power converter and method using a flying capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a driver circuit are presented. The first transistor is coupled between an input terminal and a first terminal of the flying capacitor. The second transistor is coupled between the first terminal of the flying capacitor and an output terminal. The third transistor is coupled between the output terminal and a second terminal of the flying capacitor. The fourth transistor is coupled between the second terminal of the flying capacitor and a reference potential. The driver circuit is coupled between a high side power rail and a low side power rail. There is a regulation circuit to regulate a high side voltage of the high side power rail such that the regulated high side voltage is independent of an input voltage at the input terminal.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 16, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Jong Lee, Sabin Eftimie
  • Patent number: 10680524
    Abstract: A voltage generator includes an oscillator, a charge pump, a smoothing capacitor, and a driving controller. The oscillator has an output. The charge pump has an input and an output, and the input of the charge pump is coupled to the output of the oscillator. The smoothing capacitor is coupled to the output of the charge pump. The driving controller is coupled to the oscillator, and generates an enable signal to adjust an operation frequency of the oscillator. The voltage generator supplies a driving voltage to a switch for driving the switch via the smoothing capacitor. The driving controller generates the enable signal according to the driving voltage.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 9, 2020
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng, Hsien-Huang Tsai
  • Patent number: 10673324
    Abstract: An isolated converter with switched capacitors can include: a first capacitor; a first group of switches coupled between two terminals of an input port, where the first group of switches is configured to selectively couple a first terminal of the first capacitor to one of a first terminal and a second terminal of the input port; a second group of switches coupled between two terminals of an output port, where the second group of switches is configured to selectively couple a second terminal of the first capacitor to one of a first terminal and a second terminal of the output port; and a second capacitor coupled between one of the first and second terminals of the input port and one of the first and second terminals of the output port.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 2, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Wang Zhang, Chen Zhao
  • Patent number: 10673315
    Abstract: A power supply conversion circuit is provided, which includes: a first voltage clamping module configured to decrease an input voltage to a preset low voltage; a boost module configured to increase the input voltage or the preset low voltage to a target voltage; a second voltage clamping module configured to maintain the target voltage within a preset voltage range; a filter module configured to filter out ripples in the target voltage; and at least one output module, each of which is configured to supply power to a load. Compared with a conventional LDO integrated circuit, the circuit can provide multiple output power supplies, and it is only required to additionally arrange one field effect transistor for one more output power supply. Therefore, the power supply conversion circuit has a simple structure, is expandable easily and is applicable to an analog integrated circuit requiring multiple output power supplies.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 2, 2020
    Assignee: Shanghai Awinic Technology Co., LTD
    Inventors: Xucheng Luo, Jianwei Hu, Jiantao Cheng
  • Patent number: 10673321
    Abstract: Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Marvell Asia Pte., Ltd.
    Inventors: Eric Hunt-Schroeder, John A. Fifield, Dale E. Pontius
  • Patent number: 10666136
    Abstract: A two dimensional charge pump and control circuitry is disclosed. The two dimensional charge pump includes a group of parallel-coupled charge pumps coupled between a DC power source and a first output connection node via a corresponding group of charge pump connection nodes. The group of parallel-coupled charge pumps has a corresponding group of clock connection nodes. Each of the group of parallel-coupled charge pumps includes a corresponding group of series capacitive elements coupled between a corresponding one of the group of charge pump connection nodes and a corresponding one of the group of clock connection nodes.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Khalifa University of Science and Technology
    Inventors: Abdulqader Nael Mahmoud, Mohammad Radwan Alhawari, Baker Mohammad, Hani Hasan Mustafa Saleh, Mohammed Ismail Elnaggar
  • Patent number: 10663136
    Abstract: A drive circuit for a motor is used in a light scanning vehicular lamp. The drive circuit includes an output stage, a pre-driver that controls the output stage, a clamp circuit that generates intermediate voltage that is limited so as not to exceed given voltage, and a booster circuit that receives the intermediate voltage and supplies internal power-supply voltage higher than the intermediate voltage to a power supply terminal of the pre-driver.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 26, 2020
    Assignee: KOITO MANUFACTURING CO., LTD.
    Inventor: Tomoyuki Ichikawa
  • Patent number: 10658011
    Abstract: A voltage generating system including: a voltage source, a clock generating circuit, and a voltage generating circuit. The voltage source generates a reference voltage. The clock generating circuit generates a first clock signal and a second clock signal according to the reference voltage. The voltage generating circuit including an output circuit and a switch circuit. The output circuit generates a control signal at a control node according to the first clock signal and the reference voltage, generates an output signal at an output node according to the second clock signal and the reference voltage. An absolute value of an amplitude of the output signal is greater than the reference voltage while an absolute value of an amplitude of the control signal is greater than the reference voltage. The switch circuit selectively outputs the output signal to an output terminal according to the control signal.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-An Chang, Yi-Chun Shih
  • Patent number: 10656666
    Abstract: A bias output apparatus includes: a plurality of voltage output circuits, each configured to output a bias voltage to be supplied to a load and a determination voltage generated based on the bias voltage; a determination circuit configured to output a binary determination signal based on the determination voltage output by each of the plurality of voltage output circuits; and a controller configured to control the plurality of voltage output circuits and determine whether or not the plurality of voltage output circuits are operating normally based on the determination signal output by the determination circuit. The controller is further configured to determine that the plurality of voltage output circuits are operating normally if an output pattern of the determination signal is a predetermined first pattern while the controller is controlling the plurality of voltage output circuits to output bias voltages in order.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 19, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hirohisa Nakajima
  • Patent number: 10644590
    Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: May 5, 2020
    Assignee: pSemi Corporation
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 10644016
    Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 5, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kuo Tung Chang, Shenqing Fang, Timothy Thurgate
  • Patent number: 10644497
    Abstract: Embodiments include a technique for using a charge pump for a distributed voltage passgate with high voltage protection. The technique includes receiving a reference signal, and preventing the reference signal from passing through a passgate to a circuit, wherein the passgate is an NFET passgate. The technique also includes charging the passgate using a charge pump circuit above the reference signal, and regulating the charge pump circuit using a clock signal. The technique also includes controlling the passgate based at least in part on the charge pump circuit.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kennedy K. Cheruiyot, Paul D. Muench, Michael A. Sperling, Michael R. Whalen
  • Patent number: 10637351
    Abstract: A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chia Liang Tai
  • Patent number: 10637456
    Abstract: A cascaded synchronous bootstrap supply circuit with reduced voltage drop between the cascaded bootstrap capacitors by replacing bootstrap diodes with gallium nitride (GaN) transistors. GaN transistors have a much lower forward voltage drop than diodes, thus providing a cascaded gate driver bootstrap supply circuit with a reduced drop in bootstrap capacitor voltage, which is particularly important as the number of levels increases.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 28, 2020
    Assignee: Efficient Power Conversion Corporation
    Inventors: David C. Reusch, Suvankar Biswas, Michael A. de Rooij
  • Patent number: 10637396
    Abstract: A transconductance controlling circuit is provided. The transconductance controlling circuit includes a resonance circuit, a negative-resistance unit-circuit and a transconductance boosting circuit. The resonance circuit generates an oscillation signal. The negative-resistance unit-circuit is coupled to a resonance circuit and includes a first transistor and a second transistor. The transconductance boosting circuit is coupled to the negative-resistance unit-circuit and includes a third transistor and a fourth transistor. A first drain of the first transistor is coupled to a third drain of the third transistor, a first gate of the first transistor is coupled to a third gate of the third transistor, the first gate of the first transistor is coupled to a second drain of the second transistor, and a first base of the first transistor is coupled to a fourth base of the fourth transistor and to a fourth source of the fourth transistor.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 28, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tai-Hsing Lee, Jie Zhang
  • Patent number: 10622899
    Abstract: A power converter for providing an output voltage is presented. The power converter includes an inductor, a charge pump circuit and a controller. The charge pump circuit has a plurality of charge pumps; each charge pump being selectively coupled to the inductor via a coupling switch. Each charge pump is operable in at least three modes. Each mode is associated with a different conversion ratio. The controller is adapted to provide a first set of control signals to control the coupling switches; and a second set of control signals to operate the charge pump circuit. The second set of control signals is configured to operate a charge pump coupled to the inductor with a sequence of modes.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 14, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Guillaume de Cremoux
  • Patent number: 10615790
    Abstract: A circuit for controlling body biasing of a transistor is disclosed. The transistor includes a first terminal, a second terminal, a gate and a body terminal. The circuit includes a body control circuit coupled to the first terminal and the second terminal. The body control circuit is configured to connect the body terminal to ground when a voltage at the second terminal is less than a fix predefined voltage. The body control circuit is further configured to connect the body terminal to the second terminal when voltage at the first terminal is higher than voltage at the second terminal and the voltage at the second terminal is higher than the fix predefined voltage, and to connect the body terminal to the first terminal when the voltage at the first terminal is less than the voltage at the second terminal and the voltage at the first terminal is higher than the fix predefined voltage.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Siamak Delshadpour, Peter Christiaans
  • Patent number: 10608529
    Abstract: An internal voltage veneration circuit includes negative voltage generation circuits of a first type and a second type, and the negative voltage generation circuits of the first type and the second type are connected parallel to each other. A drive signal is input to a charge pump circuit from a signal drive circuit in opposite phases in the negative voltage generation circuits of the first type and in the negative voltage generation circuits of the second type. A plurality of pairs of a negative voltage generation circuit of the first type and a negative voltage generation circuit of the second type are disposed, and the negative voltage generation circuit of the first type and the negative voltage generation circuit of the second type are located adjacent to each other.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 31, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Eiji Aoki, Yoshinao Morikawa
  • Patent number: 10606299
    Abstract: A circuit for regulating a leakage current in a charge pump is disclosed. The circuit includes a bias voltage generating circuit and a first transistor, wherein: the bias voltage generating circuit generates a bias voltage that is proportional to a supply voltage; a gate of the first transistor is coupled to the bias voltage; the first transistor has a drain that is coupled to an output of the charge pump and a source that is grounded; a voltage the drain of the first transistor is proportional to the supply voltage; and a current flowing through the source and drain of the first transistor is proportional to the supply voltage that powers the charge pump.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 31, 2020
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan Tang, Bin Sheng, Byoung Kwon Cha, Yi Xu, Jen-Tai Hsu
  • Patent number: 10601311
    Abstract: Circuits for a voltage regulator are provided, comprising: an inductor having a first side coupled to an input voltage; a first flying capacitor; a second flying capacitor; and a plurality of switches, wherein: in a first state, the plurality of switches couple: a second side of the inductor to a second side of the first flying capacitor and an output node; a first side of the first flying capacitor to a first side of the second flying capacitor; and a second side of the second flying capacitor to a voltage supply, in a second state, the plurality of switches couple: the second side of the inductor to the first side of the second flying capacitor; the second side of the second flying capacitor to the output node and the first side of the first flying capacitor; and the second side of the first flying capacitor to the voltage supply.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Lion Semiconductor Inc.
    Inventors: Hans Meyvaert, Zhipeng Li, Alberto Alessandro Angelo Puggelli, Thomas Li
  • Patent number: 10596807
    Abstract: A capacitive load driving circuit includes a first switching element, a second switching element, a third switching element, a fourth switching element and voltage dropper elements. The first switching element is provided on a first charging path extending from a power supply to a capacitive load. The second switching element is provided on a second charging path extending from a capacitor to the capacitive load. The third switching element is provided on a first discharging path extending from the capacitive load to a ground. The fourth switching element is provided on a second discharging path extending from the capacitive load to the capacitor. The voltage dropper elements are provided on each of control signal power supply paths to the first switching element, to the second switching element, to the third switching element and to the fourth switching element.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 24, 2020
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Chikaho Ikeda
  • Patent number: 10594210
    Abstract: A two-stage power converter includes a dual-level driver to control a current conducted by a switch transistor in a charge pump to control the charging of a flying capacitor in the charge pump.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 17, 2020
    Assignee: DIALOG SEMICONDUCTOR (UK) LIMITED
    Inventors: Mark Mercer, Karthik Jayaraman, Chanchal Gupta, Kevin Dowdy
  • Patent number: 10587267
    Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Biraja Prasad Dash, Ravinthiran Balasingam, Dimitar Trifonov
  • Patent number: 10587190
    Abstract: Circuits, methods, and system for DC voltage conversion are disclosed. A charge pump circuit is described that includes input switches and output switches that are individually controlled by different clock signals to alternatively couple energy storage capacitors to an input and to an output. The individualized switching control allows for the use of clock signals with no overlapping transitions to improve conversion efficiency. Additionally, the input switches are controlled by clock signals that are level shifted relative to the input voltage. The level shifted switching control also improves efficiency and allows for a range in input voltages to be accommodated for DC voltage conversion.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jan Matej, Pavel Londak, Petr Rozsypal
  • Patent number: 10573353
    Abstract: Methods of operating a voltage generation circuit include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the output of the voltage driver to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of an output of the voltage driver is less than a threshold, connecting the output of the voltage driver to a second voltage node configured to receive a second voltage, greater than the first voltage, when the clock signal has the particular logic level and the voltage level of the output of the voltage driver is greater than the threshold, and connecting the output of the voltage driver to a third voltage node configured to receive a third voltage, less than the first voltage, when the clock signal has a different logic level.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Marcerola, Marco-Domenico Tiburzi, Stefano Perugini
  • Patent number: 10566898
    Abstract: A negative voltage circuit comprises an inverter circuit that performs a charging operation and a discharging operation, a first dual current circuit supplying a first current for a charging operation of the inverter circuit based on a start-up mode, and a second current for the charging operation of the inverter circuit based on a normal operating mode, a second dual current circuit supplying a third current for a discharging operation of the inverter circuit based on the start-up mode, and a fourth current for the discharging operation of the inverter circuit based on the normal operating mode, a load switching circuit that connects an output node of the inverter circuit to one of an output terminal of a negative voltage circuit and the second operating voltage terminal, and a load capacitor circuit connected between the output terminal and a ground to stabilize a negative voltage at the output terminal.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: February 18, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyun Paek, Byeong Hak Jo
  • Patent number: 10560016
    Abstract: Cross-coupled charge-pumps. At least some of the example embodiment are methods including: pumping charge from a first capacitor through a first field effect transistor (FET) to a voltage output and from a second capacitor through a second FET to the voltage output of the charge pump; refreshing charge to a third capacitor and a fourth capacitor during the pumping of charge; electrically isolating the first through fourth capacitors during a dead time; and then pumping charge from the third capacitor through a third FET to the voltage output and from the fourth capacitor through a fourth FET to the voltage output of the charge pump; and refreshing charge to the first capacitor and the second capacitor during the pumping of charge from the third and fourth capacitors.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Pierre Genest
  • Patent number: 10554147
    Abstract: There is provided a converter for converting a received RF signal into a DC signal for powering a load, the converter comprising: a rectifier arranged to generate, based on the RF signal, the DC signal and one or more harmonics of the RF signal, and to output the DC signal and the one or more harmonics together with a component of the RF signal; a first planar transmission line arranged to guide the received RF signal to the rectifier; and a second planar transmission line arranged to receive from the rectifier the DC signal, the component of the RF signal and the one or more harmonics from the rectifier, and to reflect the one or more harmonics back towards the rectifier. The first planar transmission line is further arranged to reflect back towards the rectifier RF signals from the rectifier that are based on the reflected signals. The converter further comprises a low-pass filter for supplying the DC signal to the load, the low-pass filter comprising an inductor and a third planar transmission line that.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: February 4, 2020
    Assignee: DRAYSON TECHNOLOGIES (EUROPE) LIMITED
    Inventors: Manuel Pinuela Rangel, Bruno Roberto Franciscatto