AUTOMATIC IN-SITU CONTROL OF AN ELECTRO-PLATING PROCESSOR

Abstract

In an electroplating processor having at least one anode and one thief electrode, reference electrodes are used to measure a voltage gradient in the electrolyte near the edge of the wafer. The voltage gradient is used to calculate the current at the wafer surface using a control volume/current balance technique. The fraction of the total wafer current flowing to the edge region of the wafer is determined and compared to a target value. The processor controller changes at least one of the anode and thief currents to bring the actual edge region current toward the target current.

Description

This application relates to chambers, systems, and methods for electrochemically processing semiconductor material wafers, and similar workpieces or substrates having micro-scale devices.

BACKGROUND OF THE INVENTION

Microelectronic devices, such as semiconductor devices, are generally fabricated on and/or in semiconductor material wafers or workpieces using several different types of machines. In a typical manufacturing process, one or more layers of conductive materials, such as metals, are formed on a wafer. The wafer is then typically etched or polished to remove a portion of the conductive layers, to form contacts, conductive lines, or other components.

As microelectronic devices are made ever smaller, the seed layer must also be made ever thinner. With very thin seed layers, the sheet resistance at the start of the electroplating process may be as high as, for example 50 Ohm/sq, whereas the final sheet resistance of the electroplated film or layer on the wafer may be below 0.02 Ohm/sq. With conventional electroplating machines, this three orders of magnitude change in sheet resistance can make it difficult or impossible to consistently provide uniform layers and void-free filling.

Electroplating processors generally have one or more anode electrodes, and a current thief electrode, with the seed layer being the cathode. The electrode set-points, i.e. the electrical current provided from each electrode over time, are estimated ahead of time and must be reconsidered for each type of wafer and electrolyte bath. Even when the electrode set-points are chosen carefully, the resulting quality and characteristics of the plated layer or film may be less than optimal, due to the large number of variables involved. Accordingly, improved electroplating machines and methods are needed.

SUMMARY OF THE INVENTION

In an electroplating processor having at least one anode and one thief electrode, two or more reference electrodes are used to measure a voltage gradient in the electrolyte near the edge of the wafer. The voltage gradient is used to calculate the current flowing radially outward within the plating bath near the outer portion of the wafer. Using this radial current within a control volume/current balance technique, the fraction of the total wafer current flowing to the edge region of the wafer is determined and compared to a target value. The processor controller changes the anode and thief currents to bring the actual edge region current toward the target current.

In one aspect, only two reference electrodes are needed. A low thief current may be initially used (to avoid the risk of deplating). The current to the electrodes may then be adjusted automatically via the controller based on the perceived sheet resistance of the wafer, as indicated by the calculated wafer current.

Other and further objects and advantages will appear from the following description and drawings which show examples of how this new processor may be designed, along with methods for processing. The invention resides as well in sub-combinations of the elements described.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, the same element number indicates the same element in each of the views.

FIG. 1 is an exploded perspective view of an electrochemical processor.

FIG. 2 is a perspective view cross section of the vessel assembly shown in FIG. 1.

FIG. 3 is an enlarged section view of the vessel assembly.

FIG. 4 is a schematic perspective view section of the upper cup shown in FIG. 3.

FIG. 5 is a schematic diagram of a control volume adjacent to the edge of a wafer in the processor shown in FIG. 1.

FIG. 6 is a schematic diagram of a control volume adjacent to the edge of a wafer in an alternative processor.

FIG. 7 is an enlarged detail view of the control volume shown in FIG. 6.

FIG. 8 is a graph of slot current vs. radial current.

FIG. 9 is a graph of extra thief electrode current vs. estimated radial current.

DETAILED DESCRIPTION OF THE DRAWINGS

A control system and method allow for automatically controlling the electrode set points of one or more anodes and a current thief in an electroplating processor, based on real time measurements within the processor. This reduces reliance on making set point estimates and provides improved electroplating.

An objective is to determine the current at the wafer surface, since this is a primary factor effecting the quality and uniformity of the electroplated film. If the current at the wafer surface is known in real time, the current to the electrodes may be adjusted as needed to achieve desired results. Determining the current to just one portion of wafer (i.e. the edge portion) may be sufficient to properly control the reactor currents.

Electroplating patterned copper damascene wafers presents additional challenges in determining the initial electrode set points because the seed layer covers complex feature patterning. Consequently, the initial sheet resistance is unknown Changes in sheet resistance as features (such as trenches or vias on the wafer) fill from the bottom up, cannot be accurately predicted. The present method overcomes these factors by detecting the initial sheet resistance via the calculated wafer current. The controller then compensates in real time for the changing sheet resistance during the plating process.

Turning now in detail to the drawings, FIGS. 1-4 show a representative electroplating processor. The concepts of the invention however are applicable to virtually any processor having at least one anode and a current thief electrode. As shown in FIG. 1, an electro-chemical processor 20 has a head 30 positioned above a vessel assembly 50. The vessel assembly 50 may be supported on deck plate 24 attached to a stand 38 or other structure. The head 30 may be supported on a lift/rotate unit 34, for lifting and inverting the head to load and unload a wafer 10 into the head, and for lowering the head 30 into engagement with the vessel assembly 50 for processing.

Referring now to FIGS. 2-3, the vessel assembly 50 may include an anode cup 52, a lower membrane support 54, and an upper membrane support 56 held together with fasteners 60. Within the anode cup 52, a first or inner anode 70 is positioned near the bottom of an inner anolyte chamber 110. A second or outer anode 72 is positioned near the bottom of an outer anolyte chamber 112 surrounding the inner anolyte chamber 110. The anodes may be provided as consumable anode material (i.e. copper pellets, balls, etc.)

As shown in FIG. 2, the inner anode 70 is electrically connected to a first electrical lead or connector 130 and the outer anode 72 is electrically connected to a separate second electrical lead or connector 132. A current thief electrode 206 may surround the upper end of the upper cup 76.

Turning now to FIGS. 3-4, an upper cup 76, if used, may be contained within or surrounded by an upper cup housing 58. The upper cup housing 58 is attached to and sealed against the upper cup 76. The upper cup 76 has a curved top surface 124 and a central through opening that forms a central or inner catholyte chamber 120. This chamber 120 is defined by the generally cylindrical space within a diffuser 74 leading into the bell or horn shaped space defined by the curved upper surface 124 of the upper cup 76. A series of concentric annular slots extend downwardly from the top curved surface 124 of the upper cup 76. An outer catholyte chamber 78 formed in the bottom of the upper cup 76 is connected to the slots via an array of tubes or other passageways.

As shown in FIG. 4, in one example, eight circumferential slots 90, 92, 94, 96, 98, 100, 102 and 104 extend down from the curved upper surface 124 of the upper cup 76. The slots are narrow so that the liquid electrolyte filling the volume in the slots has high electrical resistance. The slots are typically between 1 to 5 mm, or 2-4 mm wide. The circumferential slots are connected into the outer catholyte chamber 78 by vertical tubes 104A, 102A, 100A and 98A. In the specific example shown there are 18 tubes connecting into each slot. The tubes are the primary source of electrical resistance. The slots help redistribute (i.e. fan out) the current flowing through the tubes to a uniform axisymmetric source so that the rotating wafer sees uniform current as it rotates (rather than maxima and minima if the wafer were to rotate over the holes). The slots are placed and the width chosen to properly distribute the outer anode current across the outer portion of the wafer. Design elements of the processor 20 are described in U.S. patent application Ser. No. 13/110,728, incorporated herein by reference.

Turning to FIG. 5, a control volume 210 is selected near the edge of the wafer 10. The control volume 210 has an inner circumferential boundary 212, and outer circumferential boundary 214, a lower boundary 216 and an upper boundary 218. The control volume 210 and its boundaries are mathematical constructs useful in describing the present system and methods. They are not physical elements.

For a processor designed for 300 mm diameter wafers, the inner boundary 212 may be located 100 to 130 mm from the wafer center. An inner probe or reference electrode 202 is located inward of the inner boundary 212. An outer probe or reference electrode 204 is located outward of the inner boundary 212, so that the outer probe 204 is within the control volume 210. The probes 202 and 204 are actual physical elements, such as wires. The probes may also be provided as electrolyte filled capillary tubes leading to an actual physical electrode or wire. The probes 202 and 204 may be electrically connected to the controller 200. The probes 202 and 204 may be flush with the upper surface of the upper cup, to reduce or avoid altering the electrolyte and electrical current flow in the processor.

In use, the probes measure a voltage gradient. The difference between the voltage measured at the inner and outer probes is used to calculate current flow (radially outward) through the inner boundary, using Ohm's law V=IR, where V is the measured voltage difference, R is the resistance of the liquid electrolyte over the distance DD between the probes, and I is the current flowing in through inner boundary, or radial current flux I/radial-in. The greater DD, the greater the measured voltage will be for a given radial current. Typically DD may range from 10 to 60 mm or more, depending on the diameter of the wafer, with typical values being 10 to 30 mm. R is known based on the measured resistance of the electrolyte (or provided by the manufactured) and the known distance DD between the probes. In the example shown in FIG. 5, the inner probe 202 is at a radius of 120 mm (120 mm from the wafer center position) and the outer probe 204 is at 140 mm, so that DD is about 20 mm.

The current I/radial-out flowing out of the control volume 210 through the outer boundary 214 is set equal to the thief current which is known, for example via an ammeter connected to the thief electrode 206. Although FIG. 5 shows the wafer edge extending radially outward beyond the control volume, the control volume may optionally be selected so that the outer boundary 214 is beyond the wafer edge, so that equating I/radial-out to the thief current introduces little or no error.

The total current I/vertical-in flowing into the control volume 210 through the lower boundary 216 is equal to the current flowing through the electrolyte in the slots 102 and 104. The upper cup 76 is made of a dielectric material, so that all current flowing through the upper cup necessarily flows only in the electrolyte filled slots in the upper cup. The current though the slots is a fraction of the outer anode current, the inner anode current and the thief electrode current. If large radial voltage gradients are created within the reactor due to high sheet resistance or by high thief electrode current, these voltage gradients cause a current flow down the inner slots (90,92,94,96) and back up the outer slots (98,100,102,104). Current flow through the slots can actually be accurately determined from the radial current measured by the probes. The current flow though the slots 102 and 104 in FIG. 5 is a function of the outer anode current and the radial current through the inner boundary 212 of the control volume. Consequently, for any currents used within the reactor (dialed-in sets or not dialed-in), the fraction of the outer anode current through slots 102 and 104 is accurately predicted by the equation of a line with the “x” value being the measured current as calculated from the reference electrodes.

In summary, by using the single voltage difference between the two reference electrodes to compute the radial current flow in the processor, the current across two sides of the control volume can be accurately determined (212 using equation 2 discussed below, and 218 by using the plot shown in FIG. 8.) This same single radial current from the two probes can also be used to determine the “gain” used to compute a new set of currents to drive the wafer edge current to its target.

As shown in FIG. 9 the “gain” is shown to vary from 1 to 8 depending on the radial current. As the proper gain can vary widely, using a proper value is necessary to arrive quickly to the wafer target and to stay on target. Modeling shows that the proper “gain” most accurately follows a linear relationship from the radial current when the currents being used within the reactor are already near the “dial-in” currents. So, the algorithm gets more accurate as the wafer current nears the target.

The target (% of total wafer current to the wafer area within the control volume) is a value generally equal to the amount of wafer area within the control volume (i.e. 26.5% for a flat profile). However, a slight adjustment to the target vs. the radial current is appropriate to compensate for small errors from using just two probes to compute the reactor radial current. All of the unknowns in the control algorithm can be expressed as functions of the single current flux calculation. These unknowns are the control volume boundaries 212 and 218, the gain, and the % wafer current target. The instrumentation needed within the chamber to control the process may therefore be relatively simple.

As shown in FIG. 5, upper and lower slot probes 220 and 222 may be added in the slot 104, as well as in the slot 102, to detect voltage change in the slot, with the voltage change used to calculate current flow in the slot.

Since the current flowing into the control volume must equal the current flowing out of the control volume, I/radial-in plus I/vertical-in must equal I/radial-out plus I/vertical-out. I/vertical-out is set as the actual current at the wafer surface in the control volume. I/vertical-out is calculated from equation 1 below.

I/vertical-out=I/radial-in+I/vertical-in−I/radial-out.  1]

Especially when plating onto very thin seed layers, the sheet resistance changes very rapidly, i.e., by an order or magnitude in a few milliseconds. The current at the wafer surface, or I/vertical-out, is a function of the sheet resistance (when electrode currents are constant). With I/vertical-out known instantaneously, the controller 200 may vary the current provided to the anodes and thief electrode in real time, to achieve improved electroplating results, even with rapid change in sheet resistance. The anode(s) and thief electrode currents may be adjusted as quickly as every 2.5 milliseconds.

The control volume 210 in FIG. 5 is shown in two-dimensions. Although the probes essentially measure a two dimensional gradient, while current in the processor flows in three dimensions, mathematical modeling suggests that use of the two probes provides good accuracy. For a three-dimensional control volume, the current flowing radially into the control volume may be estimated from equation 2 below.

I_Rad=K_bath(V2−V1/R2−R1)2πR_aveh_gap  2]

where K is the bath conductivity and h_gap is the vertical gap or space between the down facing surface of the wafer and the top surface of the upper cup at the current flux measurement location. The current flux measurement location is the location generally halfway between the inner probe 202 and the outer probe 204. Alternatively, a duplicate pair of reference electrodes at 180 degrees may be used to get better estimates of the three dimensional current flow through boundary 212. A reference electrode in the form or a ring may also optionally be used to get a better three dimensional estimate of the voltage difference and flux. The probes are effectively located in a position where a single voltage difference can accurately compute the current flowing radially outward.

Referring to FIGS. 2 and 5, the controller 200 is electrically connected to the probes 202 and 204 and uses inputs from the probes to calculate the voltage gradient. The controller then calculates I/vertical-out as described above. The calculated I/vertical-out can then be compared to a stored target value. The difference between them provides an error signal. The controller uses the error signal to adjust the currents supplied by the anode(s) and the thief electrode. If I/vertical-out is too high, the controller can increase the thief current to decrease it.

To simplify the control, especially in processors having two or more anodes, the processor may be set up so that current to the outer anode is constant for all sheet resistances, e.g., by selecting a specific height of the head 30. Then, only the thief current ratio needs to be controlled, based I/vertical-out. The thief current ratio is the ratio of the thief current to the inner anode current. Adjusting only the thief current ratio simplifies the control with processors having two or more anodes.

In one form the method may be performed as follows:

a. Find the electric potential at the probe locations for any current set and wafer sheet resistance.

b. Calculate the radial current flux using the measured voltage gradient between the probes.

c. Using the control volume analysis as described above to determine the current going to the wafer edge.

d. Compare the wafer edge current to the target edge current.

e. Calculate a new set of currents to drive the wafer edge current to the target.

FIGS. 6 and 7 show the method described above as applied to a generic electroplating processor having a single anode 300, a single thief electrode 206, and a diffuser 302 having very high electrical resistance, so that current density at the lower boundary of the control volume is substantially uniform.

The target value for the edge current can be adjusted to yield edge thick or thin profiles. Empirical adjustment of the target can be used to flatten the profile to account for system errors. For example, a 27.5% target current may yield a flatter profile instead of 26.75%. Calibration of the probe calculation of radial current flux can be accomplished by flowing a specified current between the inner anode and the thief electrode using an insulated wafer (or bare silicon wafer). All the current is then radial allowing a check or a setting of the required factors (bath conductivity, wafer-to-wall gap, probe radial distance). Automatic, in-situ control can be used to “write” dynamic current control (DCC) recipes for various product wafers (i.e., the instantaneous current from each electrode over time). The recorded DCC recipe can be used in production, so that the same recipe is always used on each wafer. The correction “sensitivity” derivative (i.e. gain) may be calculated “on-the-fly” with the response in a prior iteration used to predict the “sensitivity” for the next iteration.

The term wafer as used here includes other substrates and workpieces having microelectronic, micro-mechanical, and/or micro-optical devices. The methods described may be used in processors having one or more anodes and a single thief electrode. The term connected or electrically connected as used here includes both wired and wireless connections.

Thus, a novel system and method has been shown and described. Various changes and substitutions may be made without departing from the spirit and scope of the invention. The invention, therefore, should not be limited except by the following claims and their equivalents.

Claims

1. An electroplating processor, comprising:

a vessel for holding electrolyte;

at least one anode, a current thief and a field shaping element in the vessel;

first and second spaced apart reference electrodes, with the first reference electrode located between a center position of the vessel and the second reference electrode; and

a controller electrically connected to the at least one anode, the current thief and the first and second reference electrodes.

2. The processor of claim 1 with the first and second reference electrodes located on a common radius extending radially outward from the center position.

3. The processor of claim 1 with the first and second electrodes in or on the field shaping unit.

4. The processor of claim 1 with the field shaping unit comprising an upper cup having a curved top surface and a plurality of circumferential slots, and with at least one circumferential slot between the first and second reference electrodes.

5. The processor of claim 1 with the thief electrode comprising a ring extending around an upper edge of the vessel, and with the second reference electrode between the thief electrode and the first reference electrode.

6. The processor of claim 2 with the vessel having a radius R and with the first electrode located at least 0.65 R from the center position.

7. The processor of claim 1 further comprising a head engageable with the vessel, and with the head having a wafer holding position for holding a wafer 5-30 mm above the second reference electrode.

8. The processor of claim 1 with the second reference electrode at a vertical position higher than the first reference electrode.

9. The processor of claim 4 further including supplemental reference electrodes in one or more of the circumferential slots.

10. A method of controlling an electroplating processor having at least one anode and a thief electrode, comprising:

determining a voltage gradient in an electrolyte adjacent to an edge of a wafer;

determining a radial electric current flow into a volume of electrolyte adjacent to the edge of the wafer using the voltage gradient;

determining a radial electric current flow out of the volume to a thief electrode;

determining a vertical electric current flow into the volume;

calculating electric current flow to the wafer surface by subtracting the radial current flow to the thief electrode from the sum of radial current flow into the volume and the vertical electrical current flow into the volume;

determining an error value by subtracting the current flow to the wafer surface from a target value;

using the error value to control electrical current flow to at least one of the anode and the thief electrode.

11. The method of claim 10 further comprising determining a sheet resistance based on the electric current flow to the wafer surface.

12. The method of claim 10 with the processor having an inner anode and an outer anode and the wafer in a head, with the current from the outer anode held constant for all sheet resistances by selecting a specific height of the head relative to the electrolyte surface, and further comprising controlling the thief current.