External Physical Configuration Of Semiconductor (e.g., Mesas, Grooves) Patents (Class 257/466)
  • Patent number: 9953953
    Abstract: Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: April 24, 2018
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean Brun
  • Patent number: 9941662
    Abstract: A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 10, 2018
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Yuji Masui, Yoshinori Yamauchi, Rintaro Koda, Takahiro Arakida
  • Patent number: 9806221
    Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 31, 2017
    Assignee: GlobalFoundries, Inc.
    Inventors: Steven M. Shank, John J. Ellis-Monaghan, Marwan H. Khater, Jason S. Orcutt
  • Patent number: 9576990
    Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: February 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Po-Li Shih
  • Patent number: 9437644
    Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 6, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi Eikyu, Atsushi Sakai, Hiroyuki Arie
  • Patent number: 9437750
    Abstract: A method for forming a TFT includes providing a substrate, and forming a gate electrode, an electrically insulating layer, a semiconductor layer, an etch stop layer and a photoresist layer successively on the substrate. A photolithographic process is performed to the photoresist layer by using a half-tone mask to thereby configure the photoresist layer to have two recesses in a top thereof. Two lateral ends of the etch stop layer are etched away to form an etch stop pattern. The photoresist layer is heated to flow downwardly. Two lateral ends of the semiconductor channel are etched away to become a channel layer. An ashing is performed to the photoresist layer to have the recesses thereof communicate atmosphere with the etch stop pattern. The etch stop pattern is etched to define first and second through holes. Source and drain electrodes are formed to electrically connect with the channel layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: September 6, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Po-Li Shih
  • Patent number: 9178112
    Abstract: A light emitting device having a light extraction structure, which is capable of achieving an enhancement in light extraction efficiency and reliability, and a method for manufacturing the same. The light emitting device includes a semiconductor layer having a multi-layered structure including a light emission layer; and a light extraction structure formed on the semiconductor layer in a pattern having unit structures. Further, the wall of each of the unit structures is sloped at an angle of ?45° to +45° from a virtual vertical line being parallel to a main light emitting direction of the light emitting device.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: November 3, 2015
    Assignees: LG ELECTRONICS INC., LG INNOTEK CO., LTD.
    Inventor: Sun Kyung Kim
  • Patent number: 9035410
    Abstract: An avalanche photodiode detector is provided. The avalanche photodiode detector comprises an absorber region having an absorption layer for receiving incident photons and generating charged carriers; and a multiplier region having a multiplication layer; wherein the multiplier region is on a mesa structure separate from the absorber region and is coupled to the absorber region by a bridge for transferring charged carriers between the absorber region and multiplier region.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 19, 2015
    Assignee: THE BOEING COMPANY
    Inventors: Ping Yuan, Joseph C. Boisvert, Dmitri D. Krut, Rengarajan Sudharsanan
  • Publication number: 20150098482
    Abstract: Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Inventors: Chee Siong Peh, Chiew Hai NG, David G. McIntyre
  • Patent number: 8969470
    Abstract: A quantum dot-polymer nanocomposite for optical chemical and biological sensing is formed by stably incorporating functionalized quantum dots into a pH sensitive hydrogel polymer network. At least one monomer of the pH sensitive hydrogel has functional groups selectively chosen to correspond to functionalized groups on the quantum dots to enable conjugation between the hydrogel polymer network and the functionalized quantum dots. The resulting quantum dot-polymer nanocomposite is placed in a solution having a known pH and addition of a chemical composition or biological agent of interest generates a change in pH of that solution. The nanocomposite expands or contracts responsive to the pH change. The pH change is optically detected by measuring the intensity level of fluorescence from the quantum dots when the nanocomposite is subjected to an excitation light source.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 3, 2015
    Assignee: The Mitre Corporation
    Inventor: Sichu Li
  • Patent number: 8958011
    Abstract: Bi-directional camera modules and flip chip bonders including the same are provided. The module includes a circuit board on which an upper sensor and a lower sensor are mounted, an upper lens and a lower lens disposed on the upper sensor and under the lower sensor, respectively, and a housing fixing the upper lens and the lower lens spaced apart from the upper sensor and the lower sensor, respectively. The housing surrounds the circuit board. The housing has a plurality of inlets and an outlet through which air flows, and the housing has an air passage connected from the inlets to the outlet via a space between lower lens and the lower sensor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Sick Park, Myung-Sung Kang, Ji-Seok Hong
  • Publication number: 20150028444
    Abstract: An infrared detection element includes a substrate, a lower electrode layer, a pyroelectric layer, and an upper electrode layer. The lower electrode layer is fixed to the substrate, and the pyroelectric layer is formed on the lower electrode layer. The upper electrode layer is formed on pyroelectric layer. The lower electrode layer contains pores therein and has a larger thermal expansion coefficient than the pyroelectric layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: January 29, 2015
    Inventors: Toshinari NODA, Takashi KUBO, Hisao SUZUKI, Naoki WAKIYA, Naonori SAKAMOTO
  • Publication number: 20140374870
    Abstract: Disclosed herein are an image sensor module and a method of manufacturing the same. The image sensor includes: a base substrate having an image sensor mounted groove including a first groove and a second groove having a stepped shape; and an image sensor mounted in a groove of the base substrate.
    Type: Application
    Filed: January 31, 2014
    Publication date: December 25, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyung Ho Lee, Suk Jin Ham, Seung Wan Woo, Yee Na Shin
  • Patent number: 8901697
    Abstract: An integrated circuit having an insulated conductor or within a semiconductor substrate and extending perpendicular to a plane of a semiconductor wafer or substrate on which the integrated circuit is fabricated, the conductor comprising a first region of doped semiconductor extending between a first device or a first contact and a second device or a second contact.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Bernard Patrick Stenson
  • Patent number: 8901694
    Abstract: An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Joong-Han Shin, Byung-Lyul Park, Gil-Heyun Choi
  • Patent number: 8896077
    Abstract: An optoelectronic device comprising an optically active layer that includes a plurality of domes is presented. The plurality of domes is arrayed in two dimensions having a periodicity in each dimension that is less than or comparable with the shortest wavelength in a spectral range of interest. By virtue of the plurality of domes, the optoelectronic device achieves high performance. A solar cell having high energy-conversion efficiency, improved absorption over the spectral range of interest, and an improved acceptance angle is presented as an exemplary device.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: November 25, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Yi Cui, Jia Zhu, Ching-Mei Hsu, Shanhui Fan, Zongfu Yu
  • Patent number: 8883529
    Abstract: A semiconductor light emitting device having high reliability and excellent light distribution characteristics can be provided with an n-electrode arranged on a light extraction surface on the side opposite to the surface whereupon a semiconductor stack is mounted on a substrate. A plurality of convexes are arranged on a first convex region and a second convex region on the light extraction surface. The second convex region adjoins the interface between the n-electrode and the semiconductor stack, between the first convex region and the n-electrode. The base end of the first convex arranged in the first convex region is positioned closer to a light emitting layer than the interface between the n-electrode and the semiconductor stack, and the base end of the second convex arranged in the second convex region is positioned closer to the interface between the n-electrode and the semiconductor stack than the base end of the first convex.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 11, 2014
    Assignee: Nichia Corporation
    Inventors: Yohei Wakai, Hiroaki Matsumura, Kenji Oka
  • Publication number: 20140319547
    Abstract: A method of producing a plurality of optoelectronic semiconductor chips includes a) providing a layer composite assembly having a principal plane which delimits the layer composite assembly in a vertical direction, and includes a semiconductor layer sequence having an active region that generates and/or detects radiation, wherein a plurality of recesses extending from the principal plane in a direction of the active region are formed in the layer composite assembly; b) forming a planarization layer on the principal plane such that the recesses are at least partly filled with material of the planarization layer; c) at least regionally removing material of the planarization layer to level the planarization layer; and d) completing the semiconductor chips, wherein for each semiconductor chip at least one semiconductor body emerges from the semiconductor layer sequence.
    Type: Application
    Filed: November 12, 2012
    Publication date: October 30, 2014
    Inventors: Patrick Rode, Lutz Hoeppel, Norwin von Malm, Stefan Illek, Albrecht Kieslich, Siegfried Herrmann
  • Patent number: 8872295
    Abstract: A thin film photovoltaic device comprising a relief textured transparent cover plate, a layer of transparent conductive oxide having a layer thickness of less than 700 nm, a light absorbing active layer and a reflective back electrode, where the layer of transparent conductive oxide is a non-textured layer.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 28, 2014
    Assignees: DSM IP Assets B.V., Schüco TF GmbH & Co., KG
    Inventors: Ko Hermans, Benjamin Slager, Bart Clemens Kranz, Andreas Hofmann
  • Patent number: 8860162
    Abstract: A solar module includes a solar cell, a heat spreader layer disposed above the solar cell, and a cell interconnect disposed above the solar cell. From a top-down perspective, the heat spreader layer at least partially surrounds an exposed portion of the cell interconnect.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: October 14, 2014
    Assignee: Sunpower Corporation
    Inventors: Ryan Linderman, Matthew Dawson, Itai Suez
  • Patent number: 8860164
    Abstract: A light receiving element includes a core configured to propagate a signal light, a first semiconductor layer having a first conductivity type, the first semiconductor layer being configured to receive the signal light from the core along a first direction in which the core extends, an absorbing layer configured to absorb the signal light received by the first semiconductor layer, and a second semiconductor layer having a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazumasa Takabayashi
  • Patent number: 8772075
    Abstract: A display region and a light sensing region are defined in each pixel region of the OLED touch panel of the present invention. The readout thin film transistor of the light sensing region is formed by the same processes with the drive thin film transistor of the display region. The top and bottom electrodes of the optical sensor are formed by the same processes with the top and bottom electrodes of the OLED. Accordingly, the present invention can just add a step of forming the patterned sensing dielectric layer to the processes of forming an OLED panel to integrate the optical sensor into the pixel region of the OLED panel. Thus, an OLED touch panel is formed.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 8, 2014
    Assignee: AU Optronics Corp.
    Inventors: An-Thung Cho, Jung-Yen Huang, Chia-Tien Peng, Chun-Hsiun Chen, Wei-Ming Huang
  • Patent number: 8772896
    Abstract: In order to improve reliability by preventing an edge breakdown in a semiconductor photodetector having a mesa structure such as a mesa APD, the semiconductor photodetector includes a mesa structure formed on a first semiconductor layer of the first conduction type formed on a semiconductor substrate, the mesa structure including a light absorbing layer for absorbing light, an electric field buffer layer for dropping an electric field intensity, an avalanche multiplication layer for causing avalanche multiplication to occur, and a second semiconductor layer of the second conduction type, wherein the thickness of the avalanche multiplication layer at the portion in the vicinity of the side face of the mesa structure is made thinner than the thickness at the central portion of the mesa structure.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: July 8, 2014
    Assignees: Fujitsu Limited, Sumitomo Electric Device Innovations, Inc.
    Inventors: Nami Yasuoka, Haruhiko Kuwatsuka, Toru Uchida, Yoshihiro Yoneda
  • Patent number: 8735228
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 27, 2014
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Patent number: 8729539
    Abstract: Provided is a light-emitting apparatus which, without using an insulating film for separating pixels, inhibits leakage current between adjacent pixels and which accommodates higher resolution. By providing a groove in an insulating layer along an edge of a first electrode, the thickness of a first charge transport layer is reduced to inhibit leakage current between adjacent pixels.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: May 20, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuaki Kakinuma, Seishi Miura, Koichi Ishige, Nobuhiko Sato
  • Patent number: 8723286
    Abstract: Coil units are disclosed for use in electrical circuits. An exemplary coil unit comprises a rigid substrate having an electrically non-conductive three-dimensional (3-D) surface. At least one 3-D coil (shaped, for example, as a helical coil) of semiconductor material is formed on the substrate surface. Disposed on the at least one coil of semiconductor material is a 3-D coil of a conductive metal. The coil of conductive metal is situated sufficiently closely to the at least one coil of semiconductor material for the coil of conductive metal to produce Coulombic drag in the at least one coil of semiconductor material when the coils are conductive of low-mass electrons. The semiconductor material can be a photoconductor or other material that has conductive low-mass electrons.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 13, 2014
    Assignee: Levitronics, Inc.
    Inventor: William N. Barbat
  • Patent number: 8710614
    Abstract: A light receiving element includes a core configured to propagate a signal light, a first semiconductor layer having a first conductivity type, the first semiconductor layer being configured to receive the signal light from the core along a first direction in which the core extends, an absorbing layer configured to absorb the signal light received by the first semiconductor layer, and a second semiconductor layer having a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazumasa Takabayashi
  • Patent number: 8703525
    Abstract: A solar cell includes; a substrate; a first electrode disposed on the substrate, and including a first groove formed therein, a semiconductor layer disposed on the first electrode, and including a second groove formed therein, and a second electrode disposed on the semiconductor layer and connected to the first electrode via the second groove, wherein a third groove passing through the first electrode, the semiconductor layer, and the second electrode is formed in a first region, a fourth groove passing through only the semiconductor layer and the second electrode is formed in a second region, and the first region and the second region are alternately disposed along a direction of extension of the third groove.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 22, 2014
    Assignees: Samsung SDI Co., Ltd., Samsung Display Co., Ltd.
    Inventor: Joong-Hyun Park
  • Publication number: 20140103480
    Abstract: A mask for partially blocking ultraviolet rays in TFT glass substrate manufacturing process is disclosed. The mask includes a panel pattern area for forming the panel patterns, and an additional pattern area for forming additional patterns in a rim of the panel pattern area. In addition, a TFT glass substrate and the manufacturing thereof are also disclosed. By arranging the additional patterns in the rim of the panel patterns, the microstructures in the rim of the panel patterns are substantially the same with that in the middle of the panel patterns.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 17, 2014
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO
    Inventors: Pei Lin, Hua Zheng, Liangdong Wu, Shangpan Chen, Long Pan, Pan Gao, Mingwen Lin, Shyh-Feng Chen
  • Publication number: 20140103481
    Abstract: A semiconductor substrate according to the present invention includes: a substrate; an electrode array which is provided on the surface on one side in a thickness direction of the substrate and in which a plurality of electrodes is two-dimensionally arranged in a plan view; and a resin layer which is provided on the surface on one side and seals peripheries of the plurality of electrodes. The plurality of electrodes protrudes by greater than or equal to 5% of its own height on the resin layer and is capable of being accommodated in the resin layer by being compressed in the thickness direction.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 17, 2014
    Applicant: OLYMPUS CORPORATION
    Inventors: Shugo Ishizuka, Yuichi Gomi, Yoshiaki Takemoto
  • Patent number: 8686526
    Abstract: The invention is directed to providing a semiconductor device receiving a blue-violet laser, of which the reliability and yield are enhanced. A device element converting a blue-violet laser into an electric signal is formed on a front surface of a semiconductor substrate. An optically transparent substrate is attached to the front surface of the semiconductor substrate with an adhesive layer being interposed therebetween. The adhesive layer contains transparent silicone. Since the front surface of the device element is covered by the optically transparent substrate, foreign substances are prevented from adhering to the front surface of the device element. Furthermore, the adhesive layer is covered by the optically transparent substrate. This prevents the adhesive layer from being exposed to outside air, thereby preventing the degradation of the adhesive layer 6 due to a blue-violet laser.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Katsuhiko Kitagawa, Hiroyuki Shinogi, Shinzo Ishibe, Hiroshi Yamada
  • Patent number: 8685858
    Abstract: Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Augustin J. Hong, Woo-Shik Jung, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana
  • Patent number: 8682116
    Abstract: One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: March 25, 2014
    Assignee: Infineon Technologies AG
    Inventor: Thomas Schulz
  • Patent number: 8637951
    Abstract: A semiconductor light receiving element comprises: a substrate, a semiconductor layer of a first conductivity type formed on the substrate, a non-doped semiconductor light absorbing layer formed on the semiconductor layer of the first conductivity type, a semiconductor layer of a second conductivity type formed on the non-doped semiconductor light absorbing layer, and an electro-conductive layer formed on the semiconductor layer of the second conductivity type. A plurality of openings, periodically arrayed, are formed in a laminated body composed of the electro-conductive layer, the semiconductor layer of the second conductivity type, and the non-doped semiconductor light absorbing layer. The widths of the openings are less than or equal to the wavelength of incident light, and the openings pass through the electro-conductive layer and the semiconductor layer of the second conductivity type to reach the non-doped semiconductor light absorbing layer.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: January 28, 2014
    Assignee: NEC Corporation
    Inventors: Daisuke Okamoto, Junichi Fujikata, Kenichi Nishi
  • Patent number: 8633513
    Abstract: Structures and method for reducing junction leakage in semiconductor devices. The die can include a substrate having a cut edge, a first region of first conductivity type within the substrate and a region of a second conductivity type within the substrate and in contact with the first region forming a junction. At least one semiconductor device is on the substrate. A second region of the first conductivity type is between the plurality of semiconductor devices and the cut edge within the region of the second conductivity type, and extending to the junction. The second region of the first conductivity type can isolate the at least one semiconductor device from leakage pathways created by saw damage at the junction along the cut edge.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: January 21, 2014
    Assignee: Aptina Imaging Corporation
    Inventors: Daniel Doyle, Jeffrey Gleason
  • Publication number: 20140017839
    Abstract: An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, the optoelectronic device includes a first optoelectronic material that is inhomogeneously strained. A first charge carrier collector and a second charge carrier collector are each in electrical communication with the first optoelectronic material and are adapted to collect charge carriers from the first optoelectronic material. In another embodiment, a method of photocatalyzing a reaction includes using a strained optoelectronic material.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 16, 2014
    Applicant: Peking University
    Inventors: Ju Li, Xiaofeng Qian, Ji Feng
  • Publication number: 20140001592
    Abstract: A semiconductor light-receiving element includes: a light-receiving portion that is provided on a semi-insulating substrate and has a mesa shape in which semiconductor layers are laminated; a lamination structure of insulating films that is provided on a part of a side face of the light-receiving portion and has a structure in which a first insulating film comprised of a silicon nitride film, a second insulating film comprised of a silicon oxynitride film and a third insulating film comprised of a silicon nitride film are laminated in contact with each other; and a resin film that is provided adjacent to the light-receiving portion, the resin film being sandwiched in or between any of the first insulating film, the second insulating film and the third insulating film.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 2, 2014
    Inventors: Ryuji YAMABI, Yoshifumi NISHIMOTO
  • Patent number: 8610170
    Abstract: An array structure solves issues that exist in conventional compound semiconductor photodiode arrays, such as large cross talk, large surface leaks, large stray capacitance, narrow detection wavelength bands, and bad manufacturing yield, simultaneously. A photodiode array has, laminated upon a semiconductor substrate, a buffer layer (8) with a broad forbidden band width, an I-type (low concentration photosensitive layer (2) with a narrow forbidden band width, and an n-type semiconductor window layer (3) with a broad forbidden band width, wherein photodiode elements are electrically separated from adjacent elements, by doping the periphery of the p-type impurity, and the detection wavelength band is expanded, by making the n-type window layer (3) on the photosensitive layer (2) a thinner layer with crystal growth.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 17, 2013
    Assignee: Irspec Corporation
    Inventors: Katsuhiko Nishida, Mutsuo Ogura
  • Patent number: 8604580
    Abstract: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: December 10, 2013
    Assignee: President and Fellows of Harvard College
    Inventors: Eric Mazur, James Edward Carey
  • Publication number: 20130320358
    Abstract: A semiconductor device is manufactured by forming at least one epitaxial structure over a substrate. A portion of the substrate is cut and lifted to expose a partial surface of the epitaxial structure. A first electrode is then formed on the exposed partial surface to result in a vertical semiconductor device.
    Type: Application
    Filed: July 2, 2012
    Publication date: December 5, 2013
    Applicant: PHOSTEK, INC.
    Inventor: Yuan-Hsiao CHANG
  • Publication number: 20130299934
    Abstract: A pixel and pixel array for use in an image sensor are provided. The image sensor includes floating sensing nodes symmetrically arranged with respect to a photodiode in each pixel.
    Type: Application
    Filed: March 8, 2013
    Publication date: November 14, 2013
    Inventors: Min-seok OH, Eun-sub SHIM, Jung-chak AHN, Moo-sup LIM, Sung-ho CHOI
  • Patent number: 8581313
    Abstract: There is employed a lamination structure of semiconductor substrate in which light receiving part having a photoelectric converting function is formed in an inner portion, and insulating films and wirings. There are provided a wiring layer formed above semiconductor substrate and having a concave portion formed in a place corresponding to a portion disposed above light receiving part, second insulating film having a higher refractive index than insulating films and covering a side surface of the wiring layer facing the concave portion, third insulating film having a lower refractive index than second insulating film and covering the side surface of second insulating film, and fourth insulating film having a higher refractive index than third insulating film and covering the side surface of third insulating film.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Motonari Katsuno, Masayuki Takase, Tetsuya Nakamura
  • Patent number: 8569853
    Abstract: A semiconductor light-receiving device includes a semiconductor light-receiving element that has a first electrode and a second electrode, a first wiring coupled to the first electrode, and a second wiring coupled to the second electrode, a width of the second wiring being smaller than a width of the first wiring.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: October 29, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Yuji Koyama
  • Patent number: 8564036
    Abstract: In a photodetector 1, a low-resistance Si substrate 3, an insulating layer 4, a high-resistance Si substrate 5, and an Si photodiode 20 construct a hermetically sealed package for an InGaAs photodiode 30 placed within a recess 6, while an electric passage part 8 of the low-resistance Si substrate 3 and a wiring film 15 achieve electric wiring for the Si photodiode 20 and InGaAs photodiode 30. While a p-type region 22 of the Si photodiode 20 is disposed in a part on the rear face 21b side of an Si substrate 21, a p-type region 32 of the InGaAs photodiode 30 is disposed in a part on the front face 31a side of an InGaAs substrate 31.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: October 22, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Yoshihisa Warashina, Masatoshi Ishihara, Tomofumi Suzuki
  • Patent number: 8541857
    Abstract: Backside illumination CMOS image sensors having convex light-receiving faces and methods of manufacturing the same. A backside illumination CMOS image sensor includes a metal layer, an insulating layer and a photodiode. The insulating layer is on the metal layer. The photodiode is on the insulating layer, and a top face of the photodiode, which receives light, is curved. A method of manufacturing a backside illumination CMOS image sensor including a photodiode having a convex surface includes forming an island smaller than the photodiode on a portion of a light-receiving face of the photodiode, and annealing the island to form the photodiode having the convex light-receiving face.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: September 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-chak Ahn, Kyung-ho Lee
  • Publication number: 20130221474
    Abstract: According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region.
    Type: Application
    Filed: January 9, 2013
    Publication date: August 29, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kabushiki Kaisha Toshiba
  • Publication number: 20130168658
    Abstract: An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between 2.5 to 7 microns; a plurality of first terminals spaced apart and coupled to the light emitting region peripherally on a first side, each first terminal of the plurality of first terminals having a height between about 0.5 to 2 microns; and one second terminal coupled centrally to a mesa region of the light emitting region on the first side, the second terminal having a height between 1 to 8 microns.
    Type: Application
    Filed: February 22, 2013
    Publication date: July 4, 2013
    Applicant: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.
    Inventor: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.
  • Patent number: 8476725
    Abstract: The present invention is a front-side contact, back-side illuminated (FSC-BSL) photodiode arrays and front-side illuminated, back-side contact (FSL-BSC) photodiode arrays having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform, as well as high, photocurrent density owing to presence of a large continuous homogeneous, heavily doped layer; and back to front intrachip connections via the homogenous, heavily doped layers on the front and back sides of the substrate.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 2, 2013
    Assignee: OSI Optoelectronics, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Publication number: 20130162330
    Abstract: Embodiments relate to photo cell devices. In one embodiment, a trench-based photo cells provides very fast capture of photo-generated charge carriers, particularly when compared with conventional approaches, as the trenches of the photo cells create depleted regions deep within the bulk of the substrate that avoid the time-consuming diffusion of carriers.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Inventor: Thoralf Kautzsch
  • Patent number: 8471353
    Abstract: A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D1 of a portion covering the side wall of the mesa is equal to or greater than 850 nm.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoaki Koi, Isao Watanabe, Takashi Matsumoto