Matrix Or Array (e.g., Single Line Arrays) Patents (Class 257/443)
  • Patent number: 11276722
    Abstract: A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mineo Shimotsusa
  • Patent number: 11255983
    Abstract: The semiconductor device comprises a substrate of semiconductor material having a main surface, an integrated circuit in the substrate, a photodetector element or array of photodetector elements arranged at or above the main surface, and at least one nanomaterial film arranged above the main surface. At least part of the nanomaterial film has a scintillating property. The method of production includes the use of a solvent to apply the nanomaterial film, in particular by inject printing, by silk-screen printing, by spin coating or by spray coating.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: February 22, 2022
    Assignee: AMS INTERNATIONAL AG
    Inventors: Jens Hofrichter, Guy Meynants, Josef Pertl, Thomas Troxler
  • Patent number: 11251220
    Abstract: A monolithic multi-metallic thermal expansion stabilizer (MTES) has a coefficient of thermal expansion (CTE) differential between a first surface and a second surface, and a transition region extending between for mitigating the CTE differential.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: February 15, 2022
    Assignee: Raytheon Company
    Inventor: Detlef Kramer
  • Patent number: 11226237
    Abstract: A temperature sensor module with an integrated lid structure for spurious IR-cancellation is disclosed. An improved temperature sensor module that allows detection of a maximum of the relevant IR-radiation from an object's surface of interest as well as generation of additional information about parasitic or spurious IR-radiation that distort the relevant thermal signal in order to enable a cancellation of interfering thermal signal portions is presented. The temperature sensor module includes a temperature sensing element, a sensor-interface control integrated circuit, whereas the temperature sensing element is coupled to the sensor-interface control IC, and a lid structure and a sensor packaging both defining a field of view of the temperature sensor module, wherein the lid structure is formed by a substrate comprising a second integrated temperature sensor connected to the sensor-interface control IC or an external connected processing unit.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: January 18, 2022
    Assignee: Integrated Device Technology, Inc.
    Inventors: Raik Richter, Marko Mailand
  • Patent number: 11217705
    Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: January 4, 2022
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
  • Patent number: 11209363
    Abstract: An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 28, 2021
    Assignee: Quantum-Si Incorporated
    Inventors: Jonathan M. Rothberg, Keith G. Fife, David M. Boisvert
  • Patent number: 11195870
    Abstract: A first conductive portion includes a first pad surrounded by a first insulator film in a plane perpendicular to a first direction, and a first via connected to the first pad so that the first via is positioned between the first pad and a first semiconductor layer in the first direction. A second conductive portion includes a second pad surrounded by a second insulator film in a plane perpendicular to the first direction, and a second via connected to the second pad so that the second via is positioned between the second pad and a second semiconductor layer in the first direction. The first and the second conductive portions are different in dimension.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 7, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tsutomu Tange, Takumi Ogino, Hiroaki Kobayashi
  • Patent number: 11183527
    Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gang Zhang, Shi Li Quan, Hyung-yong Kim, Seug-gab Park, In-gyu Baek, Kyung-rae Byun, Jin-yong Choi
  • Patent number: 11171263
    Abstract: The present disclosure provides a quantum dot and a manufacturing method for the same, and a luminescent material, a light-emitting element and a display device applying the quantum dot. The quantum dot includes a nano-crystal and a ligand. The nano-crystal is at least one selected from the group consisting of a XII-XV group compound semiconductor nano-crystal, a XII-XVI group compound semiconductor nano-crystal, a XIII-XV group compound semiconductor nano-crystal and a XIII-XVI group compound semiconductor nano-crystal. The ligand is disposed on a surface of the nano-crystal. The ligand contains 15%-70% of a fatty acid compound, 1%-35% of a phosphine compound, >0%-55% of a thiol compound, and 0%-10% of another ligand substance.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 9, 2021
    Assignee: CHIMEI CORPORATION
    Inventor: Keng-Chu Lin
  • Patent number: 11164902
    Abstract: A device including a semiconductive substrate having opposite first and second surfaces, a light-sensitive element in the semiconductive substrate, an isolation structure extending at least from the second surface of the semiconductive substrate to within the semiconductive substrate, and a color filter over the second surface of the semiconductive substrate. The isolation structure includes a dielectric fill and a first high-k dielectric layer wrapping around the dielectric fill.
    Type: Grant
    Filed: July 11, 2020
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang
  • Patent number: 11127771
    Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Yusuke Tanaka, Toshifumi Wakano, Keiji Tatani, Takashi Nagano, Hayato Iwamoto, Keiichi Nakazawa, Tomoyuki Hirano, Shinpei Yamaguchi, Shunsuke Maruyama
  • Patent number: 11114424
    Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes: a base substrate; a display function layer located on the base substrate, a first groove arranged in the first surface, and a first connection sub-line located in the first groove and covering a bottom and each side wall of the first groove, the first connection sub-line being connected to a signal input terminal; an integrated circuit located on a second surface, a second groove arranged in the second surface, and a second connection sub-line located in the second groove, the second connection sub-line being connected to the first connection sub-line and a signal output terminal of the integrated circuit.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 7, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dongni Liu, Minghua Xuan
  • Patent number: 11094725
    Abstract: Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 17, 2021
    Assignee: SONY CORPORATION
    Inventors: Yusuke Tanaka, Toshifumi Wakano, Keiji Tatani, Takashi Nagano, Hayato Iwamoto, Keiichi Nakazawa, Tomoyuki Hirano, Shinpei Yamaguchi, Shunsuke Maruyama
  • Patent number: 11054533
    Abstract: An SiPM sensor chip includes pixels consisting of microcells Z, each pixel being associated with an xy position x1, x2, x3, . . . , xN or y1, y2, y3, . . . yM. A plurality of pixels form a block, and the microcells are connected to output channels for a linear coding.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 6, 2021
    Assignee: FORSCHUNGSZENTRUM JUELICH GMBH
    Inventors: Christoph Lerche, Arne Berneking, Nadim Joni Shah
  • Patent number: 11048025
    Abstract: The present disclosure discloses an anti-reflection coating and a method of forming the same. According to one embodiment of the present disclosure, the anti-reflection coating includes a first layer positioned on a substrate to be spaced apart from the substrate by a first distance and a second layer positioned on the first layer to be spaced apart from the first layer by a second distance. In this case, the first and second layers are a metamaterial forming a structural double layer and are realized as an anomalous dispersive medium that does not absorb incident light. The structural double layer may realize spatiotemporal dispersion that varies depending on an incidence angle using the nonlocality of the electromagnetic wave reaction of incident light.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: June 29, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Q Han Park, Ku Im, Ji Hun Kang
  • Patent number: 10971534
    Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Cheng, Shyh-Fann Ting, Yen-Ting Chiang, Yeur-Luen Tu, Min-Ying Tsai
  • Patent number: 10943940
    Abstract: Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Chuang Wu, Jhy-Jyi Sze, Yu-Jen Wang, Yen-Chang Chu, Shyh-Fann Ting, Ching-Chun Wang
  • Patent number: 10854647
    Abstract: In some embodiments, the present disclosure relates to an image sensor, including a first photodiode and a second photodiode disposed in a semiconductor substrate. A floating diffusion node is disposed along a frontside of the semiconductor substrate and between the first and second photodiodes. A partial backside deep trench isolation (BDTI) structure is disposed within the semiconductor substrate and between the first and second photodiodes. The partial BDTI extends from a backside of the semiconductor substrate and is spaced from the floating diffusion node. A full BDTI structure extends from the backside of the semiconductor substrate to the frontside of the semiconductor substrate.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yimin Huang
  • Patent number: 10840290
    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Keiji Tatani, Hajime Inoue, Ryuichi Kanamura
  • Patent number: 10840277
    Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 17, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinjiro Kameda, Eiichi Funatsu
  • Patent number: 10818732
    Abstract: A photosensitive sensor and a method of manufacturing the photosensitive sensor are disclosed. The photosensitive sensor includes a thin film transistor and a photosensitive element on a substrate, wherein the photosensitive element includes a first electrode, a second electrode, and a photosensitive layer between the first electrode and the second electrode. The second electrode is connected to a drain electrode of the thin film transistor. An orthographic projection of an active layer of the thin film transistor on the substrate is within an orthographic projection of the second electrode on the substrate. The second electrode includes at least two stacked conductive layers, at least one of the at least two stacked conductive layers being a light shielding metal layer.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 27, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shipei Li, Wusheng Li, Qi Yao, Dongsheng Li, Fang He, Huili Wu, Renquan Gu, Sheng Xu, Wei He, Dongsheng Yin, Ying Zhao
  • Patent number: 10810710
    Abstract: An image acquisition unit acquires first and second radiographic images acquired by irradiating a first radiation detector and a second radiation detector which overlaps the first radiation detector so as to deviate from the first radiation detector by a half pixel with radiation which has been emitted from a radiation source and transmitted through an object. A corresponding positional relationship acquisition unit acquires a corresponding positional relationship between the position of pixels of the first radiographic image and the position of pixels of the second radiographic image. A resolution enhancement unit estimates a pixel value corresponding to a position between the pixels of the first radiographic image, on the basis of the corresponding positional relationship, a pixel value of the first radiographic image, and a pixel value of the second radiographic image, and generates a processed radiographic image having a higher resolution than the first and second radiographic images.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: October 20, 2020
    Assignee: FUJIFILM CORPORATION
    Inventor: Takahiro Kawamura
  • Patent number: 10805563
    Abstract: According to an aspect of the present invention, provided is a solid state imaging device including a plurality of pixels, and each of the pixels has a charge accumulation region of a first conductivity type that accumulates signal charges corresponding to an incident light, a drain region of the first conductivity type to which a predetermined voltage is applied, a drain gate located between the drain region and the charge accumulation region in a planar view, and a semiconductor region of the first conductivity type connected to the charge accumulation region and the drain region.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 13, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hajime Ikeda, Masahiro Kobayashi, Hiroshi Sekine, Yusuke Onuki
  • Patent number: 10778926
    Abstract: Example embodiments relate to an image sensor and a method for read-out of pixel signal. One embodiment includes an image sensor. The image sensor includes an array of pixels for detecting light incident on the pixel. The image sensor also includes an in-pixel correlated double sampling (CDS) circuitry. The image sensor also includes a column line that extends along and is associated with a column of pixels in the array of pixels. The column line is configured to selectively receive a pixel signal from a pixel in the column. Further, the image sensor includes a voltage-drop correction line that extends along and is associated with the column of pixels. The voltage-drop correction line is configured to provide a correction voltage signal to a pixel in the column such that corrects for voltage drop of the pixel signal in read-out through the column line.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: September 15, 2020
    Assignee: IMEC VZW
    Inventors: Annachiara Spagnolo, Jonathan Borremans
  • Patent number: 10778141
    Abstract: A method of fabricating a photovoltaic cell having a microinverter is provided. The method may include fabricating a monolithic microinverter layer through epitaxy and operably connecting the at least one microinverter layer to at least one photovoltaic cell formed on a photovoltaic layer. A photovoltaic device is also provided. The device may have a photovoltaic layer comprising at least one photovoltaic cell and a microinverter layer comprising at least one microinverter, wherein the microinverter layer was fabricated through epitaxy, the at least one microinverter is configured to be operably connected to at least one photovoltaic cell.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 15, 2020
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Kyusang Lee
  • Patent number: 10763294
    Abstract: An image sensor chip may include a first sub-chip, a second sub-chip on the first sub-chip, and an interconnector between the first and second sub-chips. The first sub-chip may include a first substrate, a bottom electrode on a first region of the first substrate, and a first capacitor on the bottom electrode. The first capacitor may include a plurality of first electrodes vertically extending from a top surface of the bottom electrode, a second electrode on the first electrodes, and a first dielectric layer between the second electrode and the first electrodes. The second sub-chip may include a pixel array configured to convert incident light into an electrical signal. The pixel array may be electrically connected through the interconnector to the first capacitor.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaekyu Lee, Sung In Kim, Byung-Joon Baek
  • Patent number: 10748954
    Abstract: A solid-state image pickup device is provided which can inhibit degradation of image quality which may occur when a global electronic shutter operation is performed. A gate drive line for a first transistor of gate drive lines for pixel transistors is positioned in proximity to a converting unit.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 18, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masahiro Kobayashi, Yusuke Onuki, Toru Koizumi
  • Patent number: 10727260
    Abstract: An image sensor packaging method, an image sensor package and a lens module are disclosed. In the image sensor packaging method, plural image sensor dies are formed within a molded layer, resulting in a package with a significantly reduced thickness which is favorable to the slimming of the package. The packaging method does not involve any wire bonding process. Instead, metal pads are led out through a thin metal film formed in non-photosensitive areas on the same side of micro lens surfaces of the image sensor dies. This approach has a less adverse impact on micro lens surfaces and, compared to the wire bonding process, allows a smaller spacing from metal pads to the micro lens surfaces with respect to a direction parallel to the micro lens surfaces, which enables more compact image sensor dies usable in a lens module for an optimized spatial design and ease of miniaturization.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: July 28, 2020
    Assignee: Inno-Pach Technology Pte Ltd.
    Inventors: Liping Chang, Deze Yu, Wanning Zhang
  • Patent number: 10707358
    Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Juan Boon Tan, Kiok Boone Elgin Quek, Khee Yong Lim, Chim Seng Seet, Rajesh Nair
  • Patent number: 10692919
    Abstract: The present technology relates to a solid-state imaging element, an imaging device, and an electronic device that can improve transfer efficiency of a charge accumulation unit (MEM) and can increase the number of saturation electrons Qs. In a case where a charge voltage conversion unit (FD) is connected to a center of a charge accumulation unit (MEM) in each pixel and pixels are arrayed in an array, a column in which photoelectric conversion units (PD) are arrayed and a column including charge voltage conversion units (FD) and pixel transistors are arrayed in parallel. The present technology can be applied to a CMOS image sensor.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: June 23, 2020
    Assignee: SONY CORPORATION
    Inventor: Ryoto Yoshita
  • Patent number: 10672818
    Abstract: An imaging device comprises a sensor substrate including a pixel array that includes at least a first pixel. The first pixel includes an avalanche photodiode including a light receiving region, a cathode, and an anode. The first pixel includes a wiring layer electrically connected to the cathode and arranged in the sensor substrate such that the wiring layer is in a path of incident light that exits the light receiving region.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 2, 2020
    Assignee: SONY CORPORATION
    Inventors: Akira Tanaka, Yusuke Otake, Toshifumi Wakano
  • Patent number: 10666020
    Abstract: An emitter array may comprise a plurality of vertical-emitting devices. The plurality of vertical-emitting devices may be in a two-dimensional pattern of vertical-emitting devices. The emitter array may further comprise a plurality of electrical contacts on a surface of the emitter array. Each of the plurality of electrical contacts may be co-located with and electrically connected to a corresponding vertical-emitting device of the plurality of vertical-emitting devices. The plurality of electrical contacts may provide mechanical support over the plurality of vertical-emitting devices. The plurality of electrical contacts may extend to approximately a same height. A subset of the plurality of vertical-emitting devices may be powered via a corresponding subset of the plurality of electrical contacts.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 26, 2020
    Assignee: Lumentum Operations LLC
    Inventor: Albert Yuen
  • Patent number: 10630876
    Abstract: An array imaging module includes at least two optical lenses and a molded photosensitive assembly, wherein the molded photosensitive assembly includes at least two photosensitive units, a circuit board that electrically couples to the photosensitive units, and a molded base having at least two optical windows. The molded base is integrally coupled at the circuit board at a peripheral portion thereof, wherein the photosensitive units are aligned with the optical windows respectively. The optical lenses are located along two photosensitive paths of the photosensitive units respectively, such that each of the optical windows forms a light channel through the corresponding photosensitive unit and the corresponding optical lens.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 21, 2020
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Takehiko Tanaka, Nan Guo, Zhen Huang, Duanliang Cheng, Liang Ding, Feifan Chen, Heng Jiang
  • Patent number: 10622394
    Abstract: The image sensing device includes a semiconductor substrate, an interconnection layer, a radiation-sensing region and an isolation structure. The semiconductor substrate has a front surface and a back surface. The interconnection layer is disposed over the front surface of the semiconductor substrate. The radiation-sensing region is disposed in the semiconductor substrate. The isolation structure is disposed on the back surface of the semiconductor substrate. The isolation structure includes a trench and an etch stop layer. The trench extends from the back surface of the semiconductor substrate. The etch stop layer is disposed along the trench. An etch selectivity of a silicon oxide film to the etch stop layer is greater than a predetermined value.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chuang Wu, Ming-Tsong Wang, Feng-Chi Hung, Ching-Chun Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10608027
    Abstract: A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip including image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip in a stack. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 31, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Yi-Ann Chen, Abid Husain, Hideki Takeuchi
  • Patent number: 10608043
    Abstract: A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 31, 2020
    Assignee: ATOMERA INCORPORATION
    Inventors: Yi-Ann Chen, Abid Husain, Hideki Takeuchi
  • Patent number: 10595798
    Abstract: A detection apparatus according to an embodiment includes first detectors, a first electrode, second detectors and a second electrode. The first detectors detect a photon. The first electrode is electrically connected to each of the first detectors. The second detectors detect a photon. The second electrode is electrically connected to each of the second detectors. The number of first detectors is less than the number of second detectors.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 24, 2020
    Assignee: Canon Medical Systems Corporation
    Inventors: Go Kawata, Keita Sasaki, Rei Hasegawa
  • Patent number: 10546886
    Abstract: The invention relates to a photodetection device comprising a substrate and a diodes network, the substrate comprising an absorption layer and each diode comprising a collection region with a first type of doping in the absorption layer. The device comprises a conduction mesh under the surface of the substrate, comprising at least one conduction channel inserted between the collection regions of two adjacent diodes, the at least one conduction channel having a second doping type opposite the first type and a higher doping density than the absorption layer. The doping density of the at least one conduction channel is derived from metal diffusion in the absorption layer from a metal mesh present on the substrate surface. The absorption layer has the first doping type. The invention also relates to a method of making such a device.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: January 28, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Johan Rothman
  • Patent number: 10546890
    Abstract: Some embodiments relate to a device array including a plurality of devices arranged in a semiconductor substrate. A protection ring circumscribes an outer perimeter of the device array. The protection ring includes a first ring neighboring the device array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction. The first ring has a first width, the second ring has a second width, and the third ring has a third width. At least two of the first width, the second width, and the third width are different from one another.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng
  • Patent number: 10529768
    Abstract: A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement. At least one of the transistors may include a first semiconductor layer and a superlattice on the first semiconductor layer including a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The transistor(s) may also include a second semiconductor layer on the superlattice, spaced apart source and drain regions in the second semiconductor layer defining a channel therebetween, and a gate comprising a gate insulating layer on the second semiconductor layer and a gate electrode on the gate insulating layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 7, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Yi-Ann Chen, Abid Husain, Hideki Takeuchi
  • Patent number: 10514450
    Abstract: A beamformer for performing analog beamforming of ultrasound signals received from a plurality of transducer devices, the beamformer includes: first analog devices configured to output first ultrasound signals by delaying or transmitting the ultrasound signals based on a predetermined delay time; second analog devices configured to store first sub-ultrasound signals from among the first ultrasound signals, and to output the first sub-ultrasound signals depending on whether the first sub-ultrasound signals are repeatedly used; and a processor configured to control the delay time, and to perform the analog beamforming by summing the first ultrasound signals which correspond to the plurality of transducer devices and which are outputted depending on the delay time.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: December 24, 2019
    Assignees: SAMSUNG MEDISON CO., LTD., SOGANG UNIVERSITY RESEARCH FOUNDATION
    Inventors: Woo-youl Lee, Tae-kyong Song, Hyun-gil Kang, Ji-won Park
  • Patent number: 10497737
    Abstract: A pixel element for an imaging sensor comprises a semiconductor substrate, a radiation-sensitive element configured to generate electric charges in response to incident radiation, a charge accumulation region provided in the semiconductor substrate configured to accumulate at least a portion of the electric charges, and an electrode arranged on the semiconductor substrate adjacent to the charge accumulation region. The electrode is electrically insulated from the semiconductor substrate such as to form an inversion region in the semiconductor substrate that connects to the charge accumulation region when a voltage is applied to said electrode.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 3, 2019
    Assignee: Caeleste CVBA
    Inventor: Bart Dierickx
  • Patent number: 10418398
    Abstract: A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit. The solid-state image pickup apparatus further includes a light shielding member including a first part and a second part, wherein the first part is disposed over the charge storage unit and at least over the first gate electrode or the second gate electrode, and the second part is disposed between the first gate electrode and the second gate electrode such that the second part extends from the first part toward a surface of the semiconductor substrate.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 17, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masahiro Kobayashi, Yuichiro Yamashita, Yusuke Onuki
  • Patent number: 10403663
    Abstract: A solid-state imaging device includes a plurality of pixels each of which includes a photoelectric conversion unit that generates charges by photoelectrically converting light, and a transistor that reads a pixel signal of a level corresponding to the charges generated in the photoelectric conversion unit. A phase difference pixel which is at least a part of the plurality of pixels is configured in such a manner that the photoelectric conversion unit is divided into a plurality of photoelectric conversion units and an insulated light shielding film is embedded in a region for separating the plurality of photoelectric conversion units, which are divided, from each other.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 3, 2019
    Assignee: Sony Corporation
    Inventor: Hirotoshi Nomura
  • Patent number: 10396060
    Abstract: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 27, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura
  • Patent number: 10373993
    Abstract: A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit. The solid-state image pickup apparatus further includes a light shielding member including a first part and a second part, wherein the first part is disposed over the charge storage unit and at least over the first gate electrode or the second gate electrode, and the second part is disposed between the first gate electrode and the second gate electrode such that the second part extends from the first part toward a surface of the semiconductor substrate.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: August 6, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masahiro Kobayashi, Yuichiro Yamashita, Yusuke Onuki
  • Patent number: 10368417
    Abstract: The present invention relates to a display device and, particularly, to a display device using a semiconductor light-emitting device. The display device according to the present invention comprises a semiconductor light-emitting device, and the semiconductor light-emitting device comprises: a first conductive semiconductor layer; a second conductive semiconductor layer having a lateral surface, and overlapped with the first conductive semiconductor layer; a first conductive electrode electrically connected to the first conductive semiconductor layer; and a second conductive electrode electrically connected to the second conductive semiconductor layer, wherein the second conductive semiconductor layer has an inclined part inclined with respect to the lateral surface, and the second conductive electrode is formed so as to cover the inclined part.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: July 30, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Seonock Kim, Hwankuk Yuh
  • Patent number: 10366199
    Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: July 30, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jagadish Hosmani, Mohammed Yousuff Shariff, Venugopal Sanaka, Huibo Hou
  • Patent number: 10332932
    Abstract: The present disclosure relates to a solid-state image pickup device, a manufacturing method, and an electronic apparatus, which can obtain high charge transfer efficiency from a photoelectric conversion unit to a floating diffusion layer. The floating diffusion layer is arranged in a rectangular shape so as to surround a gate electrode of a vertical transistor whose groove portion is rectangular. A reset drain is formed so as to be adjacent to the floating diffusion layer through a reset gate. A potential of the floating diffusion layer is reset to the same potential as that of the reset drain by applying a predetermined voltage to the reset gate. It is possible to apply the present disclosure to, for example, a CMOS solid-state image pickup device used in an image pickup device such as a camera.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 25, 2019
    Assignee: Sony Corporation
    Inventors: Keisuke Hatano, Hideaki Togashi
  • Patent number: 10283547
    Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: U-Ting Chen, Shu-Ting Tsai, Cheng-Ying Ho, Tzu-Hsuan Hsu, Shih Pei Chou