RECESSED CHANNEL ACCESS TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF

Abstract

A recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth. A buried gate electrode is disposed at a lower portion of the trench. A gate oxide layer is formed between the buried gate electrode and the semiconductor substrate. A drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed. The source doping region has a junction depth that is deeper than that of the drain doping region. An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devices. More particularly, the present invention relates to a recessed channel access transistor (RCAT) device for high-density dynamic random access memory (DRAM) applications.

2. Description of the Prior Art

As the size of semiconductor devices shrinks, the gate channel length decreases correspondingly, and short channel effect (SCE) and junction leakage current become very serious problems. Recessed channel access transistor devices (or RCAT devices in short) have been developed to suppressing the short channel effect by physically increasing the gate channel length without an increase in a lateral area of a gate electrode.

Typically, an RCAT transistor has a gate oxide layer formed on sidewalls and the bottom surface of a recess etched into a substrate, where a conductive substance fills the recess. Contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate, the RCAT transistor has a U-shaped channel along the surface of the recess. Therefore, the integration of the recessed-gate transistor can be increased.

However, in a conventional RCAT device, when a drain voltage (Vd) is applied to a capacitor that is electrically connected to an NMOS transistor, agate induced drain leakage (GIDL) problem may occur. The GIDL adversely affects the refresh or data retention characteristic of the DRAM device.

SUMMARY OF THE INVENTION

It is therefore one objective of the present invention to provide an improved recessed channel access transistor device to solve the above-mentioned prior art problems or shortcomings.

According to one embodiment of the invention, a recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth. A buried gate electrode is disposed at a lower portion of the trench. Agate oxide layer is formed between the buried gate electrode and the semiconductor substrate. A drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed. The source doping region has a junction depth that is deeper than that of the drain doping region. An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region.

According to one aspect of the invention, a method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench extending from a main surface of the semiconductor substrate to a predetermined depth is prepared. A gate oxide layer is formed on interior surface of the trench. A buried gate electrode is formed at a lower portion of the trench. The capping the buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the main surface of the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench, wherein a portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. Thereafter, an ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region in the semiconductor substrate. The source doping region has a junction depth that is deeper than that of the drain doping region.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

FIGS. 1-7 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a recessed channel access transistor (RCAT) device in accordance with one embodiment of the present invention;

FIGS. 8-10 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a RCAT device in accordance with another embodiment of the present invention; and

FIGS. 11-13 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a RCAT device in accordance with yet another embodiment of the present invention.

It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which the embodiments may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the described embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the included embodiments are defined by the appended claims.

With regard to the fabrication of transistors and integrated circuits, the term “major surface” refers to that surface of the semiconductor layer in and about which a plurality of transistors are fabricated, e.g., in a planar process. As used herein, the term “vertical” means substantially orthogonal with respect to the major surface. Typically, the major surface is along a <100> plane of a monocrystalline silicon layer on which the field-effect transistor devices are fabricated.

FIGS. 1-7 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a recessed channel access transistor (RCAT) device in accordance with one embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 10 is provided. The semiconductor substrate 10 may be a silicon substrate, silicon germanium, gallium arsenic or other semiconductor materials. For example, the semiconductor substrate 10 may be a P type silicon substrate. A trench 12 is formed in the semiconductor substrate 10. The trench 12 has a depth d from the main surface 10a of the semiconductor substrate 10. The trench 12 may have a substantially vertical sidewall surface 12a and a bottom surface 12b connected to the sidewall surface 12a.

As shown in FIG. 2, an oxidation process may be performed to form a gate oxide layer 14 on the interior surface of the trench 12. A gate electrode layer 16 is then deposited on the gate oxide layer 14 and fills the trench 12. The gate electrode layer 16 may comprise polysilicon, for example.

As shown in FIG. 3, an etch back process may be performed to recess the gate electrode layer 16 such that the top surface of the recessed gate electrode layer 16 is lower than the main surface 10a of the semiconductor substrate 10. Subsequently, a dielectric layer 18 such as a silicon oxide layer is deposited over the semiconductor substrate 10 in a blanket manner. The dielectric layer 18 fills the trench 12, thereby forming a buried gate electrode 16a at the lower portion of the trench 12.

As shown in FIG. 4, a planarization process such as a chemical mechanical polishing (CMP) process is carried out to remove excess dielectric layer 18 from the main surface 10a of the semiconductor substrate 10 . At this point, the polished top surface of the dielectric layer 18 is substantially flush with the main surface 10a.

As shown in FIG. 5, a pad layer 22 such as a silicon oxide layer is then deposited in a blanket manner. The pad layer 22 may be a silicon oxide layer. A hard mask layer 24 such as a silicon nitride layer is then deposited on the pad layer 22.

As shown in FIG. 6, a lithographic process and a dry etching process are performed to from a recess 30 in the semiconductor substrate 10 on one single side of the trench 12. At this point, a portion of the dielectric layer 18 is revealed within the recess 30. Within the recess 30, a lower top surface 10b of the semiconductor substrate 10 is formed.

As shown in FIG. 7, the hard mask layer 24 is stripped off, while leaving the pad layer 22 substantially intact. Subsequently, an ion implantation process 40 is performed to implant dopants such as N type dopants into the semiconductor substrate 10 on both sides of the trench 12, that is, the digit side and the cell side in this embodiment, thereby forming a RCAT device 1 with asymmetric drain doping region 42 and source doping region 44.

Due to the recess 30 on the cell side of the RCAT device 1, the PN junction depth 44a of the source doping region 44 on the digit side can be formed deeper than the PN junction depth 42a of the drain doping region 42 on the cell side. An L-shaped channel 50 maybe defined along the sidewall surface 12a on the cell side and along the bottom surface 12b of the trench 12 between the drain doping region 42 and the source doping region 44.

According to the embodiment, preferably, PN junction depth 44a of the source doping region 44 on the digit side may be equal to the depth d of the trench 12. Compared to the prior art RCAT devices, the PN junction depth 42a of the drain doping region 42 on the cell side may be shallower in order to maintain an adequate operation current level when operating the RCAT device 1. A contact (not shown) may be formed on the source doping region 44 to couple to a digit line (not shown).

Structurally speaking, according to the embodiment and briefly referring to FIG. 7, the RCAT device 1 comprises a semiconductor substrate 10 having thereon a trench 12 extending from a main surface 10a of the semiconductor substrate 10 to a predetermined depth d, a buried gate electrode 16a disposed at a lower portion of the trench 12, a gate oxide layer 14 between the buried gate electrode 16a and the semiconductor substrate 10, a drain doping region 42 on a first side (cell side) of the trench in the semiconductor substrate 10, and a source doping region 44 on a second side (digit side) of the trench. The source doping region 44 has a junction depth that is deeper than that of the drain doping region 42. An L-shaped channel 50 is defined along a sidewall surface on the first side and along a bottom surface of the trench 12 between the drain doping region 42 and the source doping region 44.

FIGS. 8-10 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a RCAT device in accordance with another embodiment of the present invention. As shown in FIG. 8, after the formation of the buried gate electrode or word line 16a, similar to the process step as depicted in FIG. 4, a planarization process such as a CMP process is carried out to remove excess dielectric layer 18 from the main surface 10a of the semiconductor substrate 10. At this point, the polished top surface of the dielectric layer 18 is substantially flush with the main surface 10a.

Subsequently, anion implantation process 142 is performed to implant dopants such as N type dopants into the main surface 10a of the semiconductor substrate 10, thereby forming a drain doping region 42 on the cell side and a doping region 43 on the digit side. The junction depth of the drain doping region 42 is substantially equal to the junction depth of the doping region 43.

As shown in FIG. 9, a pad layer 22 is then deposited in a blanket manner. The pad layer 22 may be a silicon oxide layer. A hard mask layer 24 such as a silicon nitride layer is then deposited on the pad layer 22. A lithographic process and a dry etching process are performed to from a recess 30 in the semiconductor substrate 10 on the digit side. At this point, a portion of the dielectric layer 18 is revealed within the recess 30.

Using the hard mask layer 24 as an ion implant mask, an ion implantation process 144 is performed to implant dopants such as N type dopants into the semiconductor substrate 10 on the digit side, thereby forming a RCAT device la with asymmetric drain doping region 42 and source doping region 44.

Due to the recess 30 on the cell side of the RCAT device 1, the PN junction depth 44a of the source doping region 44 on the digit side can be formed deeper than the PN junction depth 42a of the drain doping region 42 on the cell side. A channel 50 is defined along the sidewall surface 12a on the cell side and along the bottom surface 12b of the trench 12 between the drain doping region 42 and the source doping region 44.

According to the embodiment, preferably, PN junction depth 44a of the source doping region 44 on the digit side may be equal to the depth d of the trench 12. Compared to the prior art RCAT devices, the PN junction depth 42a of the drain doping region 42 on the cell side may be shallower in order to maintain an adequate operation current level when operating the RCAT device 1. A contact (not shown) may be formed on the source doping region 44 to couple to a digit line (not shown).

As shown in FIG. 10, after the ion implantation process 144 is complete, the hard mask layer 24 may be removed.

FIGS. 11-13 are schematic, cross-sectional diagrams showing an exemplary method for fabricating a RCAT device in accordance with yet another embodiment of the present invention. As shown in FIG. 11, after the formation of the buried gate electrode or word line 16a, similar to the process step as depicted in FIG. 4, a planarization process such as a CMP process is carried out to remove excess dielectric layer 18 from the main surface 10a of the semiconductor substrate 10 . At this point, the polished top surface of the dielectric layer 18 is substantially flush with the main surface 10a.

Likewise, an ion implantation process 142 is performed to implant dopants such as N type dopants into the main surface 10a of the semiconductor substrate 10, thereby forming a drain doping region 42 on the cell side and a doping region 43 on the digit side. The junction depth of the drain doping region 42 is substantially equal to the junction depth of the doping region 43.

As shown in FIG. 12, a pad layer 22 is then deposited in a blanket manner. The pad layer 22 may be a silicon oxide layer. A hard mask layer (not shown in this figure) such as a silicon nitride layer is then deposited on the pad layer 22. A lithographic process and a dry etching process are performed to from a recess 30 in the semiconductor substrate 10 on the digit side. At this point, a portion of the dielectric layer 18 is revealed within the recess 30. Thereafter, the hard mask layer is stripped off, while leaving the pad layer 22 substantially intact.

As shown in FIG. 13, a doped polysilicon layer (not shown) is then deposited on the semiconductor substrate 10 and fills the recess 30. A lithographic process and a dry etching process are performed to pattern the doped polysilicon layer into a contact element 60 situated directly on the recess 30. A thermal process may be performed to drive the dopants from the contact element 60 into the portion of the semiconductor substrate 10 that is in direct contact with the contact element 60, thereby forming a source doping region 44.

The PN junction depth 44a of the source doping region 44 on the digit side may be equal to the depth d of the trench 12. Compared to the prior art RCAT devices, the PN junction depth 42a of the drain doping region 42 on the cell side may be shallower in order to maintain an adequate operation current level when operating the RCAT device 1c. The contact element 60 formed on the source doping region 44 may be coupled to a digit line (not shown).

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A recessed channel access transistor device, comprising:

a semiconductor substrate having thereon a trench extending from a main surface of the semiconductor substrate to a predetermined depth;

a buried gate electrode disposed at a lower portion of the trench;

a gate oxide layer between the buried gate electrode and the semiconductor substrate;

a drain doping region on a first side of the trench in the semiconductor substrate; and

a source doping region on a second side of the trench, wherein a top surface of the source doping region on the second side of the trench is lower than the main surface of the semiconductor substrate, and wherein the source doping region has a junction depth that is deeper than that of the drain doping region.

2. The recessed channel access transistor device according to claim 1 further comprising a dielectric layer in the trench, wherein the buried gate electrode is capped by the dielectric layer.

3. The recessed channel access transistor device according to claim 2 further comprising a recess on the second side of the trench, wherein a portion of the dielectric layer is revealed within the recess.

4. The recessed channel access transistor device according to claim 3 further comprising a contact element in the recess and in direct contact with the source doping region.

5. The recessed channel access transistor device according to claim 4 wherein the contact element is a doped polysilicon.

6. The recessed channel access transistor device according to claim 1 wherein the junction depth of the source doping region is substantially equal to the predetermined depth of the trench.

7. The recessed channel access transistor device according to claim 1 further comprising an L-shaped channel along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region.

8-10. (canceled)