INTEGRATED CIRCUIT DEVICE WITH A CONNECTOR ACCESS REGION AND METHOD FOR MAKING THEREOF
An integrated circuit device and a method for making it are provided. The integrated circuit device comprises plural conductive layers, plural dielectric layers and plural first stopping layers. The conductive layers are extending in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers.
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1. Technical Field
The disclosure relates in general to an integrated circuit device and method for making such connector access region.
2. Description of the Related Art
Dimensions of integrated circuits continue to become smaller in order to fit more circuitry in a given area. Multilayer integrated circuits have had the width of the electrically conductive layers in a set of parallel electrically conductive layers, as well as the width of the dielectric layers separating the electrically conductive layers, reduced. However, the lateral dimensions or diameters for the interlayer connectors, including plugs and vias, which contact the individual electrically conductive layers, is often large enough so that the possibility of a single interlayer connector contacting two adjacent electrically conductive layers has become a problem. While various schemes have been devised in response to this issue, none are ideal for all circumstances. See, for example, the following co-pending U.S. patent application Ser. No. 13/049,303, filed 16 Mar. 2011, entitled REDUCED NUMBER OF MASK FOR IC DEVICE WITH STACKED CONTACT LEVELS; and Ser. No. 13/114,931, filed 24 May 2011, entitled MULTILAYER CONNECTION STRUCTURE AND MAKING METHOD.
SUMMARYThe disclosure is directed to a connector access region of an integrated circuit device and method for making thereof. The connector access region in the embodiment could prevent short circuit from occurring between adjacent conductive layers. Also, the power consumption and RC delay between adjacent conductive layers of connector access region of the embodiment is relieved.
According to one embodiment, an integrated circuit device is provided. The integrated circuit device comprises plural conductive layer, plural dielectric layers and plural first stopping layers. The conductive layers are extended in a first direction. The dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement. The first stopping layers are disposed over the conductive layers and the dielectric layers. The first stopping layers make no contact with the conductive layers
According to another embodiment, a method for making integrated circuit device is provided. The method comprises forming a plurality of conductive layers, wherein the conductive layers are spaced apart to each other in an interval and extending in a first direction; forming a plurality of dielectric layers paralleled to the conductive layers, wherein the conductive layers and the dielectric layers are disposed in an alternative arrangement; and forming a plurality of first stopping layers over the conductive layers and the dielectric layers, wherein the first stopping layers make no contact with the conductive layers.
The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
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By tilting the arrangement of the contact areas, the short circuit between adjacent conductive layers could be avoided. That is, the integrated circuit device may be used for connection of high-density wire, especially for wire formed from double patterning process, such as word line and bit line.
There are more room in the nearby regions of the contact areas in the embodiment. That is, the OPC of mask could be more precise, and the litho pattern will much fit the need. Beside, limiting the positions of the contact areas between the interlayer connectors and the conductive layer connector prevents the connector recess region from short circuit. Moreover, since the stopping layer is above the conductive layers (
It is notable that the connector recess region of the embodiment is not limited to the mutilayer integrated circuit. This design may also be used for regular contact area or interconnection structure with fewer conductive layers.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
Claims
1. An integrated circuit device with a connector access region, comprising:
- a plurality of conductive layers, wherein the conductive layers are extending in a first direction;
- a plurality of dielectric layers, wherein the dielectric layers are paralleled to the conductive layers, and the conductive layers and the dielectric layers are disposed in an alternative arrangement; and
- a plurality of first stopping layers, wherein the first stopping layers are disposed over the conductive layers and the dielectric layers, and the first stopping layers make no contact with the conductive layers.
2. The integrated circuit device according to claim 1, further comprising:
- a plurality of extending portions disposed on and electrically connected to the conductive layers, wherein each top of the extending portions provides a contact area, the contact areas defining a contact plane, the conductive layers extending below the contact plane, the contact areas being arranged along a second direction, and the angle between the first direction and the second direction is larger than zero; and
- a plurality of interlayer connectors extending above the contact plane, wherein the interlayer connectors electrically connected to the contact areas and electrically isolated from the conductive layers adjacent to the contact areas.
3. The integrated circuit device according to claim 2, further comprising:
- an electrically insulating material covering the conductive layers except for the part connected to the extending portions.
4. The integrated circuit device according to claim 3, further comprising:
- a second stopping layer disposed between the electrically insulating material and the interlayer connectors.
5. The integrated circuit device according to claim 4, further comprises:
- a plurality of isolating layers disposed on the second stopping layer for separating the interlayer connectors.
6. The integrated circuit device according to claim 2, wherein the contact areas have rectangular shape.
7. The integrated circuit device according to claim 2, wherein the arrangement of the contacts areas constitutes at least two virtual lines, and the virtual lines are extended along the second direction.
8. The integrated circuit device according to claim 2, wherein the width of the conductive layers is Y, and the width of the contact areas is between Y to 1.5Y.
9. The integrated circuit device according to claim 2, wherein the length of the contact areas is X, and the width of the contact areas is between 2X to 20X.
10. A method for making an integrated circuit device with a connector access region, comprising:
- forming a plurality of conductive layers spaced apart to each other in an interval and extending in a first direction;
- forming a plurality of dielectric layers paralleled to the conductive layers, wherein the conductive layers and the dielectric layers are disposed in an alternative arrangement; and
- forming a plurality of first stopping layers over the conductive layers and the dielectric layers, and the first stopping layers making no contact with the conductive layers.
11. The method according to claim 10, further comprising:
- forming a plurality of extending portions, the extending portions disposed on and electrically connected to the conductive layers, wherein each top of the extending portions is a contact area, the contact areas defining a contact plane, the conductive layers extending below the contact plane, the contact areas being arranged along a second direction, and the angle between the first direction and the second direction is larger than zero; and
- forming a plurality of interlayer connectors extending above the contact plane, wherein the interlayer connectors are electrically connected to the contact areas but electrically isolated from the conductive layers adjacent to the contact areas.
12. The method according to claim 11, wherein before the step of forming extending portions, further comprising:
- forming an electrically insulating material covering the conductive layers;
- forming a second stopping layer on the electrically insulating material; and
- etching the second stopping layer and the electrically insulating material to form a plurality of openings,
- wherein the extending portions are formed in the openings.
13. The method according to claim 12, wherein after the step of forming second stopping layer, further comprising:
- forming a plurality of isolating layers on the second stopping layer, the isolating layers spaced apart by trenches, the trenches positioned correspondingly to the contact areas,
- wherein the interlayer connectors are formed in the trenches.
14. The method according to claim 11, wherein the contact areas have rectangular shape.
15. The method according to claim 11, wherein the arrangement of the contacts areas constitutes at least two virtual lines, and the virtual lines are extended along the second direction.
16. The method according to claim 11, wherein the width of the conductive layers is Y, and the width of the contact areas is between Y to 1.5Y.
17. The method according to claim 11, wherein the length of the contact areas is X, and the width of the contact areas is between 2X to 20X.
Type: Application
Filed: Nov 11, 2013
Publication Date: May 14, 2015
Applicant: MACRONIX INTERNATIONAL CO., LTD. (Hsinchu)
Inventor: Shih-Hung Chen (Hsinchu County)
Application Number: 14/076,376
International Classification: H01L 23/532 (20060101); H01L 21/768 (20060101); H01L 23/528 (20060101);