Abstract: The present application provides a method of preparing a semiconductor structure. The method includes providing a conductive film; disposing a barrier layer over the conductive film; disposing a first dielectric layer over the barrier layer; disposing a patterned hard mask over the first dielectric layer; and removing a portion of the first dielectric layer exposed through the patterned hard mask, wherein the removal of the portion of the first dielectric layer includes providing a nitrogen plasma to collide with the portion of the first dielectric layer.
Abstract: A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.
Type:
Grant
Filed:
December 8, 2022
Date of Patent:
January 7, 2025
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Trevor Timpane, Layne A. Berge, Patryk Gumann, Sean Hart, Curtis Eugene Larsen, Michael Good
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of interconnects disposed within a dielectric structure over a substrate. A conductor is disposed over at least one of the plurality of interconnects. A protective layer is disposed on the conductor and a mask layer is disposed on the protective layer. One or more passivation layers are disposed on the mask layer. The protective layer, the mask layer, and the one or more passivation layers respectively have one or more sidewalls directly over the conductor.
Abstract: Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The semiconductor structures may include an upper conductive line, a first lower conductive line laterally insulated by a first lower dielectric region and a second lower dielectric region. The semiconductor structure also includes a lower level via region above the first lower conductive line. The lower level via region includes a dielectric blocking material and a spacer material.
Type:
Grant
Filed:
July 19, 2021
Date of Patent:
November 12, 2024
Assignee:
International Business Machines Corporation
Inventors:
Lawrence A. Clevenger, Brent Anderson, Nicholas Anthony Lanzillo
Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
Abstract: A semiconductor structure and a method for manufacturing same. The semiconductor structure includes a storage unit, which includes: a first dielectric layer and a metal bit line located therein; a semiconductor channel, located on the metal bit line; a word line, disposed surrounding part of the semiconductor channel; a second dielectric layer, located between the metal bit line and the word line, and on top of the word line; a first and a second lower electrode layers, stacked on the semiconductor channel, the first lower electrode layer contacting the top surface of the semiconductor channel; an upper electrode layer, located on top of the second lower electrode layer, and surrounding the first and the second lower electrode layers; and a capacitor dielectric layer, located between the upper electrode layer and the first lower electrode layer, and between the upper electrode layer and the second lower electrode layer.
Abstract: An integrated circuit device includes a substrate; an integrated circuit region on the substrate, said integrated circuit region comprising a dielectric stack; a seal ring disposed in said dielectric stack and around a periphery of the integrated circuit region; a trench around the seal ring and exposing a sidewall of the dielectric stack; and a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.
Abstract: An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.
Abstract: The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate.
Abstract: Pattern transfer sheets, methods of monitoring pattern transfer printing, and pattern transfer printing systems are provided, for monitoring and adjusting laser illumination used for transferring paste patterns from trenches on the sheets onto a substrate such as electronic circuitry and/or solar cell substrates. Pattern transfer sheets comprise, outside the pattern, (i) trace mark(s) configured to receive the printing paste, aligned to the trenches and are wider than the width of the illuminating laser beam—to detect misalignment of paste release from within the trace mark(s) and/or (ii) working window marks configured to receive the printing paste, set at specified offsets with respect to specific trenches, with different working window marks set at different offsets—to correct the effective working window by adjusting the power of the laser beam.
Type:
Grant
Filed:
July 14, 2022
Date of Patent:
October 1, 2024
Assignee:
Wuhan DR Laser Technology Corp, . LTD
Inventors:
Amir Noy, Benny Naveh, Eyal Cohen, Valery Sorin, Dor Dror
Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: filling a trench of a stacking structure with a bottom anti-reflection coated material to form a dummy via in the trench, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and etching the dummy via by performing a first etching process and a second etching process.
Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
Type:
Grant
Filed:
July 25, 2023
Date of Patent:
August 27, 2024
Assignee:
Taiwan Semiconductor Manufacturing Company Limited
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.
Type:
Grant
Filed:
November 1, 2021
Date of Patent:
July 23, 2024
Assignee:
GLOBALFOUNDRIES U.S. Inc.
Inventors:
James P. Mazza, Elizabeth Strehlow, Motoi Ichihashi, Xuelian Zhu, Jia Zeng
Abstract: A discrete metal-insulator-metal (MIM) energy storage component, the energy storage component comprising: a MIM-arrangement comprising: a first electrode layer; a plurality of conductive nanostructures grown from the first electrode layer; a conduction controlling material covering each nanostructure in the plurality of conductive nanostructures and the first electrode layer uncovered by the conductive nanostructures; and a second electrode layer covering the conduction controlling material; a first connecting structure for external electrical connection of the capacitor component; a second connecting structure for external electrical connection of the capacitor component; and an electrically insulating encapsulation material at least partly embedding the MIM-arrangement.
Type:
Grant
Filed:
October 7, 2019
Date of Patent:
July 9, 2024
Assignee:
SMOLTEK AB
Inventors:
Vincent Desmaris, Rickard Andersson, Muhammad Amin Saleem, Maria Bylund, Anders Johansson, Fredrik Liljeberg, Ola Tiverman, M Shafiqul Kabir
Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a side all of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure.
Abstract: A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.
Type:
Grant
Filed:
June 21, 2023
Date of Patent:
July 2, 2024
Assignee:
Taiwan Semiconductor Manufacturing Company Limited
Inventors:
Jen-Yuan Chang, Chien-Chang Lee, Chia-Ping Lai
Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a shallow trench isolation (STI) region, and a capacitor. The STI region is embedded in the semiconductor substrate. The capacitor includes first and second conductive stacks. The first conductive stack includes a first dummy gate strip disposed entirely within the STI region and a plurality of first metal dummy gate contacts landing on the first metal capacitor strip. The second conductive stack includes a second dummy gate strip disposed entirely within the STI region and extending in parallel with the first dummy gate strip, and a plurality of second dummy gate contacts landing on the second dummy gate strip, wherein the first conductive stack is electrically isolated from the second conductive stack.
Abstract: Integrated devices comprising integrated circuits and energy storage devices are described. Disclosed energy storage devices correspond to an all-solid-state construction, and do not include any gels, liquids, or other materials that are incompatible with microfabrication techniques. Disclosed energy storage device comprises energy storage cells with electrodes comprising metal-containing compositions, like metal oxides, metal nitrides, or metal hydrides, and a solid state electrolyte.
Abstract: There may be provided a method of manufacturing a semiconductor chip. A layer stack in which first material layers and second material layers are alternately stacked is formed on a semiconductor substrate that includes a chip region and a scribe lane region, and crack propagation guides are formed in a first portion of the layer stack within the scribe lane region.
Abstract: A semiconductor structure and a method for forming the same are provided. The method for forming a semiconductor structure includes the following operations. A substrate is provided. A dielectric layer having a first trench is formed on the substrate. A first filling layer is formed for partially filling the first trench. A first mask layer having a first opening is formed on the dielectric layer. The first opening exposes the first filling layer and part of the dielectric layer. The dielectric is etched by taking the first mask layer as a mask to form a second trench. The first filling layer is removed. And, conductive materials are formed in the first trench and the second trench.
Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes at least two electrode layers, and the electrode layers are parallel to each other and arranged in different layers. Adjacent electrode layers overlap with each other and have an overlapping area, a dielectric layer is arranged between the adjacent electrode layers, and an air gap is arranged in the dielectric layer located in the overlapping area.
Abstract: Some embodiments relate to a semiconductor device disposed on a semiconductor substrate. A dielectric structure is arranged over the semiconductor substrate. First and second metal vias are disposed in the dielectric structure and spaced laterally apart from one another. First and second metal lines are disposed in the dielectric structure and have nearest neighboring sidewalls that are spaced laterally apart from one another by a portion of the dielectric structure. The first and second metal lines contact upper portions of the first and second metal vias, respectively. First and second air gaps are disposed in the portion of the dielectric structure. The first and second air gaps are proximate to nearest neighboring sidewalls of the first and second metal lines, respectively.
Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.
Type:
Grant
Filed:
February 6, 2021
Date of Patent:
April 9, 2024
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.
Type:
Grant
Filed:
June 7, 2021
Date of Patent:
April 2, 2024
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.
Abstract: A semiconductor device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The substrate includes a dense region and an isolation region. The first metal layer is disposed over the substrate and includes a first metal pattern and a second metal pattern. The first metal pattern is located in the dense region. There is at least one slot in the first metal pattern. The second metal pattern is located in the isolation region. The dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the dielectric layer.
Abstract: The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.
Abstract: A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.
Abstract: In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.
Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.
Abstract: Disclosed is an RF switch device and, more particularly, an RF switch device having an air gap over a gate electrode and a metal interconnect at a position higher than the air gap and that at least partially overlap the air gap in the vertical direction, thereby preventing exposure of an upper portion of the air gap in subsequent processing.
Type:
Grant
Filed:
April 11, 2022
Date of Patent:
November 28, 2023
Assignee:
DB HiTek, Co., Ltd.
Inventors:
Seung Hyun Eom, Jin Hyo Jung, Hae Taek Kim, Ja Geon Koo, Ki Won Lim, Hyun Joong Lee, Sang Yong Lee
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bond pad disposed over a substrate and a passivation structure disposed over the substrate and the bond pad. The passivation structure has one or more sidewalls directly over the bond pad. A protective layer is disposed directly between the passivation structure and the bond pad. The passivation structure extends from directly over the protective layer to laterally past a sidewall of the protective layer that faces a central region of the bond pad.
Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.
Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
Type:
Grant
Filed:
December 7, 2022
Date of Patent:
September 19, 2023
Assignees:
UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
Abstract: A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.
Type:
Grant
Filed:
August 27, 2021
Date of Patent:
August 15, 2023
Assignee:
Taiwan Semiconductor Manufacturing Company Limited
Inventors:
Jen-Yuan Chang, Chien-Chang Lee, Chia-Ping Lai
Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.
Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.
Abstract: A substrate processing method includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film by vapor deposition. In one example, the first film, second film, and the third film are selected from the group consisting of a metal film, a metal-containing liner, and a dielectric film.
Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.
Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
Type:
Grant
Filed:
April 14, 2021
Date of Patent:
March 7, 2023
Assignee:
SAMSUNG ELECTRONICS CO., LTD.
Inventors:
Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
Abstract: Moisture-driven degradation of a crack stop in a semiconductor die is mitigated by forming a groove in an upper surface of the die between an edge of the die and the crack stop; entirely filling the groove with a moisture barrier material; preventing moisture penetration of the semiconductor die by presence of the moisture barrier material; and dissipating mechanical stress in the moisture barrier material without presenting a stress riser in the bulk portion of the die. The moisture barrier material is at least one of moisture-absorbing, moisture adsorbing, and hydrophobic.
Type:
Grant
Filed:
December 5, 2020
Date of Patent:
January 31, 2023
Assignee:
International Business Machines Corporation
Inventors:
Sushumna Iruvanti, Shidong Li, Steve Ostrander, Jon Alfred Casey, Brian Richard Sundlof
Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.
Abstract: A DNA sequencing device and related methods, wherein the device includes a substrate, a nanochannel formed in the substrate, a first electrode positioned on a first side of the nanochannel, and a second electrode. The second electrode is positioned on a second side of the nanochannel opposite the first electrode and is spaced apart from the first electrode to form an electrode gap that is exposed in the nanochannel. At least a portion of first electrode is movable relative to the second electrode to decrease a size of the electrode gap.
Type:
Grant
Filed:
June 23, 2020
Date of Patent:
January 3, 2023
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Kim Yang Lee, Thomas Young Chang, David S. Kuo, ShuaiGang Xiao, Xiaomin Yang, Koichi Wago
Abstract: An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.
Type:
Grant
Filed:
June 7, 2019
Date of Patent:
November 8, 2022
Assignee:
TEXAS INSTRUMENTS INCORPORATED
Inventors:
Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield
Abstract: A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.
Type:
Grant
Filed:
February 12, 2021
Date of Patent:
October 4, 2022
Assignee:
Western Digital Technologies, Inc.
Inventors:
Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
Abstract: Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.
Type:
Grant
Filed:
October 23, 2018
Date of Patent:
September 13, 2022
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
Joshua T. Smith, Robert Bruce, Jyotica V. Patel, Benjamin Wunsch
Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
Type:
Grant
Filed:
March 16, 2020
Date of Patent:
July 19, 2022
Assignee:
Micron Technology, Inc.
Inventors:
Jordan D. Greenlee, Christian George Emor, Luca Fumagalli, John D. Hopkins, Rita J. Klein, Christopher W. Petz, Everett A. McTeer
Abstract: A plasma processing method of etching an organic film through a mask having an opening is provided. The mask is formed on the organic film, and is made of a silicon-containing film. The method includes rectifying a shape of the mask. The rectifying of the shape of the mask includes refining a side wall of the opening of the mask, and etching an upper surface of the mask.
Abstract: The present invention is directed to an electrophoretic display device comprising microcells filled with an electrophoretic fluid and a dielectric layer, which comprises a first type of magnetic filler material, a second type of nonmagnetic filler material, and a polymeric material. The first and second types of filler material physically interact with each other and they are fixed and aligned in the dielectric adhesive layer in a direction perpendicular to a plane of the dielectric layer. The dielectric layer exhibits anisotropic conductivity having higher conductivity in the z direction compared to the other two orthogonal directions.
Type:
Grant
Filed:
February 28, 2020
Date of Patent:
June 28, 2022
Assignee:
E INK CALIFORNIA, LLC
Inventors:
Craig Lin, Yu Li, Peter B. Laxton, Lei Liu, Hui Du, HongMei Zang