Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) Patents (Class 438/622)
  • Patent number: 10707120
    Abstract: An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: July 7, 2020
    Assignee: Tower Semiconductor Ltd.
    Inventors: Bouhnik Yami, Nagar Magi, Barhum Liat, Alexey Heiman, Yakov Roizin
  • Patent number: 10686011
    Abstract: A semiconductor device integrated with memory device includes a substrate, having a first side and a second side. A transistor circuit layer is disposed over the substrate at the first side. An interconnect structure layer is disposed over the transistor circuit layer with electric connection to form a circuit route. A memory cell layer is disposed over the interconnect structure layer or over a second side of the substrate, in connection to the circuit route. The memory cell layer includes a plurality of memory cells, and a cell structure of the memory cells includes an oxide semiconductor field effect transistor and a memory element.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 16, 2020
    Assignee: United Microelectronics Corp.
    Inventor: Zhi-Biao Zhou
  • Patent number: 10665474
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 10637105
    Abstract: A battery embedded structure is disclosed. The battery embedded structure comprises a substrate including one or more stacked battery units. Each stacked battery unit includes two or more conductive layers and one or more unit cells. Each unit cell is disposed between two conductive layers. The substrate has a principal surface provided by one or more respective side surfaces of the one or more stacked battery units. The battery embedded structure also comprises a wiring layer disposed on the principal surface of the substrate. The wiring layer includes a plurality of electrical paths and a plurality of vias. Each via is connected with one electrical path. Each via is located at a position corresponding to an edge surface of a conductive layer of the two or more conductive layers of the one or more stacked battery units so as to contact electrically to that conductive layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keiji Matsumoto, Hiroyuki Mori
  • Patent number: 10596626
    Abstract: An additive manufacturing system including a two-dimensional energy patterning system for imaging a powder bed is disclosed. Improved structure formation, part creation and manipulation, use of multiple additive manufacturing systems, and high throughput manufacturing methods suitable for automated or semi-automated factories are also disclosed.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: March 24, 2020
    Assignee: SEURAT TECHNOLOGIES, INC.
    Inventors: James A. DeMuth, Erik Toomre, Francis L. Leard, Kourosh Kamshad, Heiner Fees, Eugene Berdichevsky
  • Patent number: 10580721
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first conductive layer covering a part of the first main surface; a through electrode connected to the first conductive layer and having a first conductive plated layer and a second conductive plated layer; and a second conductive layer formed on the second main surface. The first conductive plated layer contacts with the semiconductor substrate through a seed layer. The second conductive plated layer is formed on the first conductive plated layer. The second conductive layer is formed of the seed layer, the first conductive plated layer, and the second conductive plated layer. The first conductive plated layer has a first edge surface. The second conductive plated layer has a second edge surface flush with the first edge surface.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: March 3, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akihiko Nomura
  • Patent number: 10563304
    Abstract: Atomic layer deposition (ALD) processes are combined with physical vapor deposition (PVD) processes in a low pressure environment to produce a high quality barrier film. The initial barrier film is deposited on a substrate using ALD processes and then moved to a PVD chamber to treat the barrier film to increase the barrier film's density and purity, decreasing the barrier film's resistivity. A dual source of materials is sputtered onto the substrate to provide doping while a gas is simultaneously used to etch the substrate to release nitrogen. At least one source of material is positioned to provide doping at an acute angle to the surface of the substrate while supplied with DC power and RF power at a first RF power frequency. The substrate is biased using RF power at a second RF power frequency.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 18, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xiangjin Xie, Adolph Miller Allen, Xianmin Tang, Goichi Yoshidome
  • Patent number: 10559644
    Abstract: A display device includes a substrate having a pixel area with at least a first rounded corner portion and first to third non-pixel areas arranged sequentially along an outer circumference of the pixel area. An internal circuit in the first non-pixel area has a first end portion adjacent to the first rounded corner portion of the pixel area. The first end portion of the internal circuit is rounded in accordance with the first rounded corner portion. A plurality of routing wires are in the third non-pixel area below the pixel area. The routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area. The routing wires include at least a first routing wire connected to the pixel area passing an area of the first end portion of the internal circuit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Kyu Lee, Yang Wan Kim, Sun Ja Kwon, Byung Sun Kim, Hyun Ae Park, Su Jin Lee, Jae Yong Lee, Tae Hoon Kwon, Seung Ji Cha
  • Patent number: 10553452
    Abstract: A printed circuit board includes first and second insulating layers forming a cavity, a first heat releasing layer formed on an exterior surface of the cavity, and a circuit layer formed above or below the first the insulating layer and at least between a surface of the cavity and the first insulating layer. The heat releasing layer is electrically connected to at least a portion of the circuit layer.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 4, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk-Chang Hong, Hyo-Bin Park, Dong-Kwang Shin, Sang-Jin Baek
  • Patent number: 10510561
    Abstract: In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Yu Tsai, Tsung-Shang Wei, Yu-Sheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10510696
    Abstract: A method of manufacturing a semiconductor device includes: forming a memory cell on a substrate; forming a conductive pad region to electrically couple to the memory cell; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and etching the second passivation layer to expose a second area of the conductive pad region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 10510592
    Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Kuan-Chieh Huang
  • Patent number: 10490404
    Abstract: Systems and methods for in situ hard mask removal are described. In an embodiment, a method includes receiving a semiconductor workpiece comprising a substrate, an intermediary layer, a hard mask layer, and a photoresist layer in an etch chamber. The method may also include etching the hard mask layer to open a region left exposed by the photoresist layer. Additionally, such an embodiment may include etching the intermediary layer in a region left exposed by the hard mask layer. The method may also include removing the hard mask layer. In such embodiments, etching the hard mask layer, etching the intermediary layer, and removing the hard mask layer are performed in the etch chamber, and without the wafer being removed from the etch chamber.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 26, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Christopher Talone, Andrew Nolan, Mingmei Wang, Alok Ranjan
  • Patent number: 10475995
    Abstract: A variable resistance memory cell with a wide difference (“window”) between threshold voltages is provided. The window between threshold voltages is increased by amplifying the stoichiometry gradient by means of an asymmetry in the memory cell architecture to provide a greater margin for detecting different logic states of the memory cell.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventor: Paolo Fantini
  • Patent number: 10446484
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John M. Safran, Jochonia N. Nxumalo, Joyce C. Liu, Sami Rosenblatt, Chandrasekharan Kothandaraman
  • Patent number: 10446490
    Abstract: A method of forming an interconnect structure includes providing a first dielectric layer, patterning a wire opening in a first dielectric layer, lining the wire opening with a metal liner and includes filling the wire opening with a first conductive material. The method also includes depositing a first cap on the first dielectric layer, depositing a second dielectric layer, and patterning a via trench in the second dielectric layer. The method also includes depositing a metal liner, removing the metal liner from a via junction, and enlarging the contact area. The method also includes filling the via trench with a second conductive material to form a via.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10403596
    Abstract: A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of conducive vias that penetrate the dielectric layer, an electronic component disposed on the first surface of the dielectric layer and electrically connected to the wiring layer, an encapsulant encapsulating the electronic component, and a packaging substrate disposed on the second surface and electrically connected to the conductive vias. With the dielectric layer in replacement of a conventional silicon board and the wiring layer as a signal transmission medium between the electronic component and the packaging substrate, the package structure does not need through-silicon vias. Therefore, the package structure has a simple fabrication process and a low fabrication cost. The present invention further provides a method of fabricating the package structure.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Indsutries Co., Ltd.
    Inventors: Hsien-Wen Chen, Shih-Ching Chen, Chieh-Lung Lai
  • Patent number: 10405431
    Abstract: A flexible printed circuit board with reduced ion migration from signal-carrying elements which are coated against corrosion includes an insulating layer, a wiring area, a copper electroplating layer, a nickel electroplating layer, a cover film, and a gold chemical-plating layer. The wiring area is formed on the insulating layer. The copper electroplating layer formed on the wiring area has a first portion and a second portion. The nickel electroplating layer is formed on at least the first portion and exposes sidewalls of the first portion. The cover film is formed on the second portion and fills in gaps of the copper electroplating layer. The gold chemical-plating layer is formed on top surface of the nickel electroplating layer and the sidewalls of the first portion.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 3, 2019
    Assignees: Avary Holding (Shenzhen) CO., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Lei Zhou, Rui-Wu Liu, Qiong Zhou
  • Patent number: 10361117
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10304774
    Abstract: A semiconductor structure having tapered damascene aperture is disclosed. The semiconductor structure including an etching stop layer over an inter-layer dielectric (ILD) layer, a low-k dielectric layer over the etching stop layer, and a tapered aperture at least going into the low-k dielectric layer; wherein the tapered aperture is filled with copper (Cu), a width of a mouth surface portion of the aperture tapers inwardly from a first, wider width to a second, narrower width at a bottom surface portion of the aperture, and the width of the bottom surface portion of the tapered aperture is less than 50 nm. Associated methods of fabricating a semiconductor structure are also disclosed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • Patent number: 10283449
    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 7, 2019
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 10269712
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Patent number: 10249444
    Abstract: The disclosure provides for electrochemical supercapacitors with high energy densities, based on paired groups of carbon nanotube mounted to conductive substrates. In one variation, the electrochemical supercapacitors are double layer capacitors, or electrochemical double layer capacitors, containing opposing groups of carbon nanotubes on opposing substrates. In another variation, the capacitor is an interdigitated capacitor of alternating electrode containing carbon nanotubes, mounted on a common substrate. Processes and devices are also described.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 2, 2019
    Assignee: Georgia Tech Research Corporation
    Inventor: William Jud Ready
  • Patent number: 10199271
    Abstract: A structure and method for forming a self-aligned metal wire on a contact structure. The method for forming the self-aligned metal wire and contact structure may include, among other things, forming an initial contact structure above a substrate; forming a patterned mask on the initial contact structure, the mask including an opening; using the patterned mask to form an opening through the initial contact structure; forming a dielectric layer in the openings; removing the patterned mask to expose a remaining portion of the initial contact structure; and forming the metal wire on the remaining portion of the initial contact structure. The contact structure may include a vertical cross-sectional geometry including one of a trapezoid wherein a bottommost surface of the first contact structure is wider than an uppermost surface of the first contact structure, and a parallelogram. The metal wire may completely contact an uppermost surface of the contact structure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Guillaume Bouche, Laertis Economikos, Lei Sun, Guoxiang Ning, Xunyuan Zhang
  • Patent number: 10170307
    Abstract: A semiconductor device and method includes a method. The method includes patterning a plurality of first mandrels over a first mask layer. The method further includes forming a first spacer layer on sidewalls and tops of the first mandrels. The method further includes removing horizontal portions of the first spacer layer, with remaining vertical portions of the first spacer layer forming first spacers. The method further includes, after removing the horizontal portions of the first spacer layer, depositing a reverse material between the first spacers. The method further includes patterning the first mask layer using the first spacers and the reverse material in combination as a first etching mask.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Wei Huang, Yu-Yu Chen
  • Patent number: 10164080
    Abstract: Art electrode pair enables the performance of a device to be accurately delivered, a method for manufacturing the same. An electrode pair 10, wherein one electrode 12A and the other electrode 12B are provided on the same plane so as to face each other with a gap 17 therebetween, and portions of the one electrode 12A and the oilier electrode 12B facing each other are respectively curved so as to get away from the plane along a direction nearing each other. This electrode pair 10 is manufactured by preparing, as a sample, a substrate on which a pair of seed electrodes is formed with a space therebetween so as to have an initial gap, immersing the sample in an electroless plating solution, changing the electroless plating solution after a lapse of a certain period of time, and adjusting the number of times of changing.
    Type: Grant
    Filed: March 9, 2014
    Date of Patent: December 25, 2018
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Shuhei Takeshita
  • Patent number: 10163974
    Abstract: In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Chung Su, Hung-Wen Hsu, Jiech-Fun Lu, Shih-Pei Chou
  • Patent number: 10074731
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a target layer over a substrate and forming a seed layer over the target layer. The method includes forming a hard mask layer over the seed layer, and the hard mask layer includes an opening to expose a portion of the seed layer. The method includes forming a conductive layer in the opening, and the conductive layer is selectively formed on the portion of the seed layer. The method includes etching a portion of the target layer by using the conductive layer as a mask.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Wei Wang, Chia-Hao Chang, Wen-Cheng Luo
  • Patent number: 10074618
    Abstract: A semiconductor structure includes a die including a first surface and a second surface opposite to the first surface; a first interconnect structure disposed at the first surface, and including a first dielectric layer and a first conductive member disposed within the first dielectric layer; a molding surrounding the die and the first interconnect structure; a second interconnect structure disposed over the second surface and the molding, and including a second dielectric layer and a second conductive member disposed within the second dielectric layer; a first seal ring is disposed within the second dielectric layer and disposed over the molding; and a conductive bump disposed over the second interconnect structure.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: September 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10049878
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 10032671
    Abstract: The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an etching gas. Alternatively, peeling is performed while an etching gas for a peeling layer is blown to the peeling layer in an atmosphere of an etching gas. Specifically, an etching gas is blown to a part to be peeled while a layer to be peeled is torn off from a substrate. Alternatively, peeling is performed in an etchant for a peeling layer while supplying an etchant to the peeling layer.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Eiji Sugiyama, Yoshitaka Dozen, Yumiko Ohno, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 10020337
    Abstract: Provided is a photoelectric conversion device including: a semiconductor substrate having a photoelectric conversion unit; a first conductive layer formed over the semiconductor substrate; a first diffusion prevention layer formed over the first conductive layer; and a light guide that guides an incident light into the photoelectric conversion unit, in which the first diffusion prevention layer contains hydrogen atoms and carbon atoms, and a composition ratio of the hydrogen atoms is greater than or equal to 46 at % and less than or equal to 50 at %.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: July 10, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hideomi Kumano
  • Patent number: 10014197
    Abstract: The present invention provides a semiconductor device manufacturing method that can sense the atmospheric air leakage more precisely and that can prevent too many defective products from being manufactured. The semiconductor device manufacturing method according to the embodiment includes the steps of: forming a barrier layer over an interlayer insulating film over a semiconductor substrate; forming a wiring layer over the barrier layer; forming a mask having an opening and configured by a photosensitive organic film over the wiring layer; patterning the wiring layer by etching the wiring layer through the opening; and removing the mask by a plasma processing using an ashing gas. The step of removing the mask includes the step of sensing an atmospheric air leakage that is mixture of the atmospheric air into the ashing gas by measuring an emission intensity of nitrogen in the ashing gas using an ultraviolet photometer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 3, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sakae Terakado, Yohei Hamaguchi
  • Patent number: 10008448
    Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 26, 2018
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Mehul B. Naik, Yong Cao, Mei-yee Shek
  • Patent number: 9984919
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first section of a mandrel is covered with a feature of an etch mask. A top surface of a second section of the mandrel is exposed by the feature of the etch mask and is recessed with an etching process. A conductive via is formed that reproduces a shape of the first section of the mandrel, and a conductive line is formed that reproduces a shape of the second section of the mandrel. The mandrel is removed to release the conductive via and the conductive line.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: May 29, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Chanro Park, Yongan Xu, Peng Xu, Yann Mignot
  • Patent number: 9984964
    Abstract: An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Lin, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Praneeth Narayanasetti
  • Patent number: 9953924
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Patent number: 9934980
    Abstract: A method utilizing a chemical mechanical polishing process to remove a patterned material stack comprising at least one pattern transfer layer and a template layer during a rework process or during a post pattern transfer cleaning process is provided. The pattern in the patterned material stack is formed by pattern transfer of a directed self-assembly pattern generated from microphase separation of a self-assembly material.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jassem A. Abdallah, Raghuveer R. Patlolla, Brown C. Peethala
  • Patent number: 9902925
    Abstract: There is provided a cleaner composition for a process of manufacturing a semiconductor and a display. The cleaner composition includes 0.01 to 5.0 wt % of amino acid-based chelating agent, 0.01 to 1.5 wt % of organic acid, 0.01 to 1.0 wt % of inorganic acid, 0.01 to 5.0 wt % of alkali compound, and the balance of deionized water and is based on acidic water with pH levels of 1 to 5. The cleaner composition may enhance metal contaminants removal capability and have a function to remove particles and organic contaminants, and prevent corrosion of copper and reverse adsorption of copper. Thus, cleaner composition may be used for various purposes of etching copper, removing residues, and a cleaner by adjusting an etch rate.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 27, 2018
    Assignees: Samsung Display Co., Ltd., LTCAM CO., LTD.
    Inventors: Dong Eon Lee, Jin Ho Ju, Jun Hyuk Woo, Seok Ho Lee
  • Patent number: 9905512
    Abstract: An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: February 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshifumi Iwasaki, Yukio Maki
  • Patent number: 9892923
    Abstract: The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric. The semiconductor substrate is introduced into a chamber configured for atomic layer deposition (ALD). A metal for the metal electrode is deposited at least on the dielectric by performing an ALD cycle. Performing the ALD cycle includes pulsing a Ti-containing precursor gas followed by pulsing a Ta-containing precursor gas, and further includes pulsing NH3 gas.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 13, 2018
    Assignee: IMEC vzw
    Inventors: Hendrik F. W. Dekkers, Lars-Ake Ragnarsson, Tom Schram
  • Patent number: 9887126
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen Peng, Jyu-Horng Shieh
  • Patent number: 9859214
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 2, 2018
    Assignee: Sony Corporation
    Inventor: Masanaga Fukasawa
  • Patent number: 9859217
    Abstract: Integrated circuit (IC) structure embodiments and methods of forming them with middle of the line (MOL) contacts that incorporate a protective cap, which provides protection from damage during back end of the line (BEOL) processing. Each MOL contact has a main body in a lower portion of a contact opening. The main body has a liner (e.g., a titanium nitride layer) that lines the lower portion and a metal layer on the liner. The MOL contact also has a protective cap in an upper portion of the contact opening above the first metal layer and extending laterally over the liner to the sidewalls of the contact opening. The protective cap has an optional liner, which is different from the liner in the lower portion, and a metal layer, which is either the same or different than the metal in the main body.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chengyu C. Niu, Vimal K. Kamineni, Mark V. Raymond, Xunyuan Zhang
  • Patent number: 9842800
    Abstract: Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate core, and forming at least one conductive interconnect structure disposed on the substrate core. The conductive interconnect structure may comprise a first side that is directly disposed on a surface of the substrate core, and a second side opposite the first side, wherein the second side comprises a greater length than a length of the first side.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventor: Robert A. May
  • Patent number: 9805996
    Abstract: A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a dielectric material layer, a conductive wiring layer, a metal core layer, and a conductive pillar layer. The conductive wiring layer is disposed on a surface of the dielectric material layer. The metal core layer having a metal part is disposed inside the dielectric material layer. The conductive pillar layer is disposed inside the dielectric material layer and between the metal core layer and the conductive wiring layer. The metal part has a first side and a second side opposite the first side. One of the first side and the second side is electrically connected to the conductive pillar layer. A width of the first side is different from a width of the second side.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: October 31, 2017
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Che-Wei Hsu, Chin-Ming Liu, Chih-Kuai Yang
  • Patent number: 9799606
    Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hoon Ahn, Sangho Rha, Jongmin Baek, Wookyung You, Nae-In Lee
  • Patent number: 9799605
    Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9793162
    Abstract: Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 17, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Claire Fenouillet-Beranger, Philippe Coronel
  • Patent number: 9793318
    Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: October 17, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai