Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) Patents (Class 438/622)
  • Patent number: 11121137
    Abstract: The present application discloses a semiconductor device with a self-aligned landing pad and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a self-aligned landing pad disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The self-aligned landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: September 14, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Te-Yin Chen
  • Patent number: 11092862
    Abstract: An electro-optical device includes a pixel electrode that is light-transmissive, a substrate that is light-transmissive and that is provided with a recessed portion open to the pixel electrode side, a light-shielding body disposed in the recessed portion, and a switching element overlapping, in a plan view from a thickness direction of the substrate, the light-shielding body, the switching element being electrically coupled to the pixel electrode, wherein the light-shielding body includes a metal film containing tungsten, and a metal nitride film that is disposed between the metal film and the substrate and that contains tungsten nitride.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 17, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 11094581
    Abstract: Provided is an integrated circuit structure and a method for manufacturing the same. The integrated circuit structure comprises a substrate; a plurality of interconnecting structures on the substrate, each of the interconnecting structures comprises side surfaces and a top surface, the side surfaces directly define air gaps therebetween isolating the interconnecting structures from each other; and a planar protective layer on top of the plurality of interconnecting structures covering all of the air gaps. The protective layer comprises a sheltering film and a supporting film.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 17, 2021
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Salahuddin Raju, Man Sun John Chan, Clarissa Cyrilla Prawoto
  • Patent number: 11049719
    Abstract: In one implementation, a processing system includes a first transfer chamber coupling to at least one epitaxy process chamber, a second transfer chamber, a transition station disposed between the first transfer chamber and the second transfer chamber, a first plasma chamber coupled to the second transfer chamber for removing oxides from a surface of a substrate, and a load lock chamber coupled to the second transfer chamber. The transition station connects to the first transfer chamber and the second transfer chamber, and the transition station includes a second plasma chamber for removing contaminants from the surface of the substrate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lara Hawrylchak, Kin Pong Lo, Errol C. Sanchez, Schubert S. Chu, Tushar Mandrekar
  • Patent number: 11049770
    Abstract: Methods and apparatus for forming an interconnect structure, including: depositing a plurality of spacers atop a low-k dielectric layer including a plurality of recessed vias, wherein one or more of the plurality of spacers is deposited atop the top surface of the low-k dielectric layer and within one or more of the plurality of recessed vias to form a one or more partially filled recessed vias; depositing a conformal metal layer atop the low-k dielectric layer, plurality of spacers, and within the one or more partially filled recessed vias to form a plurality of filled vias; etching the conformal metal layer to remove portions thereof to form a second plurality of partially filled recessed vias; and filling between the plurality spacers and within the second plurality of partially filled recessed vias with a dielectric material to form a second plurality of filled vias.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: June 29, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Suketu A. Parikh
  • Patent number: 11037799
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Patent number: 11031542
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel Charles Edelstein, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 11010533
    Abstract: Disclosed is a computer-readable medium including a program code. The program code, when executed by a processor, causes the processor to place an electrically active pattern having a first width and a first least margin area, on a layer, to place a first dummy pattern having a second width wider than the first width and having a second least margin area, on the layer, and to place a second dummy pattern having a third width and a third least margin area, on the layer, based on whether a ratio of an area of the layer to areas of the electrically active pattern and the first dummy pattern is within a reference range.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jinyoung Park
  • Patent number: 10998293
    Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Ching-Jung Yang
  • Patent number: 10991599
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus
  • Patent number: 10971396
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 10964789
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hong-Shyang Wu, Kuo-Ming Wu
  • Patent number: 10950523
    Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Wan Kim, Jung-Hoon Han, Dong-Sik Park
  • Patent number: 10943939
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 9, 2021
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Patent number: 10910498
    Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The method for fabricating the array substrate includes: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, and then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode. The method can prevent the problem that the pattern of the pixel electrode failing to connect to the pattern of the source electrode or the pattern of the drain electrode.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: February 2, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhanfeng Cao, Feng Zhang, Qi Yao
  • Patent number: 10892217
    Abstract: A wiring substrate includes first wiring portions, an insulation layer covering the first wiring portions, openings extending through the insulation layer in a thickness-wise direction, partially exposing upper surfaces of the first wiring portions, and differing from each other in capacity, and second wiring portions, each of which includes a via wiring filling one of the openings and a columnar connection terminal electrically connected to the via wiring and arranged on an upper surface of the insulation layer. The via wiring includes an electrolytic plated layer and an electroless plating structure including N layers (N is integer and ?0) arranged between the electrolytic plated layer and the upper surface of the first wiring portion exposed in a bottom of the opening. The via wiring is formed so that the electroless plating structure has a thickness that increases as a capacity of the opening filled with the via wiring is increased.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 12, 2021
    Inventors: Takashi Arai, Fumimasa Katagiri, Katsuya Fukase
  • Patent number: 10879081
    Abstract: Methods and apparatus for reducing and eliminating defects in tungsten film are disclosed herein. In the present disclosure, reducing or eliminating oxidation of a first surface of a tungsten film having a predetermined first thickness disposed upon a substrate and within a plurality of trenches is disclosed. The plurality of trenches include a predetermined depth, and a width of less than 20 nanometers. The predetermined first thickness of the tungsten film is substantially uniform throughout the plurality of trenches such that the predetermined first thickness of the tungsten film does not substantially change to a second thickness when the first surface is contacted with air or oxygen.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 29, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Guoqiang Jian, Wei Tang, Chi-Chou Lin, Paul F. Ma, Kai Wu, Vikash Banthia, Mei Chang, Jia Ye, Wenyu Zhang, Jing Zhou
  • Patent number: 10874016
    Abstract: A method for fabricating a sandwiched structure of silver-copper-silver functioning as a high frequency signal transmission structure includes an insulating sheet and a conductive circuit on the insulating sheet. The conductive circuit includes a silver conductive layer bonded to the insulating sheet, a copper conductive layer formed on the silver conductive layer, and a silver covering layer laid to cover top and side surfaces of the copper conductive layer. The silver conductive layer and the silver covering layer together enclose the copper conductive layer and the higher conductivity of the silver together with the skin effect improves high-frequency transmission efficiency of the copper.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 22, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Ming-Jaan Ho, Hsiao-Ting Hsu
  • Patent number: 10861705
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Patent number: 10833022
    Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cung D. Tran, Huaxiang Li, Bradley Morgenfeld, Xintuo Dai, Sanggil Bae, Rui Chen, Md Motasim Bellah, Dongyue Yang, Minghao Tang, Christian J. Ayala, Ravi Prakash Srivastava, Kripa Nidhan Chauhan, Pavan Kumar Chinthamanipeta Sripadarao
  • Patent number: 10832953
    Abstract: Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 10, 2020
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Matthias Wietstruck, Mehmet Kaynak, Philip Kulse, Marco Lisker, Steffen Marschmeyer, Dirk Wolansky
  • Patent number: 10813231
    Abstract: The present disclosure relates to a method for manufacturing a circuit board. The method for manufacturing the circuit board includes forming a patterned first dielectric layer on a substrate; forming an adhesive layer on the patterned first dielectric layer; forming a second dielectric layer on the adhesive layer; and patterning the second dielectric layer and the adhesive layer.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 20, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Po-Hsuan Liao, Wen-Fang Liu
  • Patent number: 10796949
    Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
  • Patent number: 10720385
    Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 10707120
    Abstract: An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: July 7, 2020
    Assignee: Tower Semiconductor Ltd.
    Inventors: Bouhnik Yami, Nagar Magi, Barhum Liat, Alexey Heiman, Yakov Roizin
  • Patent number: 10686011
    Abstract: A semiconductor device integrated with memory device includes a substrate, having a first side and a second side. A transistor circuit layer is disposed over the substrate at the first side. An interconnect structure layer is disposed over the transistor circuit layer with electric connection to form a circuit route. A memory cell layer is disposed over the interconnect structure layer or over a second side of the substrate, in connection to the circuit route. The memory cell layer includes a plurality of memory cells, and a cell structure of the memory cells includes an oxide semiconductor field effect transistor and a memory element.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 16, 2020
    Assignee: United Microelectronics Corp.
    Inventor: Zhi-Biao Zhou
  • Patent number: 10665474
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 10637105
    Abstract: A battery embedded structure is disclosed. The battery embedded structure comprises a substrate including one or more stacked battery units. Each stacked battery unit includes two or more conductive layers and one or more unit cells. Each unit cell is disposed between two conductive layers. The substrate has a principal surface provided by one or more respective side surfaces of the one or more stacked battery units. The battery embedded structure also comprises a wiring layer disposed on the principal surface of the substrate. The wiring layer includes a plurality of electrical paths and a plurality of vias. Each via is connected with one electrical path. Each via is located at a position corresponding to an edge surface of a conductive layer of the two or more conductive layers of the one or more stacked battery units so as to contact electrically to that conductive layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keiji Matsumoto, Hiroyuki Mori
  • Patent number: 10596626
    Abstract: An additive manufacturing system including a two-dimensional energy patterning system for imaging a powder bed is disclosed. Improved structure formation, part creation and manipulation, use of multiple additive manufacturing systems, and high throughput manufacturing methods suitable for automated or semi-automated factories are also disclosed.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: March 24, 2020
    Assignee: SEURAT TECHNOLOGIES, INC.
    Inventors: James A. DeMuth, Erik Toomre, Francis L. Leard, Kourosh Kamshad, Heiner Fees, Eugene Berdichevsky
  • Patent number: 10580721
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first conductive layer covering a part of the first main surface; a through electrode connected to the first conductive layer and having a first conductive plated layer and a second conductive plated layer; and a second conductive layer formed on the second main surface. The first conductive plated layer contacts with the semiconductor substrate through a seed layer. The second conductive plated layer is formed on the first conductive plated layer. The second conductive layer is formed of the seed layer, the first conductive plated layer, and the second conductive plated layer. The first conductive plated layer has a first edge surface. The second conductive plated layer has a second edge surface flush with the first edge surface.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: March 3, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akihiko Nomura
  • Patent number: 10563304
    Abstract: Atomic layer deposition (ALD) processes are combined with physical vapor deposition (PVD) processes in a low pressure environment to produce a high quality barrier film. The initial barrier film is deposited on a substrate using ALD processes and then moved to a PVD chamber to treat the barrier film to increase the barrier film's density and purity, decreasing the barrier film's resistivity. A dual source of materials is sputtered onto the substrate to provide doping while a gas is simultaneously used to etch the substrate to release nitrogen. At least one source of material is positioned to provide doping at an acute angle to the surface of the substrate while supplied with DC power and RF power at a first RF power frequency. The substrate is biased using RF power at a second RF power frequency.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 18, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xiangjin Xie, Adolph Miller Allen, Xianmin Tang, Goichi Yoshidome
  • Patent number: 10559644
    Abstract: A display device includes a substrate having a pixel area with at least a first rounded corner portion and first to third non-pixel areas arranged sequentially along an outer circumference of the pixel area. An internal circuit in the first non-pixel area has a first end portion adjacent to the first rounded corner portion of the pixel area. The first end portion of the internal circuit is rounded in accordance with the first rounded corner portion. A plurality of routing wires are in the third non-pixel area below the pixel area. The routing wires extending to the pixel area via the second non-pixel area and the first non-pixel area. The routing wires include at least a first routing wire connected to the pixel area passing an area of the first end portion of the internal circuit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Kyu Lee, Yang Wan Kim, Sun Ja Kwon, Byung Sun Kim, Hyun Ae Park, Su Jin Lee, Jae Yong Lee, Tae Hoon Kwon, Seung Ji Cha
  • Patent number: 10553452
    Abstract: A printed circuit board includes first and second insulating layers forming a cavity, a first heat releasing layer formed on an exterior surface of the cavity, and a circuit layer formed above or below the first the insulating layer and at least between a surface of the cavity and the first insulating layer. The heat releasing layer is electrically connected to at least a portion of the circuit layer.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 4, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk-Chang Hong, Hyo-Bin Park, Dong-Kwang Shin, Sang-Jin Baek
  • Patent number: 10510592
    Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Kuan-Chieh Huang
  • Patent number: 10510561
    Abstract: In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Yu Tsai, Tsung-Shang Wei, Yu-Sheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10510696
    Abstract: A method of manufacturing a semiconductor device includes: forming a memory cell on a substrate; forming a conductive pad region to electrically couple to the memory cell; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and etching the second passivation layer to expose a second area of the conductive pad region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 10490404
    Abstract: Systems and methods for in situ hard mask removal are described. In an embodiment, a method includes receiving a semiconductor workpiece comprising a substrate, an intermediary layer, a hard mask layer, and a photoresist layer in an etch chamber. The method may also include etching the hard mask layer to open a region left exposed by the photoresist layer. Additionally, such an embodiment may include etching the intermediary layer in a region left exposed by the hard mask layer. The method may also include removing the hard mask layer. In such embodiments, etching the hard mask layer, etching the intermediary layer, and removing the hard mask layer are performed in the etch chamber, and without the wafer being removed from the etch chamber.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: November 26, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Christopher Talone, Andrew Nolan, Mingmei Wang, Alok Ranjan
  • Patent number: 10475995
    Abstract: A variable resistance memory cell with a wide difference (“window”) between threshold voltages is provided. The window between threshold voltages is increased by amplifying the stoichiometry gradient by means of an asymmetry in the memory cell architecture to provide a greater margin for detecting different logic states of the memory cell.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventor: Paolo Fantini
  • Patent number: 10446490
    Abstract: A method of forming an interconnect structure includes providing a first dielectric layer, patterning a wire opening in a first dielectric layer, lining the wire opening with a metal liner and includes filling the wire opening with a first conductive material. The method also includes depositing a first cap on the first dielectric layer, depositing a second dielectric layer, and patterning a via trench in the second dielectric layer. The method also includes depositing a metal liner, removing the metal liner from a via junction, and enlarging the contact area. The method also includes filling the via trench with a second conductive material to form a via.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10446484
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John M. Safran, Jochonia N. Nxumalo, Joyce C. Liu, Sami Rosenblatt, Chandrasekharan Kothandaraman
  • Patent number: 10403596
    Abstract: A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of conducive vias that penetrate the dielectric layer, an electronic component disposed on the first surface of the dielectric layer and electrically connected to the wiring layer, an encapsulant encapsulating the electronic component, and a packaging substrate disposed on the second surface and electrically connected to the conductive vias. With the dielectric layer in replacement of a conventional silicon board and the wiring layer as a signal transmission medium between the electronic component and the packaging substrate, the package structure does not need through-silicon vias. Therefore, the package structure has a simple fabrication process and a low fabrication cost. The present invention further provides a method of fabricating the package structure.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: September 3, 2019
    Assignee: Siliconware Precision Indsutries Co., Ltd.
    Inventors: Hsien-Wen Chen, Shih-Ching Chen, Chieh-Lung Lai
  • Patent number: 10405431
    Abstract: A flexible printed circuit board with reduced ion migration from signal-carrying elements which are coated against corrosion includes an insulating layer, a wiring area, a copper electroplating layer, a nickel electroplating layer, a cover film, and a gold chemical-plating layer. The wiring area is formed on the insulating layer. The copper electroplating layer formed on the wiring area has a first portion and a second portion. The nickel electroplating layer is formed on at least the first portion and exposes sidewalls of the first portion. The cover film is formed on the second portion and fills in gaps of the copper electroplating layer. The gold chemical-plating layer is formed on top surface of the nickel electroplating layer and the sidewalls of the first portion.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 3, 2019
    Assignees: Avary Holding (Shenzhen) CO., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Lei Zhou, Rui-Wu Liu, Qiong Zhou
  • Patent number: 10361117
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10304774
    Abstract: A semiconductor structure having tapered damascene aperture is disclosed. The semiconductor structure including an etching stop layer over an inter-layer dielectric (ILD) layer, a low-k dielectric layer over the etching stop layer, and a tapered aperture at least going into the low-k dielectric layer; wherein the tapered aperture is filled with copper (Cu), a width of a mouth surface portion of the aperture tapers inwardly from a first, wider width to a second, narrower width at a bottom surface portion of the aperture, and the width of the bottom surface portion of the tapered aperture is less than 50 nm. Associated methods of fabricating a semiconductor structure are also disclosed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei Ting Chen, Che-Cheng Chang, Chen-Hsiang Lu, Yu-Cheng Liu
  • Patent number: 10283449
    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 7, 2019
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Emeka Uzoh
  • Patent number: 10269712
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Nae-In Lee
  • Patent number: 10249444
    Abstract: The disclosure provides for electrochemical supercapacitors with high energy densities, based on paired groups of carbon nanotube mounted to conductive substrates. In one variation, the electrochemical supercapacitors are double layer capacitors, or electrochemical double layer capacitors, containing opposing groups of carbon nanotubes on opposing substrates. In another variation, the capacitor is an interdigitated capacitor of alternating electrode containing carbon nanotubes, mounted on a common substrate. Processes and devices are also described.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 2, 2019
    Assignee: Georgia Tech Research Corporation
    Inventor: William Jud Ready
  • Patent number: 10199271
    Abstract: A structure and method for forming a self-aligned metal wire on a contact structure. The method for forming the self-aligned metal wire and contact structure may include, among other things, forming an initial contact structure above a substrate; forming a patterned mask on the initial contact structure, the mask including an opening; using the patterned mask to form an opening through the initial contact structure; forming a dielectric layer in the openings; removing the patterned mask to expose a remaining portion of the initial contact structure; and forming the metal wire on the remaining portion of the initial contact structure. The contact structure may include a vertical cross-sectional geometry including one of a trapezoid wherein a bottommost surface of the first contact structure is wider than an uppermost surface of the first contact structure, and a parallelogram. The metal wire may completely contact an uppermost surface of the contact structure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Guillaume Bouche, Laertis Economikos, Lei Sun, Guoxiang Ning, Xunyuan Zhang
  • Patent number: 10170307
    Abstract: A semiconductor device and method includes a method. The method includes patterning a plurality of first mandrels over a first mask layer. The method further includes forming a first spacer layer on sidewalls and tops of the first mandrels. The method further includes removing horizontal portions of the first spacer layer, with remaining vertical portions of the first spacer layer forming first spacers. The method further includes, after removing the horizontal portions of the first spacer layer, depositing a reverse material between the first spacers. The method further includes patterning the first mask layer using the first spacers and the reverse material in combination as a first etching mask.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Wei Huang, Yu-Yu Chen
  • Patent number: 10164080
    Abstract: Art electrode pair enables the performance of a device to be accurately delivered, a method for manufacturing the same. An electrode pair 10, wherein one electrode 12A and the other electrode 12B are provided on the same plane so as to face each other with a gap 17 therebetween, and portions of the one electrode 12A and the oilier electrode 12B facing each other are respectively curved so as to get away from the plane along a direction nearing each other. This electrode pair 10 is manufactured by preparing, as a sample, a substrate on which a pair of seed electrodes is formed with a space therebetween so as to have an initial gap, immersing the sample in an electroless plating solution, changing the electroless plating solution after a lapse of a certain period of time, and adjusting the number of times of changing.
    Type: Grant
    Filed: March 9, 2014
    Date of Patent: December 25, 2018
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Shuhei Takeshita