Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) Patents (Class 438/622)
  • Patent number: 11908796
    Abstract: A semiconductor device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The substrate includes a dense region and an isolation region. The first metal layer is disposed over the substrate and includes a first metal pattern and a second metal pattern. The first metal pattern is located in the dense region. There is at least one slot in the first metal pattern. The second metal pattern is located in the isolation region. The dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the dielectric layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Tseng, Wei-Lun Hu
  • Patent number: 11894264
    Abstract: The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 6, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11837548
    Abstract: A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon Bae Kim, Seo Woo Nam
  • Patent number: 11830768
    Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Christopher J. Jezewski
  • Patent number: 11830923
    Abstract: Disclosed is an RF switch device and, more particularly, an RF switch device having an air gap over a gate electrode and a metal interconnect at a position higher than the air gap and that at least partially overlap the air gap in the vertical direction, thereby preventing exposure of an upper portion of the air gap in subsequent processing.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: November 28, 2023
    Assignee: DB HiTek, Co., Ltd.
    Inventors: Seung Hyun Eom, Jin Hyo Jung, Hae Taek Kim, Ja Geon Koo, Ki Won Lim, Hyun Joong Lee, Sang Yong Lee
  • Patent number: 11832431
    Abstract: In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11824022
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bond pad disposed over a substrate and a passivation structure disposed over the substrate and the bond pad. The passivation structure has one or more sidewalls directly over the bond pad. A protective layer is disposed directly between the passivation structure and the bond pad. The passivation structure extends from directly over the protective layer to laterally past a sidewall of the protective layer that faces a central region of the bond pad.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Yeh, Chern-Yow Hsu
  • Patent number: 11776910
    Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Ling Tsai, Shen-Nan Lee, Mrunal A. Khaderbad, Chung-Wei Hsu, Chen-Hao Wu, Teng-Chun Tsai
  • Patent number: 11769695
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 11765881
    Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: September 19, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Shih-Fang Tzou, Chien-Ting Ho, Ying-Chiao Wang, Yu-Ching Chen, Hui-Ling Chuang, Kuei-Hsuan Yu
  • Patent number: 11728288
    Abstract: A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chien-Chang Lee, Chia-Ping Lai
  • Patent number: 11715752
    Abstract: A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: August 1, 2023
    Assignee: SONY GROUP CORPORATION
    Inventor: Atsushi Okuyama
  • Patent number: 11688633
    Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chiang Chen, Chun-Ting Wu, Ching-Hou Su, Chih-Pin Wang
  • Patent number: 11658066
    Abstract: A substrate processing method includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film by vapor deposition. In one example, the first film, second film, and the third film are selected from the group consisting of a metal film, a metal-containing liner, and a dielectric film.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 23, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N Tapily
  • Patent number: 11605779
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: March 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Jung-Piao Chiu, Yu-Sheng Chen, Tzu-Chiang Chen
  • Patent number: 11600569
    Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
  • Patent number: 11569181
    Abstract: Moisture-driven degradation of a crack stop in a semiconductor die is mitigated by forming a groove in an upper surface of the die between an edge of the die and the crack stop; entirely filling the groove with a moisture barrier material; preventing moisture penetration of the semiconductor die by presence of the moisture barrier material; and dissipating mechanical stress in the moisture barrier material without presenting a stress riser in the bulk portion of the die. The moisture barrier material is at least one of moisture-absorbing, moisture adsorbing, and hydrophobic.
    Type: Grant
    Filed: December 5, 2020
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sushumna Iruvanti, Shidong Li, Steve Ostrander, Jon Alfred Casey, Brian Richard Sundlof
  • Patent number: 11557605
    Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: January 17, 2023
    Assignee: Kioxia Corporation
    Inventors: Go Oike, Hanae Ishihara
  • Patent number: 11542552
    Abstract: A DNA sequencing device and related methods, wherein the device includes a substrate, a nanochannel formed in the substrate, a first electrode positioned on a first side of the nanochannel, and a second electrode. The second electrode is positioned on a second side of the nanochannel opposite the first electrode and is spaced apart from the first electrode to form an electrode gap that is exposed in the nanochannel. At least a portion of first electrode is movable relative to the second electrode to decrease a size of the electrode gap.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: January 3, 2023
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Kim Yang Lee, Thomas Young Chang, David S. Kuo, ShuaiGang Xiao, Xiaomin Yang, Koichi Wago
  • Patent number: 11495658
    Abstract: An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield
  • Patent number: 11462497
    Abstract: A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: October 4, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Patent number: 11440002
    Abstract: Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua T. Smith, Robert Bruce, Jyotica V. Patel, Benjamin Wunsch
  • Patent number: 11393756
    Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Christian George Emor, Luca Fumagalli, John D. Hopkins, Rita J. Klein, Christopher W. Petz, Everett A. McTeer
  • Patent number: 11380547
    Abstract: A plasma processing method of etching an organic film through a mask having an opening is provided. The mask is formed on the organic film, and is made of a silicon-containing film. The method includes rectifying a shape of the mask. The rectifying of the shape of the mask includes refining a side wall of the opening of the mask, and etching an upper surface of the mask.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 5, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Ryo Terashima, Yuzuru Sakai
  • Patent number: 11372305
    Abstract: The present invention is directed to an electrophoretic display device comprising microcells filled with an electrophoretic fluid and a dielectric layer, which comprises a first type of magnetic filler material, a second type of nonmagnetic filler material, and a polymeric material. The first and second types of filler material physically interact with each other and they are fixed and aligned in the dielectric adhesive layer in a direction perpendicular to a plane of the dielectric layer. The dielectric layer exhibits anisotropic conductivity having higher conductivity in the z direction compared to the other two orthogonal directions.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 28, 2022
    Assignee: E INK CALIFORNIA, LLC
    Inventors: Craig Lin, Yu Li, Peter B. Laxton, Lei Liu, Hui Du, HongMei Zang
  • Patent number: 11361993
    Abstract: A process flow is utilized for patterning of dual damascene structures in BEOL process steps. Conductor vias are inversely patterned in the form of pillars that are formed before the final dielectric stack is deposited. The final dielectric stack may include a low-k dielectric and the conductor may be ruthenium. The vias may be formed by forming conductor pillars in patterned voids of a sacrificial layer. After the pillars are formed, certain areas between the pillars can then be backfilled with a dielectric, such as for example, a low-k dielectric material. The trench conductor of the dual damascene structure may then be formed. The sacrificial dielectric may then be removed and an additional layer of low-k dielectric material can then be deposited or coated on the structure to provide the final structure having the dual damascene vias and trenches filled with the conductor surrounded by low-k material.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 14, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Angelique D. Raley, Katie Lutker-Lee
  • Patent number: 11342261
    Abstract: Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 24, 2022
    Assignee: IMEC VZW
    Inventors: Stefan Cosemans, Julien Ryckaert, Zsolt Tokei
  • Patent number: 11328992
    Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Nicholas James Harold McKubre, Richard Farrington Vreeland, Sansaptak Dasgupta
  • Patent number: 11309244
    Abstract: An exemplary method includes forming a fuse structure and forming a first cathode connector and a second cathode connector over the fuse structure. The fuse structure includes an anode, a cathode, and a fuse link extending between and connecting the anode and the cathode. The fuse link has a width defined between a first edge and a second edge, which extend a length of the fuse link. The cathode includes a central region defined by a first longitudinal axis and a second longitudinal axis extending respectively from the first edge and the second edge. The first cathode connector and the second cathode connector are equidistant respectively to the fuse link, the first cathode connector does not intersect the first longitudinal axis, and the second cathode connector does not intersect the second longitudinal axis, such that the central region is free of the first cathode connector and the second cathode connector.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shien-Yang Wu, Wei-Chang Kung
  • Patent number: 11276819
    Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu
  • Patent number: 11276644
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Patent number: 11271034
    Abstract: A method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the magnetic tunnel junction (MTJ) element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 8, 2022
    Inventor: Yimin Guo
  • Patent number: 11243573
    Abstract: A semiconductor package includes a flexible substrate and a semiconductor device. The flexible substrate includes a device bonding region and a device top metallization structure including a plurality of device signal lines and a plurality of device power lines extended beyond the device bonding region. The semiconductor device is disposed on the device bonding region and includes an interconnecting metallization structure and a passivation layer covering the interconnecting metallization structure and revealing a plurality of interconnect contacts of the interconnecting metallization structure, wherein the plurality of interconnect contacts electrically connected to one another through the device top metallization structure.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tung Hsu, Chang-Cheng Hung, Tyrone Kuo
  • Patent number: 11239162
    Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ? of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ? of the width of the top surface of the via.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Miji Lee, Taeyoung Jeong, Yoonkyeong Jo, Sangwoo Pae, Hwasung Rhee
  • Patent number: 11239420
    Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 1, 2022
    Assignee: Lam Research Corporation
    Inventors: James Samuel Sims, Andrew John McKerrow, Meihua Shen, Thorsten Lill, Shane Tang, Kathryn Merced Kelchner, John Hoang, Alexander Dulkin, Danna Qian, Vikrant Rai
  • Patent number: 11177163
    Abstract: Integrated circuits include back end of line metallization levels. An upper metallization level is on a lower metallization level and includes at least one top via-line interconnect structure in an interlayer dielectric. The lower metallization level includes at least one top via-line interconnect structure in an interlayer dielectric, wherein the top via is raised relative to the interlayer dielectric in the lower metallization level. The line in the upper metallization level contacts a top surface and sidewall portions of the top via raised above the interlevel dielectric. Also described are methods for fabricating the same.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Motoyama, Chanro Park, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • Patent number: 11152457
    Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming a first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming a second dielectric layer on the cleaned upper surface of the first dielectric layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 19, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihide Komatsu, Takeshi Igarashi, Hiroyuki Oguri
  • Patent number: 11133249
    Abstract: A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeonggil Kim, Jongmin Baek, Wookyung You, Kyuhee Han
  • Patent number: 11124664
    Abstract: The problem to be solved by the present invention is to provide an ink that can be used f producing a print having no streaks even in a case where the distance between the surface of a recording medium such as a cardboard and an ink jet head is long. The present invention relates to an ink for use in an ink jet recording method in which the distance from a surface (x) having an ink discharge port of an ink jet head to a position (y) where a line perpendicular to the surface (x) intersects with a recording medium is 2 mm or more, the ink having a viscosity in the range of 2 mPa·s or more and less than 9 mPa·s and a surface tension in the range of 20 mN/m to 40 mN/m.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 21, 2021
    Assignee: DIC CORPORATION
    Inventors: Takahiro Nio, Maiko Kitade, Yuri Shouji, Masaki Hosaka, Saki Fukui
  • Patent number: 11121137
    Abstract: The present application discloses a semiconductor device with a self-aligned landing pad and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a self-aligned landing pad disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The self-aligned landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: September 14, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Te-Yin Chen
  • Patent number: 11094581
    Abstract: Provided is an integrated circuit structure and a method for manufacturing the same. The integrated circuit structure comprises a substrate; a plurality of interconnecting structures on the substrate, each of the interconnecting structures comprises side surfaces and a top surface, the side surfaces directly define air gaps therebetween isolating the interconnecting structures from each other; and a planar protective layer on top of the plurality of interconnecting structures covering all of the air gaps. The protective layer comprises a sheltering film and a supporting film.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 17, 2021
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Salahuddin Raju, Man Sun John Chan, Clarissa Cyrilla Prawoto
  • Patent number: 11092862
    Abstract: An electro-optical device includes a pixel electrode that is light-transmissive, a substrate that is light-transmissive and that is provided with a recessed portion open to the pixel electrode side, a light-shielding body disposed in the recessed portion, and a switching element overlapping, in a plan view from a thickness direction of the substrate, the light-shielding body, the switching element being electrically coupled to the pixel electrode, wherein the light-shielding body includes a metal film containing tungsten, and a metal nitride film that is disposed between the metal film and the substrate and that contains tungsten nitride.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 17, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 11049770
    Abstract: Methods and apparatus for forming an interconnect structure, including: depositing a plurality of spacers atop a low-k dielectric layer including a plurality of recessed vias, wherein one or more of the plurality of spacers is deposited atop the top surface of the low-k dielectric layer and within one or more of the plurality of recessed vias to form a one or more partially filled recessed vias; depositing a conformal metal layer atop the low-k dielectric layer, plurality of spacers, and within the one or more partially filled recessed vias to form a plurality of filled vias; etching the conformal metal layer to remove portions thereof to form a second plurality of partially filled recessed vias; and filling between the plurality spacers and within the second plurality of partially filled recessed vias with a dielectric material to form a second plurality of filled vias.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: June 29, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Suketu A. Parikh
  • Patent number: 11049719
    Abstract: In one implementation, a processing system includes a first transfer chamber coupling to at least one epitaxy process chamber, a second transfer chamber, a transition station disposed between the first transfer chamber and the second transfer chamber, a first plasma chamber coupled to the second transfer chamber for removing oxides from a surface of a substrate, and a load lock chamber coupled to the second transfer chamber. The transition station connects to the first transfer chamber and the second transfer chamber, and the transition station includes a second plasma chamber for removing contaminants from the surface of the substrate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lara Hawrylchak, Kin Pong Lo, Errol C. Sanchez, Schubert S. Chu, Tushar Mandrekar
  • Patent number: 11037799
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Patent number: 11031542
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel Charles Edelstein, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 11010533
    Abstract: Disclosed is a computer-readable medium including a program code. The program code, when executed by a processor, causes the processor to place an electrically active pattern having a first width and a first least margin area, on a layer, to place a first dummy pattern having a second width wider than the first width and having a second least margin area, on the layer, and to place a second dummy pattern having a third width and a third least margin area, on the layer, based on whether a ratio of an area of the layer to areas of the electrically active pattern and the first dummy pattern is within a reference range.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jinyoung Park
  • Patent number: 10998293
    Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Ching-Jung Yang
  • Patent number: 10991599
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus
  • Patent number: 10971396
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin