Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization) Patents (Class 438/622)
  • Patent number: 11495658
    Abstract: An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: November 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield
  • Patent number: 11462497
    Abstract: A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: October 4, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Patent number: 11440002
    Abstract: Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua T. Smith, Robert Bruce, Jyotica V. Patel, Benjamin Wunsch
  • Patent number: 11393756
    Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Christian George Emor, Luca Fumagalli, John D. Hopkins, Rita J. Klein, Christopher W. Petz, Everett A. McTeer
  • Patent number: 11380547
    Abstract: A plasma processing method of etching an organic film through a mask having an opening is provided. The mask is formed on the organic film, and is made of a silicon-containing film. The method includes rectifying a shape of the mask. The rectifying of the shape of the mask includes refining a side wall of the opening of the mask, and etching an upper surface of the mask.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 5, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Ryo Terashima, Yuzuru Sakai
  • Patent number: 11372305
    Abstract: The present invention is directed to an electrophoretic display device comprising microcells filled with an electrophoretic fluid and a dielectric layer, which comprises a first type of magnetic filler material, a second type of nonmagnetic filler material, and a polymeric material. The first and second types of filler material physically interact with each other and they are fixed and aligned in the dielectric adhesive layer in a direction perpendicular to a plane of the dielectric layer. The dielectric layer exhibits anisotropic conductivity having higher conductivity in the z direction compared to the other two orthogonal directions.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 28, 2022
    Assignee: E INK CALIFORNIA, LLC
    Inventors: Craig Lin, Yu Li, Peter B. Laxton, Lei Liu, Hui Du, HongMei Zang
  • Patent number: 11361993
    Abstract: A process flow is utilized for patterning of dual damascene structures in BEOL process steps. Conductor vias are inversely patterned in the form of pillars that are formed before the final dielectric stack is deposited. The final dielectric stack may include a low-k dielectric and the conductor may be ruthenium. The vias may be formed by forming conductor pillars in patterned voids of a sacrificial layer. After the pillars are formed, certain areas between the pillars can then be backfilled with a dielectric, such as for example, a low-k dielectric material. The trench conductor of the dual damascene structure may then be formed. The sacrificial dielectric may then be removed and an additional layer of low-k dielectric material can then be deposited or coated on the structure to provide the final structure having the dual damascene vias and trenches filled with the conductor surrounded by low-k material.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 14, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Angelique D. Raley, Katie Lutker-Lee
  • Patent number: 11342261
    Abstract: Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 24, 2022
    Assignee: IMEC VZW
    Inventors: Stefan Cosemans, Julien Ryckaert, Zsolt Tokei
  • Patent number: 11328992
    Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Nicholas James Harold McKubre, Richard Farrington Vreeland, Sansaptak Dasgupta
  • Patent number: 11309244
    Abstract: An exemplary method includes forming a fuse structure and forming a first cathode connector and a second cathode connector over the fuse structure. The fuse structure includes an anode, a cathode, and a fuse link extending between and connecting the anode and the cathode. The fuse link has a width defined between a first edge and a second edge, which extend a length of the fuse link. The cathode includes a central region defined by a first longitudinal axis and a second longitudinal axis extending respectively from the first edge and the second edge. The first cathode connector and the second cathode connector are equidistant respectively to the fuse link, the first cathode connector does not intersect the first longitudinal axis, and the second cathode connector does not intersect the second longitudinal axis, such that the central region is free of the first cathode connector and the second cathode connector.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shien-Yang Wu, Wei-Chang Kung
  • Patent number: 11276644
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Patent number: 11276819
    Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu
  • Patent number: 11271034
    Abstract: A method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the magnetic tunnel junction (MTJ) element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 8, 2022
    Inventor: Yimin Guo
  • Patent number: 11243573
    Abstract: A semiconductor package includes a flexible substrate and a semiconductor device. The flexible substrate includes a device bonding region and a device top metallization structure including a plurality of device signal lines and a plurality of device power lines extended beyond the device bonding region. The semiconductor device is disposed on the device bonding region and includes an interconnecting metallization structure and a passivation layer covering the interconnecting metallization structure and revealing a plurality of interconnect contacts of the interconnecting metallization structure, wherein the plurality of interconnect contacts electrically connected to one another through the device top metallization structure.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Tung Hsu, Chang-Cheng Hung, Tyrone Kuo
  • Patent number: 11239420
    Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 1, 2022
    Assignee: Lam Research Corporation
    Inventors: James Samuel Sims, Andrew John McKerrow, Meihua Shen, Thorsten Lill, Shane Tang, Kathryn Merced Kelchner, John Hoang, Alexander Dulkin, Danna Qian, Vikrant Rai
  • Patent number: 11239162
    Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ? of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ? of the width of the top surface of the via.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Miji Lee, Taeyoung Jeong, Yoonkyeong Jo, Sangwoo Pae, Hwasung Rhee
  • Patent number: 11177163
    Abstract: Integrated circuits include back end of line metallization levels. An upper metallization level is on a lower metallization level and includes at least one top via-line interconnect structure in an interlayer dielectric. The lower metallization level includes at least one top via-line interconnect structure in an interlayer dielectric, wherein the top via is raised relative to the interlayer dielectric in the lower metallization level. The line in the upper metallization level contacts a top surface and sidewall portions of the top via raised above the interlevel dielectric. Also described are methods for fabricating the same.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Motoyama, Chanro Park, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • Patent number: 11152457
    Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming a first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming a second dielectric layer on the cleaned upper surface of the first dielectric layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 19, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihide Komatsu, Takeshi Igarashi, Hiroyuki Oguri
  • Patent number: 11133249
    Abstract: A semiconductor device includes a contact structure connected to an active region. A first insulating layer is disposed on a barrier dielectric layer and has a first hole connected to the contact structure. A second insulating layer is disposed on the first insulating layer and has a trench connected to the first hole. The second insulating layer has an extended portion along a side wall of the first hole. A width of the first hole less the space occupied by the extended portion is defined as a second hole. A wiring structure including a conductive material is connected to the contact structure. A conductive barrier is disposed between the conductive material and the first and second insulating layers. An etch stop layer is disposed between the first and second insulating layers and between the extended portion of the second insulating layer and a side wall of the first hole.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeonggil Kim, Jongmin Baek, Wookyung You, Kyuhee Han
  • Patent number: 11124664
    Abstract: The problem to be solved by the present invention is to provide an ink that can be used f producing a print having no streaks even in a case where the distance between the surface of a recording medium such as a cardboard and an ink jet head is long. The present invention relates to an ink for use in an ink jet recording method in which the distance from a surface (x) having an ink discharge port of an ink jet head to a position (y) where a line perpendicular to the surface (x) intersects with a recording medium is 2 mm or more, the ink having a viscosity in the range of 2 mPa·s or more and less than 9 mPa·s and a surface tension in the range of 20 mN/m to 40 mN/m.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 21, 2021
    Assignee: DIC CORPORATION
    Inventors: Takahiro Nio, Maiko Kitade, Yuri Shouji, Masaki Hosaka, Saki Fukui
  • Patent number: 11121137
    Abstract: The present application discloses a semiconductor device with a self-aligned landing pad and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a self-aligned landing pad disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a liner layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The self-aligned landing pad comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: September 14, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Te-Yin Chen
  • Patent number: 11094581
    Abstract: Provided is an integrated circuit structure and a method for manufacturing the same. The integrated circuit structure comprises a substrate; a plurality of interconnecting structures on the substrate, each of the interconnecting structures comprises side surfaces and a top surface, the side surfaces directly define air gaps therebetween isolating the interconnecting structures from each other; and a planar protective layer on top of the plurality of interconnecting structures covering all of the air gaps. The protective layer comprises a sheltering film and a supporting film.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: August 17, 2021
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Salahuddin Raju, Man Sun John Chan, Clarissa Cyrilla Prawoto
  • Patent number: 11092862
    Abstract: An electro-optical device includes a pixel electrode that is light-transmissive, a substrate that is light-transmissive and that is provided with a recessed portion open to the pixel electrode side, a light-shielding body disposed in the recessed portion, and a switching element overlapping, in a plan view from a thickness direction of the substrate, the light-shielding body, the switching element being electrically coupled to the pixel electrode, wherein the light-shielding body includes a metal film containing tungsten, and a metal nitride film that is disposed between the metal film and the substrate and that contains tungsten nitride.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 17, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Satoshi Ito
  • Patent number: 11049770
    Abstract: Methods and apparatus for forming an interconnect structure, including: depositing a plurality of spacers atop a low-k dielectric layer including a plurality of recessed vias, wherein one or more of the plurality of spacers is deposited atop the top surface of the low-k dielectric layer and within one or more of the plurality of recessed vias to form a one or more partially filled recessed vias; depositing a conformal metal layer atop the low-k dielectric layer, plurality of spacers, and within the one or more partially filled recessed vias to form a plurality of filled vias; etching the conformal metal layer to remove portions thereof to form a second plurality of partially filled recessed vias; and filling between the plurality spacers and within the second plurality of partially filled recessed vias with a dielectric material to form a second plurality of filled vias.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: June 29, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Suketu A. Parikh
  • Patent number: 11049719
    Abstract: In one implementation, a processing system includes a first transfer chamber coupling to at least one epitaxy process chamber, a second transfer chamber, a transition station disposed between the first transfer chamber and the second transfer chamber, a first plasma chamber coupled to the second transfer chamber for removing oxides from a surface of a substrate, and a load lock chamber coupled to the second transfer chamber. The transition station connects to the first transfer chamber and the second transfer chamber, and the transition station includes a second plasma chamber for removing contaminants from the surface of the substrate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lara Hawrylchak, Kin Pong Lo, Errol C. Sanchez, Schubert S. Chu, Tushar Mandrekar
  • Patent number: 11037799
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Kei-Wei Chen, Liang-Guang Chen, Te-Ming Kung, William Weilun Hong, Chi-Hsiang Shen, Chia-Wei Ho, Chun-Wei Hsu, Yang-Chun Cheng
  • Patent number: 11031542
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel Charles Edelstein, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 11010533
    Abstract: Disclosed is a computer-readable medium including a program code. The program code, when executed by a processor, causes the processor to place an electrically active pattern having a first width and a first least margin area, on a layer, to place a first dummy pattern having a second width wider than the first width and having a second least margin area, on the layer, and to place a second dummy pattern having a third width and a third least margin area, on the layer, based on whether a ratio of an area of the layer to areas of the electrically active pattern and the first dummy pattern is within a reference range.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jinyoung Park
  • Patent number: 10998293
    Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Ching-Jung Yang
  • Patent number: 10991599
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus
  • Patent number: 10971396
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 10964789
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hong-Shyang Wu, Kuo-Ming Wu
  • Patent number: 10950523
    Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Wan Kim, Jung-Hoon Han, Dong-Sik Park
  • Patent number: 10943939
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 9, 2021
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Patent number: 10910498
    Abstract: An array substrate, a method for fabricating the same and a display device are disclosed. The method for fabricating the array substrate includes: forming a pattern of a gate electrode, a pattern of a gate insulation layer and a pattern of a metal oxide semiconductor active layer on a base substrate; forming an etch stop layer; forming a pattern of a pixel electrode first, and then forming a pattern of a source electrode and a pattern of a drain electrode; wherein the pattern of the pixel electrode is connected to the pattern of the metal oxide semiconductor active layer through the pattern of the source electrode or the pattern of the drain electrode. The method can prevent the problem that the pattern of the pixel electrode failing to connect to the pattern of the source electrode or the pattern of the drain electrode.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: February 2, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Zhanfeng Cao, Feng Zhang, Qi Yao
  • Patent number: 10892217
    Abstract: A wiring substrate includes first wiring portions, an insulation layer covering the first wiring portions, openings extending through the insulation layer in a thickness-wise direction, partially exposing upper surfaces of the first wiring portions, and differing from each other in capacity, and second wiring portions, each of which includes a via wiring filling one of the openings and a columnar connection terminal electrically connected to the via wiring and arranged on an upper surface of the insulation layer. The via wiring includes an electrolytic plated layer and an electroless plating structure including N layers (N is integer and ?0) arranged between the electrolytic plated layer and the upper surface of the first wiring portion exposed in a bottom of the opening. The via wiring is formed so that the electroless plating structure has a thickness that increases as a capacity of the opening filled with the via wiring is increased.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 12, 2021
    Inventors: Takashi Arai, Fumimasa Katagiri, Katsuya Fukase
  • Patent number: 10879081
    Abstract: Methods and apparatus for reducing and eliminating defects in tungsten film are disclosed herein. In the present disclosure, reducing or eliminating oxidation of a first surface of a tungsten film having a predetermined first thickness disposed upon a substrate and within a plurality of trenches is disclosed. The plurality of trenches include a predetermined depth, and a width of less than 20 nanometers. The predetermined first thickness of the tungsten film is substantially uniform throughout the plurality of trenches such that the predetermined first thickness of the tungsten film does not substantially change to a second thickness when the first surface is contacted with air or oxygen.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 29, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Guoqiang Jian, Wei Tang, Chi-Chou Lin, Paul F. Ma, Kai Wu, Vikash Banthia, Mei Chang, Jia Ye, Wenyu Zhang, Jing Zhou
  • Patent number: 10874016
    Abstract: A method for fabricating a sandwiched structure of silver-copper-silver functioning as a high frequency signal transmission structure includes an insulating sheet and a conductive circuit on the insulating sheet. The conductive circuit includes a silver conductive layer bonded to the insulating sheet, a copper conductive layer formed on the silver conductive layer, and a silver covering layer laid to cover top and side surfaces of the copper conductive layer. The silver conductive layer and the silver covering layer together enclose the copper conductive layer and the higher conductivity of the silver together with the skin effect improves high-frequency transmission efficiency of the copper.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 22, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Ming-Jaan Ho, Hsiao-Ting Hsu
  • Patent number: 10861705
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Patent number: 10833022
    Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cung D. Tran, Huaxiang Li, Bradley Morgenfeld, Xintuo Dai, Sanggil Bae, Rui Chen, Md Motasim Bellah, Dongyue Yang, Minghao Tang, Christian J. Ayala, Ravi Prakash Srivastava, Kripa Nidhan Chauhan, Pavan Kumar Chinthamanipeta Sripadarao
  • Patent number: 10832953
    Abstract: Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 10, 2020
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Matthias Wietstruck, Mehmet Kaynak, Philip Kulse, Marco Lisker, Steffen Marschmeyer, Dirk Wolansky
  • Patent number: 10813231
    Abstract: The present disclosure relates to a method for manufacturing a circuit board. The method for manufacturing the circuit board includes forming a patterned first dielectric layer on a substrate; forming an adhesive layer on the patterned first dielectric layer; forming a second dielectric layer on the adhesive layer; and patterning the second dielectric layer and the adhesive layer.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 20, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Po-Hsuan Liao, Wen-Fang Liu
  • Patent number: 10796949
    Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
  • Patent number: 10720385
    Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. A first metal region is formed within a first dielectric region. A cap region is formed on the first metal region. A second dielectric region is formed above the cap region and the first dielectric region. A trench opening is formed within the second dielectric region. A via opening is formed through the second dielectric region, the cap region, and within some of the first metal region by over etching. A barrier region is formed within the trench opening and the via opening. A via plug is formed within the via opening and a second metal region is formed within the trench opening. The via plug electrically connects the first metal region to the second metal region and has a tapered profile.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 10707120
    Abstract: An RF SOI device combines a triple-layer stressing stack and patterned low-k features (i.e., low-k polymer structures and/or air gap regions) disposed in pre-metal dielectric over the gate structures of NMOS transistors. The triple-layer stressing stack includes a thick SiN or oxynitride lower stressor layer that applies tensile stress in the channel regions of the NMOS transistors, a thin intermediate buffer layer, an upper etch-stop layer. After Metal-1 processing is completed, a special etching process is performed to define air gaps in the pre-metal dielectric over the NMOS gate structures using upper layer(s) of the triple-layer stressing stack as an etch stop to prevent damage to the stressor layer. A non-conformal dielectric material or an optional low-k dielectric material is then deposited in or over the air gaps to complete formation of the low-k features, and an optional capping or sealing layer is formed over the completed low-k features.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: July 7, 2020
    Assignee: Tower Semiconductor Ltd.
    Inventors: Bouhnik Yami, Nagar Magi, Barhum Liat, Alexey Heiman, Yakov Roizin
  • Patent number: 10686011
    Abstract: A semiconductor device integrated with memory device includes a substrate, having a first side and a second side. A transistor circuit layer is disposed over the substrate at the first side. An interconnect structure layer is disposed over the transistor circuit layer with electric connection to form a circuit route. A memory cell layer is disposed over the interconnect structure layer or over a second side of the substrate, in connection to the circuit route. The memory cell layer includes a plurality of memory cells, and a cell structure of the memory cells includes an oxide semiconductor field effect transistor and a memory element.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 16, 2020
    Assignee: United Microelectronics Corp.
    Inventor: Zhi-Biao Zhou
  • Patent number: 10665474
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 10637105
    Abstract: A battery embedded structure is disclosed. The battery embedded structure comprises a substrate including one or more stacked battery units. Each stacked battery unit includes two or more conductive layers and one or more unit cells. Each unit cell is disposed between two conductive layers. The substrate has a principal surface provided by one or more respective side surfaces of the one or more stacked battery units. The battery embedded structure also comprises a wiring layer disposed on the principal surface of the substrate. The wiring layer includes a plurality of electrical paths and a plurality of vias. Each via is connected with one electrical path. Each via is located at a position corresponding to an edge surface of a conductive layer of the two or more conductive layers of the one or more stacked battery units so as to contact electrically to that conductive layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keiji Matsumoto, Hiroyuki Mori
  • Patent number: 10596626
    Abstract: An additive manufacturing system including a two-dimensional energy patterning system for imaging a powder bed is disclosed. Improved structure formation, part creation and manipulation, use of multiple additive manufacturing systems, and high throughput manufacturing methods suitable for automated or semi-automated factories are also disclosed.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: March 24, 2020
    Assignee: SEURAT TECHNOLOGIES, INC.
    Inventors: James A. DeMuth, Erik Toomre, Francis L. Leard, Kourosh Kamshad, Heiner Fees, Eugene Berdichevsky
  • Patent number: 10580721
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first conductive layer covering a part of the first main surface; a through electrode connected to the first conductive layer and having a first conductive plated layer and a second conductive plated layer; and a second conductive layer formed on the second main surface. The first conductive plated layer contacts with the semiconductor substrate through a seed layer. The second conductive plated layer is formed on the first conductive plated layer. The second conductive layer is formed of the seed layer, the first conductive plated layer, and the second conductive plated layer. The first conductive plated layer has a first edge surface. The second conductive plated layer has a second edge surface flush with the first edge surface.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: March 3, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akihiko Nomura