SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.
1. Field of the Invention
The present invention relates generally to the field of a semiconductor device, and more particularly to a non-planar semiconductor device with fin structures and a fabrication method thereof.
2. Description of the Prior Art
With the trend in the industry of scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology such as fin field effect transistor technology (Fin FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, so that the channel region is more effectively controlled. The drain-induced barrier lowering (DIBL) effect and short channel effect (SCE) are therefore reduced. The channel region is also longer under the same gate length, which increases the current between the source and the drain.
In order to further improve the device's performance, a strained-silicon technology has also been developed. The main principle is that strains are applied to predetermined regions within the semiconductor device, which in turn make the semiconductor device work better by enabling charge carriers, such as electrons or holes, to pass through the lattice of the channel more easily. One main technology disposes epitaxial structures with lattice constants different from that of the crystal silicon in the source/drain regions of the semiconductor devices. The epitaxial structures are preferably composed of silicon germanium (SiGe) or carbon-doped silicon (SiC), which have lattice constants different from that of the crystal silicon. Since the epitaxial structures have lattice constants which are larger or smaller than that of the crystal silicon, carrier channel regions adjacent to the epitaxial structures can sense external stress, and both the lattice structure and the band structure within these regions are thereby altered. As a result, the carrier mobility and the performances of the corresponding semiconductor devices are improved.
With the continued decrease in the size and dimensions of semiconductor devices, however, there are newly generated technological problems that need to be overcome, even with the adoption of the non-planar transistor with raised source/drain regions. How to effectively eliminate these defects and improve the performance of the semiconductor devices are important issues in this field.
SUMMARY OF THE INVENTIONIn light of the above, the embodiments of the present invention disclose a semiconductor device and a method for fabrication to overcome the above-mentioned drawbacks.
A semiconductor device is disclosed according to one embodiment of the present invention. The semiconductor device comprises a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, wherein the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.
A method for fabricating a semiconductor device is disclosed according to another embodiment of the present invention. The method may be applied to a semi-finished semiconductor device comprising a substrate, a fin structure, and an insulating structure. Both the fin structure and the insulating structure are disposed on the substrate. The method comprises the following steps: etching a top surface of the fin structure; and growing an epitaxial layer with a curved top surface merely on the top surface of the fin structure after the step of etching the top surface of the fin structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. It will, however, be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. Furthermore, some well-known system configurations and process steps are not disclosed in detail.
The drawings showing embodiments of the apparatus are not to scale and some dimensions are exaggerated for clarity of presentation. Also, where multiple embodiments are disclosed and described as having some features in common, like or similar features will usually be described with same reference numerals for ease of illustration and description thereof.
The substrate 10 may have a main surface 10a with a predetermined crystal surface, and the long axis of the fin structure 13 is parallel to a predetermined crystal orientation. For example, for a bulk silicon substrate, the main surface 10a as well as the top surfaces of the fin structures 13 may all have specific crystal surfaces, such as (100) crystal surfaces, and the long axis of the fin structures 13 may be parallel to a specific crystal orientation, such a (110) crystal orientation, but is not limited thereto. The gate structure 14 may cross over the fin structures 40 and the epitaxial structures 40 so that the source regions 16 and the drain regions 18 may be respectively disposed on either side of the gate structure 14. For example, the source/drain regions may be disposed inside the epitaxial structures 40 on two sides of the gate structure 14 or inside other epitaxial structures overlaying the epitaxial structures 40. The metal contact structures 20, respectively electrically connected to the source regions 16 and the drain regions 18, may be used as a current passage between the source regions 16 and the drain regions 18. In addition, an optional metal contact structure electrically connected to the gate structure 14 may be used to receive an external voltage, which is used to turn on or turn off the carrier channel beneath the gate structure 14.
One feature of the present embodiment is that, when the semiconductor device 100 is in an on-state, an overlapped region in the epitaxial structures and between the epitaxial structures and the gate structure 14 may be used as a main current path. Because of the curved top surface 401 of the epitaxial structure 14, the electric field induced by the gate structure may be uniformly distributed on the curved top surface 401. In this way, the electric field may not be accumulated in a certain region of the epitaxial structures 40, and the electrical properties of the semiconductor device 100 may be enhanced. In addition, because the epitaxial structures 40 with the curved top surface 401 replace top portions of the original fin structures, a widened carrier channel may be obtained compared with a semiconductor device without the epitaxial structures 40 with the curved top surface. Furthermore, because the lattice constant of the epitaxial structures 40 differ from that of the underneath fin structures, the epitaxial structures 40 disclosed in this embodiment may also provide a carrier channel with better carrier mobility compared with fin structures without the epitaxial structures.
The structure of the semiconductor device shown in
The gate structure 14 is disposed in the dielectric layer 32 and the lateral boundaries of the gate structure 14 are defined by spacers 34. In detail, the gate structure 14 is a metal gate structure which includes at least a gate dielectric 141, a work function layer 142, a gate electrode 143, and an optional cap layer 144 sequentially stacked from bottom to top. The gate dielectric 141 conformally covers both the fin structures 13 and the epitaxial structures 40, and the cap layer 144 concurrently covers the gate dielectric 141, the work function layer 142 and the gate electrode 143.
Each of the spacers 34 may have a single-layered structure or have a double or multi-layered structure. For example, the spacer 34 may be a double-layered structure which includes an L-shaped lower spacer 341 and an upper spacer 342 sequentially stacked from its bottom to its top. The gate dielectric 141 is preferably a high-k dielectric layer with a dielectric constant substantially greater than 20. As an example, the gate dielectric 141 may be selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), and barium strontium titanate (BaxSr1-xTiO3, BST), but is not limited thereto. The gate electrode 143 may include metal or metal oxide with superior filling ability and relatively low resistance, such as aluminum (Al), titanium aluminum (TiAl), titanium aluminum oxide (TiAlO), tungsten (W) or copper (Cu), but is not limited thereto. The cap layer 144 may be made of silicon nitride, silicon carbide, silicon oxynitride, silicon carbon nitride, and/or other suitable materials. The cap layer 144 may prevent a self-aligned contact formed in the following processes from electrically connecting to the gate electrode 143.
When the carrier channel of the semiconductor device 100 is switched to an on-state, the carriers may mainly flow between the source region 16 and the drain region 18 via a main current path 42 in an upper portion of the epitaxial structure 40. Because most of the carriers move via the main current path 42, the current density of the upper epitaxial structure 40 may be higher than that of the lower epitaxial structure 40. Even if the entire height of the epitaxial structure 13 is not high enough, the electrical properties of the semiconductor device 100 may still be good. For instance, the height H1 of the epitaxial structure 40 may be less than the height H2 of the fin structure 13. In a case where the fin structure 13 and the epitaxial structure 40 have a total height HT, the ratio of the height H1 of the epitaxial structure 40 to the total height HT is preferably less than 0.5. In addition, because the epitaxial structure 40 and the gate dielectric 141 together include three contact surfaces, the semiconductor device 100 may also be called a tri-gate MOSFET.
As mentioned above, the substrate 10 may be a bulk silicon substrate. Therefore, the protruding contour of the protruding structures 13 may be formed by etching the silicon substrate. The substrate 10 may also be chosen from other substrates, such as a silicon-on-insulator (SOI) substrate, and the semiconductor device 100 using the SOI substrate is shown in
In addition to the bulk silicon substrate and the silicon-on-insulator (SOI) substrate disclosed in the first and second embodiments, the substrate may also be chosen from a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate and a silicon-on-insulator (SOI) substrate, but is not limited thereto.
A method for fabricating the semiconductor device above is disclosed in the following paragraphs.
In the preceding paragraphs, the step of performing the epitaxial growth process is performed prior to the step of forming the dummy gate structure. In another embodiment, however, the step of performing the epitaxial growth process may also be performed later than the step of forming the dummy gate structure. This embodiment is disclosed in the following paragraphs.
As in the previous embodiment, additional epitaxial structures may be further formed on the fin structure 13 exposed by the dummy gate structure 60 by performing an epitaxial growth process. These additional epitaxial structures may apply compressive stress or tensile stress to the adjacent channel region to increase the carrier mobility. Afterwards, through a deposition process and a planarization process, a dielectric layer 32 surrounding the dummy gate structure 60 and the spacer 34 may be formed.
The dummy gate structure 60 is removed to leave a gate trench in the dielectric layer 32. In this way, the fin structure 13 may be exposed by the gate trench.
The remaining replacement metal gate process may then be performed, and a metal gate structure similar to that shown in
The preceding first and second embodiments disclose methods for fabricating semiconductor devices; however, the present invention also includes other methods for fabricating semiconductor devices. In the following paragraphs, a third embodiment which incorporates the first embodiment and the second embodiment is disclosed.
According to the third embodiment of the present invention, and taking the structure shown in
Then, the dummy gate structure 60 is removed to leave a gate trench 62 in the dielectric layer 32.
As shown in
The remaining replacement metal gate process may then be performed. After the replacement metal gate process, an optional inter-metal dielectric layer and an optional self-aligned contact etc. may be further formed to obtain the desired semiconductor device. These structures and processes are omitted for brevity.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A semiconductor device, comprising:
- a fin structure, disposed on a substrate;
- an insulating structure, disposed on the substrate;
- a protruding structure, in direct contact with the substrate and partially protruding from the insulating structure, wherein portions of the protruding structure protruding from the insulating structure is the fin structure;
- an epitaxial structure, disposed on a top surface of the fin structure and completely covering the top surface of the fin structure, wherein the epitaxial structure has a curved top surface, and a bottom surface of the epitaxial structure is disposed only on a top surface of the fin structure; and
- a gate structure, covering the fin structure and the epitaxial structure.
2. (canceled)
3. The semiconductor device according to claim 1, wherein the fin structure and the epitaxial structure have a total height, and a ratio of the height of the epitaxial structure to the total height is less than 0.5.
4. The semiconductor device according to claim 1, wherein the width of the epitaxial structure is gradually reduced from a location close to the fin structure to a location away from the fin structure.
5. The semiconductor device according to claim 1, wherein the top surface of the fin structure has a (100) crystal surface.
6. (canceled)
7. (canceled)
8. The semiconductor device according to claim 1, further comprising:
- a source region and a drain region, respectively disposed in the epitaxial structure on two sides of the gate structure; and
- a plurality of metal contact structures, respectively electrically connected to the source region, the drain region, and the gate structure, wherein a main current path is generated in an upper portion of the epitaxial structure when a voltage is applied to the source region, the drain region, and/or the gate structure.
9. (canceled)
10. The semiconductor device according to claim 8,
- wherein a current density in the upper portion of the epitaxial structure is higher than a current density in a lower portion of the epitaxial structure.
11. A method for fabricating a semiconductor device,
- wherein the method is applied to a semi-finished semiconductor device comprising a substrate, a fin structure, and an insulating structure, wherein both the fin structure and the insulating structure are disposed on the substrate, the method comprising:
- etching a top surface of the fin structure; and
- growing an epitaxial layer on the top surface of the fin structure after the step of etching the top surface of the fin structure, wherein the epitaxial layer has a curved top surface, and a bottom surface of the epitaxial structure is disposed only on the top surface of the fin structure.
12. The method according to claim 11, wherein the top surface of the fin structure is reduced from an initial height to a reduced height when the step of etching the top surface of the fin structure is completed.
13. The method according to claim 12, wherein the top surface of the epitaxial structure is at the initial height when the step of growing the epitaxial structure is completed.
14. (canceled)
15. (canceled)
16. The method according to claim 11, wherein the fin structure and the epitaxial structure have a total height, and a ratio of the height of the epitaxial structure to the total height is less than 0.5.
17. The method according to claim 11, further comprising performing a plasma treatment and a thermal treatment to round the epitaxial structure.
18. The method according to claim 11, further comprising forming a dummy gate structure covering the epitaxial structure and the fin structure after the step of growing the epitaxial structure.
19. The method according to claim 11, wherein the semi-finished semiconductor device further comprises a dummy gate structure covering the fin structure and disposed in a gate trench before the step of etching the top surface of the fin structure, the method further comprising:
- removing the dummy gate structure until the fin structure is exposed from the gate trench: and
- forming a metal gate structure covering the epitaxial structure and the fin structure.
20. The semiconductor device of claim 1, wherein the epitaxial structure has a curved top surface.
21. The semiconductor device of claim 1, wherein the width of the epitaxial structure is gradually reduced from the bottom surface of the epitaxial structure to a top surface of the epitaxial structure.
22. The semiconductor device of claim 1, wherein the gate structure covers portions of the fin structure and portions of the epitaxial structure, and the epitaxial structure covered by the gate structure and the epitaxial structure exposed from the gate structure are made of different materials.
23. The semiconductor device of claim 1, wherein the bottom of the epitaxial structure is higher than the top of the insulating structure.
24. The method of claim 11, wherein the width of the epitaxial structure is gradually reduced from the bottom surface of the epitaxial structure to a top surface of the epitaxial structure.
25. The method of claim 11, wherein the bottom of the epitaxial structure is higher than the top of the insulating structure.
Type: Application
Filed: Aug 20, 2014
Publication Date: Jan 21, 2016
Inventors: Yen-Liang Wu (Taipei City), Chung-Fu Chang (Tainan City), Yu-Hsiang Hung (Tainan City), Wen-Jiun Shen (Yunlin County), Ssu-I Fu (Kaohsiung City), Man-Ling Lu (Taoyuan County), Chia-Jong Liu (Ping-Tung County), Yi-Wei Chen (Taichung City)
Application Number: 14/463,676