SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
1. Field of the Invention
The present invention relates to a semiconductor device including an oxide semiconductor, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Various metal oxides are used for a variety of applications. Indium oxide is a well-known material and is used as a transparent electrode material which is necessary for liquid crystal displays and the like.
Some metal oxides have semiconductor characteristics. Metal oxides having semiconductor characteristics are a kind of compound semiconductor. The compound semiconductor is a semiconductor formed using two or more kinds of atoms bonded together. In general, metal oxides become insulators. However, it is known that metal oxides become semiconductors depending on the combination of elements included in the metal oxides.
For example, it is known that tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like are metal oxides which have semiconductor characteristics. A thin film transistor in which a transparent semiconductor layer which is formed using such a metal oxide serves as a channel formation region is disclosed (see Patent Documents 1 to 4 and Non-Patent Document 1).
Further, not only one-element oxides but also multi-element oxides are known as metal oxides. For example, InGaO3(ZnO)m (m is a natural number) which is a homologous compound is a known material (see Non-Patent Documents 2 to 4).
Furthermore, it is confirmed that such an In—Ga—Zn-based oxide is applicable to a channel layer of a thin film transistor (see Patent Document 5 and Non-Patent Documents 5 and 6).
REFERENCE Patent Documents
- [Patent Document 1] Japanese Published Patent Application No. S60-198861
- [Patent Document 2] Japanese Published Patent Application No. H8-264794
- [Patent Document 3] Japanese Translation of PCT International Application No. H11-505377
- [Patent Document 4] Japanese Published Patent Application No. 2000-150900
- [Patent Document 5] Japanese Published Patent Application No. 2004-103957
- [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, “A ferroelectric transparent thin-film transistor”, Appl. Phys. Lett., 17 Jun. 1996, Vol. 68, p. 3650-3652
- [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, “The Phase Relations in the In2O3—Ga2ZnO4—ZnO System at 1350° C.”, J. Solid State Chem., 1991, Vol. 93, p. 298-315
- [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m=3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m=7, 8, 9, and 16) in the In2O3—ZnGa2O4—ZnO System”, J. Solid State Chem., 1995, Vol. 116, p. 170-178
- [Non-Patent Document 4] M. Nakamura, N. Kimizuka, T. Mohri, and M. Isobe, “Syntheses and crystal structures of new homologous compounds, indium iron zinc oxides (InFeO3(ZnO)m) (m: natural number) and related compounds”, KOTAI BUTSURI (SOLID STATE PHYSICS), 1993, Vol. 28, No. 5, p. 317-327
- [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, “Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor”, SCIENCE, 2003, Vol. 300, p. 1269-1272
- [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors”, NATURE, 2004, Vol. 432, p. 488-492
An object of one embodiment of the present invention is to provide a display device provided with a thin film transistor having excellent electric characteristics and a pixel electrode layer, using an oxide semiconductor layer.
In order to obtain an amorphous oxide semiconductor layer, a thin film transistor is manufactured in which an In—Sn—O-based oxide semiconductor layer including silicon oxide or silicon oxynitride is used for a semiconductor layer including a channel formation region. Typically, the In—Sn—O-based oxide semiconductor layer is formed using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower to include SiOX (X>0) which interrupts crystallization, so that the thin film transistor is obtained, whose gate threshold voltage at which a channel is formed is positive and as close to 0V as possible.
Computation relating to electrical characteristics of a thin film transistor in which an In—Sn—O-based oxide semiconductor layer including SiOX was used as a semiconductor layer including a channel formation region was performed. A model of the computation and computation results are described below.
The computation was performed using Atlas produced by Silvaco Data Systems, Inc. The structure of a model of the computation is such an inverted staggered thin film transistor as illustrated in
The conductivity of the semiconductor layer 803 is, as shown in
As shown in
In addition, in order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a source and a drain electrode layers which are formed from a metal material having low electric resistance, a source region and a drain region are formed between the source and the drain electrode layers and the In—Sn—O-based oxide semiconductor layer including SiOX. One of the source region and the drain region is formed using the same layer as a pixel electrode region.
An In—Sn—O-based oxide semiconductor layer which does not include SiOX is used for the source region, the drain region, and the pixel electrode region.
As the material of the source electrode layer or drain electrode layer, an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy containing any of these elements as its component, an alloy containing a combination of any of these elements, or the like is used.
An embodiment disclosed in this specification is a semiconductor device including a gate electrode layer, a gate insulating layer, a first In—Sn—O-based oxide semiconductor layer including SiOX, a source region and a drain region which are in contact with the first In—Sn—O-based oxide semiconductor layer including SiOX, and a pixel electrode region. In this structure, the source region or the drain region and the pixel electrode region are formed from one layer that is a second In—Sn—O-based oxide semiconductor layer.
Another embodiment disclosed in this specification is a semiconductor device including a gate electrode layer over a substrate having an insulating surface, a gate insulating layer over the gate electrode layer, a first In—Sn—O-based oxide semiconductor layer including SiOX over the gate insulating layer, a source region and a drain region which are in contact with the first In—Sn—O-based oxide semiconductor layer including SiOX, and a pixel electrode region. In this structure, the source region or the drain region and the pixel electrode region are formed from one layer that is a second In—Sn—O-based oxide semiconductor layer.
In any of the above structures, conductivity of the first In—Sn—O-based oxide semiconductor layer including SiOX is less than or equal to 1.6×10−3 S/cm, or preferably less than or equal to 1.3×10−4 S/cm. Note that the first In—Sn—O-based oxide semiconductor layer including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower.
An embodiment of the present invention, which realizes the above structure, is a method of manufacturing a semiconductor device, in which a gate electrode layer is formed over a substrate having an insulating surface, a gate insulating layer is formed over the gate electrode layer, a first oxide semiconductor layer including SiOX is formed over the gate insulating layer by a sputtering method using a first In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, a source region, a drain region, and a pixel electrode region are formed over the first oxide semiconductor layer including SiOX by a sputtering method using a second In—Sn—O-based oxide semiconductor target, and the source region, the drain region, and the pixel electrode region are formed from one layer that is the second In—Sn—O-based oxide semiconductor layer.
There is no limitation on the structure of the thin film transistor, and a bottom-gate thin film transistor or a top-gate transistor can be employed.
In this specification, a semiconductor device refers to all types of devices which can function by using semiconductor characteristics. An electro-optical device, a semiconductor circuit, and an electronic device are included in the category of all semiconductor devices.
In addition, it is an object of an embodiment of the present invention to provide a semiconductor device provided with a highly reliable thin film transistor in which an oxide semiconductor layer is used.
FIGS. 11A1 and 11A2 and FIGS. 11B1 and 11B2 illustrate a semiconductor device;
FIGS. 22A1 and 22A2 and
Embodiments are described with reference to the drawings. However, it is easily understood by those skilled in the art that the modes and details herein disclosed can be modified in a variety of ways without departing from the scope and the spirit of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments below. In the structures to be given below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and explanation thereof will not be repeated.
Embodiment 1A semiconductor device and a method of manufacturing the semiconductor device will be described with reference to
An In—Sn—O-based oxide semiconductor layer including silicon oxide or silicon oxynitride is used for the semiconductor layer including a channel formation region. The conductivity of the In—Sn—O-based oxide semiconductor layer 403 including SiOX is preferably 1.6×10−3 S/cm or less, or more preferably 1.3×10−4 S/cm or less. Note that the In—Sn—O-based oxide semiconductor layer 403 including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower.
The In—Sn—O-based oxide semiconductor layer 404 reduces contact resistance. The In—Sn—O-based oxide semiconductor layer 404 is formed as the source region or drain region located between the source electrode layer or drain electrode layer 405 formed from a metal material having low electric resistance and the In—Sn—O-based oxide semiconductor layer 403 including SiOX. One of the source region and the drain region is formed with the In—Sn—O-based oxide semiconductor layer 408 which is the same layer as a pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 has both functions of the source region or the drain region and a pixel electrode.
The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX. The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 largely differ from the In—Sn—O-based oxide semiconductor layer 403 including SiOX in that they do not include Si. The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 can have lower resistance (higher conductivity) than the In—Sn—O-based oxide semiconductor layer 403 including SiOX. An In—Sn—O-based oxide semiconductor to which nitrogen is added may be used for the source region, the drain region, and the pixel electrode region. For example, an In—Sn—O-based non-single-crystal film including nitrogen can be used.
In
For example, as a two-layer structure of the gate electrode layer 401, the following structures are preferable: a two-layer structure of an aluminum layer and a molybdenum layer stacked thereover, a two-layer structure of a copper layer and a molybdenum layer stacked thereover, a two-layer structure of a copper layer and a titanium nitride layer or a tantalum nitride layer stacked thereover, and a two-layer structure of a titanium nitride layer and a molybdenum layer. As a three-layer structure, a structure in which a tungsten layer or a tungsten nitride layer, a layer of an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are stacked is preferable.
The gate insulating layer 402 is formed over the gate electrode layer 401.
The gate insulating layer 402 can be formed using a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer to have a single-layer or stacked-layer structure by a plasma CVD method, a sputtering method, or the like. Alternatively, the gate insulating layer 402 can be formed using a silicon oxide layer by a CVD method in which an organosilane gas is used. As the organosilane gas, the following compound containing silicon can be used: tetraethyl orthosilicate tetraethoxysilane (TEOS, chemical formula: Si(OC2H5)4), tetramethylsilane (TMS, chemical formula: Si (CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), or the like.
An In—Sn—O-based oxide semiconductor film 430 including SiOX and an In—Sn—O-based oxide semiconductor film 431 are formed in this order over the gate insulating layer 402. Each of the In—Sn—O-based oxide semiconductor film 430 including SiOX and the In—Sn—O-based oxide semiconductor film 431 is processed through a photolithography step so as to be an island-shaped oxide semiconductor layer.
Note that before the In—Sn—O-based oxide semiconductor film 430 including SiOX is formed by a sputtering method, dust attached to a surface of the gate insulating layer 402 may be removed by plasma treatment in which an argon gas is introduced and plasma is generated.
A conductive film 432 is formed over the gate insulating layer 402, the In—Sn—O-based oxide semiconductor film 430 including SiOX, and the In—Sn—O-based oxide semiconductor film 431 (see
As the material of the conductive film 432, there are an element selected from Al, Cr, Ta, Ti, Mo, and W; an alloy including any of these elements as its component; an alloy including a combination of any of these elements; and the like. Alternatively, an alloy film in which Al (aluminum) and Nd (neodymium) or Sc (scandium) may be used.
The conductive film 432 is etched through an etching step to form the source electrode layer or drain electrode layer 405 (see
A mask 435 is formed over the In—Sn—O-based oxide semiconductor film 431 which does not include SiOX. The In—Sn—O-based oxide semiconductor film 430 including SiOX and the In—Sn—O-based oxide semiconductor film 431 are etched using the source electrode layer or drain electrode layer 405 and the mask 435 to form the In—Sn—O-based oxide semiconductor layer 403 including SiOX, the In—Sn—O-based oxide semiconductor layer 404, and the In—Sn—O-based oxide semiconductor layer 408 (see
Through the above process, the inverted staggered thin film transistor 470 illustrated in
The insulating film 407 can be formed using a single layer or a stacked layer of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film, which are/is obtained by a sputtering method or the like.
Accordingly, a semiconductor device provided with a thin film transistor having excellent characteristics and a pixel electrode layer can be realized.
Embodiment 2In this embodiment, an example of a semiconductor device including the thin film transistor of Embodiment 1 which is provided with a channel protective layer will be described with reference to
In the thin film transistor 471 in this embodiment, the channel protective layer 409 is formed over a channel formation region of the In—Sn—O-based oxide semiconductor layer 403 including SiOX. The In—Sn—O-based oxide semiconductor layer 403 is not etched because the channel protective layer 409 functions as a channel stopper.
The channel protective layer 409 can be formed using an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, or aluminum nitride oxide). As a formation method, a sputtering method can be used.
An In—Sn—O-based oxide semiconductor layer including silicon oxide or silicon oxynitride is used for a semiconductor layer including a channel formation region. The conductivity of the In—Sn—O-based oxide semiconductor layer 403 including SiOX is preferably 1.6×10−3 S/cm or less, or more preferably 1.3×10−4 S/cm or less. Note that the In—Sn—O-based oxide semiconductor layer 403 including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower.
The In—Sn—O-based oxide semiconductor layer 404 reduces contact resistance. The In—Sn—O-based oxide semiconductor layer 404 is formed as the source region or drain region between the source electrode layer or a drain electrode layer 405 formed from a metal material having low electric resistance and the In—Sn—O-based oxide semiconductor layer 403 including SiOX. One of the source region and the drain region is formed with the In—Sn—O-based oxide semiconductor layer 408 which is the same layer as a pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 has both functions of the source region or the drain region and a pixel electrode.
The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
In
The gate insulating layer 402 is formed over the gate electrode layer 401.
The In—Sn—O-based oxide semiconductor layer 403 including SiOX and the channel protective layer 409 are formed over the gate insulating layer 402. Each of the In—Sn—O-based oxide semiconductor layer 403 including SiOX and the channel protective layer 409 is formed through a photolithography step so as to have an island shape.
An In—Sn—O-based oxide semiconductor film 431 and a conductive film 432 are formed over the gate insulating layer 402, the In—Sn—O-based oxide semiconductor layer 403 including SiOX, and the channel protective layer 409 (see
The conductive film 432 is etched through an etching step to form the source electrode layer or drain electrode layer 405 (see
A mask 435 is formed over the In—Sn—O-based oxide semiconductor film 431 which does not include SiOX. The In—Sn—O-based oxide semiconductor film 431 is etched using the source electrode layer or drain electrode layer 405 and the mask 435 to form the In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 (see
Through the above steps, the inverted staggered thin film transistor 470 as illustrated in
Accordingly, a semiconductor device provided with a thin film transistor having excellent characteristics and a pixel electrode layer can be realized.
Embodiment 3Another example of a semiconductor device and a method of manufacturing the semiconductor device will be described with reference to
In the thin film transistor 460, the gate insulating layer 402 exists throughout the region including the thin film transistor 460, and the gate electrode layer 401 is provided between the gate insulating layer 402 and the substrate 400 which is a substrate having an insulating surface. Over the gate insulating layer 402, the source electrode layer or drain electrode layer 405, the In—Sn—O-based oxide semiconductor layer 404, and the In—Sn—O-based oxide semiconductor layer 408 are provided. The In—Sn—O-based oxide semiconductor layer 403 including SiOX is provided over the gate insulating layer 402, the source electrode layer or drain electrode layer 405, the In—Sn—O-based oxide semiconductor layer 404, and the In—Sn—O-based oxide semiconductor layer 408. Although not illustrated, a wiring layer is provided over the gate insulating layer 402 in addition to the source electrode layer or drain electrode layer 405. The wiring layer extends to the outside of a peripheral portion of the In—Sn—O-based oxide semiconductor layer 403 including SiOX.
An In—Sn—O-based oxide semiconductor layer including silicon oxide or silicon oxynitride is used for a semiconductor layer including a channel formation region. The conductivity of the In—Sn—O-based oxide semiconductor layer 403 including SiOX is preferably 1.6×10−3 S/cm or less, or more preferably 1.3×10−4 S/cm or less. Note that the In—Sn—O-based oxide semiconductor layer 403 including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower.
The In—Sn—O-based oxide semiconductor layer 404 reduces contact resistance. The In—Sn—O-based oxide semiconductor layer 404 is formed as the source region or drain region between the source electrode layer or a drain electrode layer 405 formed from a metal material having low electric resistance and the In—Sn—O-based oxide semiconductor layer 403 including SiOX. One of the source region and the drain region is formed with the In—Sn—O-based oxide semiconductor layer 408 which is the same layer as a pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 has both functions of the source region or the drain region and a pixel electrode.
The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
The gate electrode layer 401 is provided over the substrate 400 which is a substrate having an insulating surface. An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401.
The gate insulating layer 402 is formed over the gate electrode layer 401. Then, the source electrode layer or drain electrode layer 405 is formed over the gate insulating layer 452 (see
An In—Sn—O-based oxide semiconductor film is formed and processed through a photolithography step to form island-shaped In—Sn—O-based oxide semiconductor films 451 and 452 (see
Next, an In—Sn—O-based oxide semiconductor film 450 including SiOX is formed over the In—Sn—O-based oxide semiconductor films 451 and 452 (see
The In—Sn—O-based oxide semiconductor film 450 including SiOX is processed by etching through a photolithography step to form the island-shaped In—Sn—O-based oxide semiconductor layer 403 including SiOX (see
Through the above process, the inverted staggered thin film transistor 460 illustrated in
Accordingly, a semiconductor device provided with a thin film transistor having excellent characteristics and a pixel electrode layer can be realized.
Embodiment 4In this embodiment, an example of a top-gate semiconductor device will be described with reference to
The thin film transistor 480 has a structure in which the gate insulating layer 402 is formed over the source electrode layer or drain electrode layer 405, the In—Sn—O-based oxide semiconductor layers 404 and 408, and the In—Sn—O-based oxide semiconductor layer 403 including SiOX, and the gate electrode layer 401 is provided over the gate insulating layer 402 to overlap with the In—Sn—O-based oxide semiconductor layers 404 and 408 and the In—Sn—O-based oxide semiconductor layer 403 including SiOX.
An In—Sn—O-based oxide semiconductor layer including silicon oxide or silicon oxynitride is used for a semiconductor layer including a channel formation region. The conductivity of the In—Sn—O-based oxide semiconductor layer 403 including SiOX is preferably 1.6×10−3 S/cm or less, or more preferably 1.3×10−4 S/cm or less. Note that the In—Sn—O-based oxide semiconductor layer 403 including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower.
The In—Sn—O-based oxide semiconductor layer 404 reduces contact resistance. The In—Sn—O-based oxide semiconductor layer 404 is formed as the source region or drain region between the source electrode layer or a drain electrode layer 405 formed from a metal material having low electric resistance and the In—Sn—O-based oxide semiconductor layer 403 including SiOX. One of the source region and the drain region is formed with the In—Sn—O-based oxide semiconductor layer 408 which is the same layer as a pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 has both functions of the source region or the drain region and a pixel electrode.
The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
Accordingly, a semiconductor device provided with a thin film transistor having excellent characteristics and a pixel electrode layer can be realized.
Embodiment 5In this embodiment, another example of a top-gate semiconductor device will be described with reference to
The thin film transistor 481 has a structure in which the gate insulating layer 402 is formed over the In—Sn—O-based oxide semiconductor layer 403 including SiOX, the In—Sn—O-based oxide semiconductor layer 404, the In—Sn—O-based oxide semiconductor layer 408, and the source electrode layer or drain electrode layer 405, and the gate electrode layer 401 is provided over the gate insulating layer 402 to overlap with the In—Sn—O-based oxide semiconductor layer 403 including SiOX and the In—Sn—O-based oxide semiconductor layers 404 and 408.
An In—Sn—O-based oxide semiconductor layer including silicon oxide or silicon oxynitride is used for a semiconductor layer including a channel formation region. The conductivity of the In—Sn—O-based oxide semiconductor layer 403 including SiOX is preferably 1.6×10−3 S/cm or less, or more preferably 1.3×10−4 S/cm or less. Note that the In—Sn—O-based oxide semiconductor layer 403 including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower.
The In—Sn—O-based oxide semiconductor layer 404 reduces contact resistance. The In—Sn—O-based oxide semiconductor layer 404 is formed as the source region or drain region between the source electrode layer or a drain electrode layer 405 formed from a metal material having low electric resistance and the In—Sn—O-based oxide semiconductor layer 403 including SiOX. One of the source region and the drain region is formed with the In—Sn—O-based oxide semiconductor layer 408 which is the same layer as a pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 has both functions of the source region or the drain region and a pixel electrode.
The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
Accordingly, a semiconductor device provided with a thin film transistor having excellent characteristics and a pixel electrode layer can be realized.
Embodiment 6In
In
In this manner, the source region, the drain region, and the In—Sn—O-based oxide semiconductor layer to be the pixel electrode region may be formed after the insulating layer functioning as a planarization insulating film is formed over the thin film transistor.
As the planarization insulating film, an organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like.
Note that a siloxane-based resin is a resin formed from a siloxane-based material as a starting material and having the bond of Si—O—Si. The siloxane-based resin may include an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may include a fluoro group.
The method for the formation method of the planarization insulating film is not limited to a particular method and the following method can be used depending on the material of the planarization insulating film: a sputtering method, an SOG method, spin coating, dip coating, spray coating, a droplet discharge method (e.g., an inkjet method, screen printing, or offset printing), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like.
In this embodiment, an example of application of the thin film transistor described in Embodiment 1 is described; however, this embodiment is not limited thereto and can be implemented in combination with any of the structures described other embodiments.
Accordingly, a semiconductor device provided with a thin film transistor having excellent characteristics and a pixel electrode layer can be realized.
Embodiment 7In this embodiment, an example of a thin film transistor whose width of a gate electrode is different from that of the transistor of Embodiment 1 is described with reference to FIGS. 11A1, 11A2, 11B1, and 11B2,
An In—Sn—O-based oxide semiconductor layer including silicon oxide or silicon oxynitride is used for a semiconductor layer including a channel formation region. The conductivity of the In—Sn—O-based oxide semiconductor layer 103 including SiOX is preferably 1.6×10−3 S/cm or less, or more preferably 1.3×10−4 S/cm or less. Note that the In—Sn—O-based oxide semiconductor layer 103 including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower.
The In—Sn—O-based oxide semiconductor layer 104 reduces contact resistance. The In—Sn—O-based oxide semiconductor layer 104 is formed as the source region or drain region between the source electrode layer or a drain electrode layer 105 formed from a metal material having low electric resistance and the In—Sn—O-based oxide semiconductor layer 103 including SiOX. One of the source region and the drain region is formed with the In—Sn—O-based oxide semiconductor layer 110 which is the same layer as a pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 110 has both functions of the source region or the drain region and a pixel electrode.
The In—Sn—O-based oxide semiconductor layer 104 and the In—Sn—O-based oxide semiconductor layer 110 are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX. The In—Sn—O-based oxide semiconductor layer 104 and the In—Sn—O-based oxide semiconductor layer 110 largely differ from the In—Sn—O-based oxide semiconductor layer 103 including SiOX in that they do not include Si. The In—Sn—O-based oxide semiconductor layer 104 and the In—Sn—O-based oxide semiconductor layer 110 can have lower resistance (higher conductivity) than the In—Sn—O-based oxide semiconductor layer 103 including SiOX. An In—Sn—O-based oxide semiconductor to which nitrogen is added may be used for the source region, the drain region, and the pixel electrode region. For example, an In—Sn—O-based non-single-crystal film including nitrogen can be used.
The thin film transistor 170 functions as a switching element of a pixel portion in the semiconductor device of
A conductive layer is formed over the substrate 100 having an insulating surface. As the substrate 100 having an insulating surface, a glass substrate formed of barium borosilicate glass, alumino-borosilicate glass, or the like can be used.
Next, a photolithography step is performed to form a resist mask. Then, unnecessary portions of the conductive layer are removed, so that wirings and an electrode (a gate wiring including the gate electrode layer 101, a capacitor wiring 108, and a first terminal 121) are formed.
Each of the gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 of a terminal portion can be formed with a single layer or a stacked layer using a conductive material such as metal material selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc); or an alloy material including any of these materials as its main component. In addition, aluminum (Al), copper (Cu), or an alloy material including any of these materials as its main component may be used.
For example, as a two-layer structure of the gate electrode layer 101, the following structures are preferable: a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, and a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked. In addition, a stack-layer in which a copper oxide layer including Ca which is to be a barrier layer is formed over a copper layer including Ca, a stack-layer in which a copper oxide layer including Mg which is to be a barrier layer is formed over a copper layer including Mg, and the like are also preferable. Further, as a three-layer structure, it is preferable to stack a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer.
Next, the gate insulating layer 102 is formed over the entire surface of the gate electrode layer 101. The gate insulating layer 102 is formed to have a thickness of 50 nm to 400 nm inclusive by a sputtering method, a PCVD method, or the like.
For example, for the gate insulating layer 102, a silicon oxide film with a thickness of 100 nm is formed by a sputtering method. Needless to say, the gate insulating layer 102 is not limited to such a silicon oxide film, and other insulating films such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or a tantalum oxide film may be used to form a single-layer structure or a stacked-layer structure. In the case of employing a stacked-layer structure, for example, a silicon nitride film may be formed by a PCVD method and then a silicon oxide film may be formed thereover by a sputtering method. When a silicon oxynitride film, a silicon nitride film, or the like is used as the gate insulating layer 102, an impurity from the glass substrate, sodium for example, can be blocked from diffusing into and entering an oxide semiconductor to be formed thereover later.
Next, an In—Sn—O-based oxide semiconductor film including SiOX is formed over the gate insulating layer 102. The In—Sn—O-based oxide semiconductor film including SiOX is formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 at 5 wt % or higher and 50 wt % or lower, or preferably at 10 wt % or higher and 30 wt % or lower. By including SiOX in an In—Sn—O-based oxide semiconductor, the In—Sn—O-based oxide semiconductor including SiOX easily becomes amorphous in its formation. The In—Sn—O-based oxide semiconductor film including SiOX is etched using a resist mask formed through a photolithography step to form an In—Sn—O-based oxide semiconductor layer including SiOX. The conductivity of the In—Sn—O-based oxide semiconductor layer 103 including SiOX is preferably less than 1.6×10−3 S/cm, or more preferably less than 1.3×10−4 S/cm.
Then, an In—Sn—O-based oxide semiconductor film which does not include SiOX is formed using an In—Sn—O-based oxide semiconductor target which does not include SiOX. The In—Sn—O-based oxide semiconductor film which does not include SiOX is etched using a resist mask formed through a photolithography step to form an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method, and a pulsed DC sputtering method in which a bias is applied in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal film is formed.
In addition, there is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be set. With the multi-source sputtering apparatus, films of different materials can be formed to be stacked in the same chamber, or a film of plural kinds of materials can be formed by electric discharge at the same time in the same chamber.
In addition, there are a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering, and a sputtering apparatus used for an ECR sputtering in which plasma generated with the use of microwaves is used without using glow discharge.
Furthermore, as a deposition method by sputtering, there are also a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, and a bias sputtering in which a voltage is also applied to a substrate during deposition.
An In—Sn—O-based oxide semiconductor layer including SiO2 and an In—Sn—O-based oxide semiconductor layer can be formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 and an In—Sn—O-based oxide semiconductor target. The target is formed by attaching a target material to a bucking plate (a board for attaching a target thereto). As for the attachment of the target to the bucking plate, the target may be divided and attached to one bucking plate.
As the etching, either wet etching or dry etching can be used.
As the dry etching method, a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used. In order to etch the films into desired shapes, the etching condition (the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on a substrate side, the temperature of the electrode on the substrate side, or the like) is adjusted as appropriate.
As an etchant used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, an ammonia peroxide mixture (hydrogen peroxide:ammonia:water=5:2:2), or the like can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.
Furthermore, the etchant after the wet etching is removed together with the etched material by cleaning. Waste liquid of the etchant including the removed material may be purified to recycle the materials included in the waste liquid. A material such as indium included in the oxide semiconductor layer are collected from the waste liquid after the etching and recycled, so that resources can be effectively used and cost can be reduced.
The etching conditions (such as an etchant, etching time, and temperature) are appropriately adjusted depending on the material so that the material can be etched into a desired shape.
Next, a photolithography step is performed to form a resist mask, and unnecessary portions (part of the gate insulating layer) are removed by etching, so that a contact hole which is formed from the same material as the gate electrode layer and reaches the wiring or the electrode layer is formed. This contact hole is provided for direct contact with a conductive film formed later. For example, in a driver circuit portion, a contact hole is formed in the case where a thin film transistor whose gate electrode layer is direct contact with a source electrode layer or drain electrode layer or a terminal that is electrically connected to a gate wiring of a terminal portion is formed.
Next, the conductive film formed from a metal material is formed by a sputtering method or a vacuum evaporation method over the In—Sn—O-based oxide semiconductor layer including SiOX and the In—Sn—O-based oxide semiconductor layer which does not include SiOX.
As examples of a material of the conductive film, an element selected from Al, Cr, Ta, Ti, Mo, W, Nd, and Sc, an alloy including any of these elements as its component, an alloy including any of the elements in combination, and the like can be given.
For example, a single-layer structure of a titanium film, a two-layer structure in which a titanium film is stacked over an aluminum film, or the like may be employed for the conductive film. Alternatively, the conductive film may have a three-layer structure in which a Ti film, an aluminum film including Nd (Al—Nd), and a Ti film are stacked in this order. The conductive film may have a single-layer structure of an aluminum film including silicon.
Then, a photolithography step is performed to form a resist mask and unnecessary portions are removed by etching to form a conductive layer 128 connected to the source electrode layer or drain electrode layer 105, a second terminal 122, and the first terminal 121. Note that the second terminal 122 is electrically connected to a source wiring (a source wiring including the source electrode layer or drain electrode layer 105).
A photolithography step is performed to form a resist mask over the In—Sn—O-based oxide semiconductor layer including SiOX. The In—Sn—O-based oxide semiconductor layer including SiOX and the In—Sn—O-based oxide semiconductor layer are etched using the mask to form the In—Sn—O-based oxide semiconductor layer 103 including SiOX, the In—Sn—O-based oxide semiconductor layer 104, and the In—Sn—O-based oxide semiconductor layer 110. Note that only part of the In—Sn—O-based oxide semiconductor layer 103 including SiOX is etched so that the In—Sn—O-based oxide semiconductor layer 103 including SiOX has a groove (a recessed portion). The In—Sn—O-based oxide semiconductor layer 104 functions as the source region or drain region. The In—Sn—O-based oxide semiconductor layer 110 functions as the source region or drain region and the pixel electrode.
Through the above steps, a semiconductor device whose pixel portion includes the thin film transistor 170 in which the In—Sn—O-based oxide semiconductor layer 103 including SiOX serves as the channel formation region, and the In—Sn—O-based oxide semiconductor layer serves as the pixel electrode can be manufactured. Note that a top view at this stage corresponds to
Further, by use of a resist mask having regions with plural thicknesses (typically, two different thicknesses) which is formed using a multi-tone mask, the number of resist masks can be reduced, resulting in simplified process and lower costs.
Next, the protective insulating layer 107 is formed to cover the thin film transistor 170. For the protective insulating layer 107, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like which is obtained by a sputtering method or the like can be used.
Next, a photolithography step is performed to form a resist mask and the protective insulating layer 107 is etched, so that a pixel electrode region of the In—Sn—O-based oxide semiconductor layer 110 is exposed. In addition, a contact hole reaching the second terminal 122 and a contact hole reaching the conductive layer 128 are also formed in this etching.
The conductive layer 128 directly connected to the first terminal 121 serves as a connection terminal electrode functioning as an input terminal of the gate wiring. The second terminal 122 is a connection terminal electrode functioning as an input terminal of the source wiring.
FIGS. 11A1 and 11A2 are respectively a cross-sectional view and a top view of a gate wiring terminal portion at this stage. FIG. 11A1 corresponds to a cross-sectional view taken along line E1-E2 of FIG. 11A2. In FIG. 11A1, a conductive layer 153 which is exposed by removing the protective insulating film 154 is a connection terminal electrode functioning as an input terminal. Furthermore, in the terminal portion of FIG. 11A1, a first terminal 151 formed from the same material as the gate wiring and the conductive layer 153 formed from the same material as the source wiring are connected to each other and brought into conduction. Note that the portion illustrated in
FIGS. 11B1 and 11B2 are respectively a cross-sectional view and a top view of a source wiring terminal portion which is different from that illustrated in
A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. Also in the terminal portion, the first terminal at the same potential as the gate wiring, the second terminal at the same potential as the source wiring, the third terminal at the same potential as the capacitor wiring, and the like are each arranged in plurality. There is no particular limitation on the number of each of the terminals, and the number of the terminals may be determined by a practitioner as appropriate.
In this manner, the pixel portion including the thin film transistor 170 that is a bottom-gate n-channel thin film transistor, the pixel electrode, and a storage capacitor and the terminal portion can be completed. In addition, a driver circuit can be formed over the same substrate. These are arranged in matrix in respective pixels so that a pixel portion is formed, which can be used as one of substrates for manufacturing an active matrix display device. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
When an active matrix liquid crystal display device is manufactured, an active matrix substrate and a counter substrate provided with a counter electrode are bonded to each other with a liquid crystal layer interposed therebetween. Note that a common electrode electrically connected to the counter electrode on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. This fourth terminal is provided so that the common electrode is fixed to a predetermined potential such as GND or 0 V.
The embodiment of the present invention is not limited to the pixel structure of
In an active matrix liquid crystal display device, display patterns are formed on a screen by driving pixel electrodes arranged in a matrix. In more detail, when voltage is applied between a selected pixel electrode and a counter electrode that corresponds to the selected pixel electrode, a liquid crystal layer provided between the pixel electrode and the counter electrode is optically modulated, and this optical modulation is recognized as a display pattern by an observer.
In displaying moving images, a liquid crystal display device has a problem that a long response time of liquid crystal molecules themselves causes afterimages or blurring of moving images. In order to improve the moving-image characteristics of a liquid crystal display device, a driving method called black insertion is employed in which black is displayed on the whole screen every other frame period.
Alternatively, a driving method called double-frame rate driving may be employed in which a vertical synchronizing frequency is 1.5 times or more, preferably, 2 times or more as high as a usual vertical synchronizing frequency, whereby the moving-image characteristics are improved.
Further alternatively, in order to improve the moving-image characteristics of a liquid crystal display device, a driving method may be employed in which a plurality of LED (light-emitting diode) light sources or a plurality of EL light sources are used to form a surface light source as a backlight, and each light source of the surface light source is independently driven in a pulsed manner in one frame period. As the surface light source, three or more kinds of LEDs may be used and an LED emitting white light may be used. Since a plurality of LEDs can be controlled independently, the light emission timing of LEDs can be synchronized with the timing at which a liquid crystal layer is optically modulated. According to this driving method, LEDs can be partly turned off; therefore, an effect of reducing power consumption can be obtained particularly in the case of displaying an image having a large part on which black is displayed.
By combining these driving methods, the display characteristics of a liquid crystal display device, such as moving-image characteristics, can be improved as compared to those of conventional liquid crystal display devices.
The use of the oxide semiconductor for the thin film transistor leads to reduction in manufacturing cost.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
Embodiment 8An example will be described below, in which at least a part of a driver circuit and a thin film transistor arranged in a pixel portion are formed over the same substrate in a display device which is one example of a semiconductor device.
The thin film transistor arranged in the pixel portion includes an In—Sn—O-based oxide semiconductor layer including SiOX, as a semiconductor layer including a channel formation region; and an In—Sn—O-based oxide semiconductor layer which does not include SiOX, as a source region and a drain region. The thin film transistor arranged in the pixel portion is formed in accordance with Embodiments 1 to 7. Further, the thin film transistor described in Embodiments 1 to 7 is an n-channel TFT, and thus a part of a driver circuit that can include an n-channel TFT among driver circuits is formed over the same substrate as the thin film transistor of the pixel portion.
In addition, the thin film transistor described in Embodiments 1 to 7 is an n-channel TFT, and a signal line driver circuit including the n-channel TFT is described with reference to
The signal line driver circuit illustrated in
The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, and the third wiring 5613, and the wirings 5621_1 to 5621_M are connected to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to three signal lines via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. For example, the wiring 5621_J of the J-th column (one of the wirings 5621_1 to 5621_M) is connected to a signal line Sj−1, a signal line Sj, and a signal line Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively, which are included in the switch group 5602_J.
A signal is input to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.
Note that the driver IC 5601 is preferably formed over a single crystal substrate. Further, the switch groups 5602_1 to 5602_M are preferably formed over the same substrate as the pixel portion is. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M are preferably connected through an FPC or the like.
Next, an operation of the signal line driver circuit illustrated in
Note that the timing chart in
Note that the timing chart in
In the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, different video signals are input to the wirings 5621_1 to 5621_M. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj−1, a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj, and a video signal input to the wiring 5621_J in the third sub-selection period T3 is input to the signal line Sj+1. In addition, the video signals input to the wiring 5621_J in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are denoted by Data_j−1, Data_j, and Data_j+1.
As shown in
As described above, in the signal line driver circuit in
Note that there are no particular limitation on the arrangement, the number, a driving method, and the like of the thin film transistors, as long as one gate selection period is divided into a plurality of sub-selection periods and video signals are input to a plurality of signal lines from one wiring in the respective sub-selection periods as shown in
For example, when video signals are input to three or more signal lines from one wiring in three or more sub-selection periods, it is only necessary to add a thin film transistor and a wiring for controlling the thin film transistor. Note that when one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes shorter. Therefore, one gate selection period is preferably divided into two or three sub-selection periods.
As another example, one selection period may be divided into a precharge period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 as shown in a timing chart of
As described above, in the signal line driver circuit of
Further, a structure of a scan line driver circuit is described. The scan line driver circuit includes a shift register and a buffer. Additionally, the scan line driver circuit may include a level shifter. In the scan line driver circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffered and amplified by the buffer, and the resulting signal is supplied to a corresponding scan line. Gate electrodes of transistors in pixels of one line are connected to the scan line. Since the transistors in the pixels of one line have to be turned on all at once, a buffer which can supply a large current is used.
One mode of a shift register used for a part of the scan line driver circuit will be described with reference to
The connection relationship of the shift register of
Further, a fourth wiring 5504 shown in
Note that the first wiring 5501 of the first stage flip-flop 5701_1 which is shown in
Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fourth wiring 5714 and the fifth wiring 5715 may be referred to as a first power source line and a second power source line, respectively.
Next,
Next, connection structures of the flip-flops shown in
A first electrode (one of a source electrode and a drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504. A second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.
A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506. A second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.
A first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and a second electrode of the third thin film transistor 5573 is connected to a gate electrode of the second thin film transistor 5572. A gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.
A first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506. A second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the fourth thin film transistor 5574 is connected to a gate electrode of the first thin film transistor 5571.
A first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505. A second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501.
A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. A second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5572.
A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. A second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571. A gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. A second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572. A gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501.
Note that the point at which the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 are connected is referred to as a node 5543. The point at which the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 are connected is referred to as a node 5544.
Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. The fifth wiring 5505 and the sixth wiring 5506 may be referred to as a first power source line and a second power source line, respectively.
In addition, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in Embodiment 1. The n-channel TFT described in Embodiment 1 has a high mobility of the transistor, and thus a driving frequency of a driver circuit can be increased. Further, parasitic capacitance is reduced by the source or drain region; thus, the n-channel TFT described in Embodiment 1 has high frequency characteristics (referred to as f characteristics). For example, a scan line driver circuit using the n-channel TFT described in Embodiment 1 can operate at high speed, and thus a frame frequency can be increased and insertion of black images can be realized.
In addition, when the channel width of the transistor in the scan line driver circuit is increased or a plurality of scan line driver circuits are provided, for example, higher frame frequency can be realized. When a plurality of scan line driver circuits are provided, a scan line driver circuit for driving scan lines of even-numbered rows is provided on one side and a scan line driver circuit for driving scan lines of odd-numbered rows is provided on the opposite side; thus, an increase in frame frequency can be realized. Furthermore, the use of the plurality of scan line driver circuits for output of signals to the same scan line is advantageous in increasing the size of a display device.
Further, when an active matrix light-emitting display device which is an example of a semiconductor device is manufactured, a plurality of thin film transistors are arranged in at least one pixel, and thus a plurality of scan line driver circuits are preferably arranged.
The light-emitting display device illustrated in
When the video signal input to a pixel of the light-emitting display device illustrated in
Since the response time of a light-emitting element is higher than that of a liquid crystal element or the like, the light-emitting element is more suitable for a time grayscale method than the liquid crystal element. Specifically, in the case of displaying with a time grayscale method, one frame period is divided into a plurality of sub-frame periods. Then, in accordance with video signals, the light-emitting element in the pixel is brought into a light-emitting state or a non-light-emitting state in each sub-frame period. By dividing one frame period into a plurality of sub-frame periods, the total length of time of a period, in which a pixel actually emits light in one frame period, can be controlled by video signals so that grayscale can be displayed.
Note that in the example of the light-emitting display device illustrated in
Also in the light-emitting display device, a part of a driver circuit that can include an n-channel TFT among driver circuits can be formed over the same substrate as the thin film transistor of the pixel portion. Alternatively, the signal line driver circuit and the scan line driver circuit can be formed using only the n-channel TFTs described in Embodiment 1 to 7.
Moreover, the above-described driver circuit can be used for electronic paper that drives electronic ink using an element electrically connected to a switching element, without being limited to applications to a liquid crystal display device or a light-emitting display device. The electronic paper is also referred to as an electrophoretic display device (an electrophoretic display) and is advantageous in that it has the same level of readability as plain paper, it has lower power consumption than other display devices, and it can be made thin and lightweight.
Electrophoretic displays can have various modes. Electrophoretic displays contain a plurality of microcapsules dispersed in a solvent or a solute, each microcapsule containing first particles which are positively charged and second particles which are negatively charged. By applying an electric field to the microcapsules, the particles in the microcapsules move in opposite directions to each other and only the color of the particles gathering on one side is displayed. Note that the first particles and the second particles each contain pigment and do not move without an electric field. Moreover, the first particles and the second particles have different colors (which may be colorless).
Thus, an electrophoretic display is a display that utilizes a so-called dielectrophoretic effect by which a substance having a high dielectric constant moves to a high-electric field region. An electrophoretic display device does not need to use a polarizer or a counter substrate, which is required in a liquid crystal display device, and both the thickness and weight of the electrophoretic display device can be reduced to a half of those of a liquid crystal display device.
A solution in which the above microcapsules are dispersed in a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Furthermore, by using a color filter or particles that have a pigment, color display can also be achieved.
In addition, when a plurality of the above microcapsules are arranged as appropriate over an active matrix substrate so as to be interposed between two electrodes, an active matrix display device can be completed, and display can be performed by application of an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors formed in accordance with Embodiments 1 to 7 can be used. Each of the thin film transistors formed in accordance with Embodiments 1 to 7 includes the In—Sn—O-based oxide semiconductor layer including SiOX as the semiconductor layer including the channel formation region; and the In—Sn—O-based oxide semiconductor layer which does not include SiOX, as the source and the drain region.
Note that the first particles and the second particles in the microcapsules may each be formed of a single material selected from a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and a magnetophoretic material, or formed of a composite material of any of these.
Through the above process, a highly reliable display device can be manufactured as a semiconductor device.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
Embodiment 9When a thin film transistor is manufactured and used for a pixel portion and further for a driver circuit, a semiconductor device having a display function (also referred to as a display device) can be manufactured. Furthermore, when a part or whole of a driver circuit using a thin film transistor is formed over the same substrate as that for a pixel portion, a system-on-panel can be obtained.
The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. Light-emitting elements include, in its category, an element whose luminance is controlled by current or voltage, and specifically include an inorganic electroluminescent (EL) element, an organic EL element, and the like. Furthermore, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.
In addition, the display device includes a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel. The present invention also relates to an element substrate, which corresponds to one mode before the display element is completed in a manufacturing process of the display device, and the element substrate is provided with means for supplying current to the display element in each of a plurality of pixels.
Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Furthermore, the display device also includes the following modules in its category: a module to which a connector such as an FPC (flexible printed circuit), a TAB (tape automated bonding) tape, or a TCP (tape carrier package) is attached; a module having a TAB tape or a TCP at the tip of which a printed wiring board is provided; and a module in which an IC (integrated circuit) is directly mounted on a display element by a COG (chip on glass) method.
The appearance and a cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIGS. 22A1, 22A2, and 22B. FIGS. 22A1 and 22A2 are each a plan view of a panel in which thin film transistors 4010 and 4011 described in Embodiment 1 which are formed over a first substrate 4001, and a liquid crystal element 4013 are sealed between the first substrate 4001 and a second substrate 4006 with a sealant 4005. The thin film transistors 4010 and 4011 each include an In—Sn—O-based oxide semiconductor layer including SiOX as a semiconductor layer including a channel formation region; and an In—Sn—O-based oxide semiconductor layer which does not include SiOX, as a source region and a drain region.
The sealant 4005 is provided to surround a pixel portion 4002 and a scan line driver circuit 4004 that are provided over the first substrate 4001. The second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with a liquid crystal layer 4008, by the first substrate 4001, the sealant 4005, and the second substrate 4006. A signal line driver circuit 4003 that is formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared is mounted in a region different from the region surrounded by the sealant 4005 over the first substrate 4001.
Note that there is no particular limitation on the connection method of a driver circuit which is separately formed, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG. 22A1 illustrates an example of mounting the signal line driver circuit 4003 by a COG method, and FIG. 22A2 illustrates an example of mounting the signal line driver circuit 4003 by a TAB method.
The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 each include a plurality of thin film transistors.
As each of the thin film transistors 4010 and 4011, the thin film transistor described in Embodiment 1 can be used. The thin film transistor described in Embodiment 1 includes an In—Sn—O-based oxide semiconductor layer including SiOX as a semiconductor layer including a channel formation region; and an In—Sn—O-based oxide semiconductor layer which does not include SiOX, as a source region and a drain region. Alternatively, the thin film transistor described in any of Embodiments 2 to 7 may be employed. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.
In addition, the liquid crystal element 4013 includes an In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX, as a pixel electrode layer. The In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX also functions as a source region or a drain region of the thin film transistor 4010 and electrically connects the thin film transistor 4010 and the liquid crystal element 4013. A counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. A portion where the In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX and the counter electrode layer 4031 overlap with each other corresponds to the liquid crystal element 4013. Note that the In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX and the counter electrode layer 4031 are respectively provided with an insulating layer 4032 and an insulating layer 4033 which function as alignment films. The liquid crystal layer 4008 is interposed between the In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX and the counter electrode layer 4031 with the insulating layers 4032 and 4033 interposed between the In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX and the counter electrode layer 4031.
Note that the first substrate 4001 and the second substrate 4006 can be made of glass, metal (typically, stainless steel), ceramic, or plastic. As plastic, an FRP (fiberglass-reinforced plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Alternatively, a sheet with a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.
A columnar spacer denoted by reference numeral 4035 is obtained by selective etching of an insulating film and is provided in order to control the distance (a cell gap) between the In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX and the counter electrode layer 4031. Note that a spherical spacer may also be used. The counter electrode layer 4031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. With the use of a common connection portion, the counter electrode layer 4031 can be electrically connected to the common potential line through conductive particles provided between the pair of substrates. Note that the conductive particles are contained in the sealant 4005.
Alternatively, a liquid crystal showing a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of the liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while the temperature of cholesteric liquid crystal is increased. Since the blue phase is only generated within a narrow range of temperatures, a liquid crystal composition containing a chiral agent at 5 wt % or more is used for the liquid crystal layer 4008 in order to broaden the temperature range. The liquid crystal composition which includes a liquid crystal showing a blue phase and a chiral agent has a short response time of 10 μs to 100 μs, has optical isotropy which makes the alignment process unneeded, and has a small viewing angle dependence.
An embodiment of the present invention can also be applied to a reflective liquid crystal display device or a semi-transmissive liquid crystal display device, in addition to a transmissive liquid crystal display device.
An example of the liquid crystal display device is described in which a polarizing plate is provided on the outer surface of the substrate (on the viewer side) and a coloring layer and an electrode layer used for a display element are provided on the inner surface of the substrate; however, the polarizing plate may be provided on the inner surface of the substrate. The stack structure of the polarizing plate and the coloring layer is not limited to that described in this embodiment and may be set as appropriate depending on materials of the polarizing plate and the coloring layer or conditions of manufacturing steps. Furthermore, a light-blocking film functioning as a black matrix may be provided.
In addition, in order to reduce the surface roughness of the thin film transistor and improve the reliability of the thin film transistor, an insulating layer functioning as a planarization film or a protective film may be formed over the thin film transistor. Note that the protective film is provided to prevent entry of impurities contained in the air, such as an organic substance, a metal substance, or water vapor, and is preferably a dense film. The protective film may be formed by a sputtering method to be a single layer or a stacked layer using any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, and an aluminum nitride oxide film. Although an example in which the protective film is formed by a sputtering method is described in this embodiment, an embodiment of the present invention is not limited to this method and a variety of methods may be employed.
Here, the insulating layer 4020 having a stack structure is formed as the protective film. As a first layer of the insulating layer 4020, a silicon oxide film is formed by a sputtering method. The use of the silicon oxide film as the protective film has the effect of preventing a hillock of an aluminum film used for the source and drain electrode layers.
In addition, an insulating layer is formed as a second layer of the protective film. In this embodiment, as a second layer of the insulating layer 4020, a silicon nitride film is formed by a sputtering method. The use of the silicon nitride film as the protective film can prevent mobile ions such as sodium ions from entering a semiconductor region, thereby suppressing variations in electric characteristics of the TFT.
As the planarization insulating film, an organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like.
Note that a siloxane resin is a resin formed from a siloxane material as a starting material and having a Si—O—Si bond. As a substituent, an organic group (e.g., an alkyl group or an aryl group) or a fluoro group may be used. The organic group may include a fluoro group.
There is no particular limitation on the method for forming the planarization insulating film, and the planarization insulating film can be formed, depending on the material, by using a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (e.g., an inkjet method, screen printing, offset printing, or the like), a doctor knife, a roll coater, a curtain coater, a knife coater, or the like.
The counter electrode layer 4031 can be made of a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide to which silicon oxide is added.
A conductive composition including a conductive high molecule (also referred to as a conductive polymer) can be used for the counter electrode layer 4031. The pixel electrode made of the conductive composition preferably has a sheet resistance of 10000 ohms per square or less and a transmittance of 70% or more at a wavelength of 550 nm. Furthermore, the resistivity of the conductive high molecule contained in the conductive composition is preferably 0.1 Ω·cm or less.
As the conductive high molecule, a so-called π-electron conjugated conductive polymer can be used. For example, it is possible to use polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds of them.
In addition, a variety of signals and potentials are supplied to the signal line driver circuit 4003 that is formed separately, and the scan line driver circuit 4004 or the pixel portion 4002 from an FPC 4018.
A terminal electrode 4016 is formed from the same conductive film as source wiring layers of the thin film transistors 4010 and 4011.
The terminal electrode 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.
Note that FIGS. 22A1, 22A2, and 22B illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, the present invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only a part of the signal line driver circuit or a part of the scan line driver circuit may be separately formed and then mounted.
For the liquid crystal display module, a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an FFS (fringe field switching) mode, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optical compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (antiferroelectric liquid crystal) mode, or the like can be used.
Through the above process, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
Embodiment 10An example of electronic paper will be described as a semiconductor device.
The twisting ball display system refers to a method in which spherical particles each colored in black or white are arranged between electrode layers which are used for a display element, and a potential difference is generated between the electrode layers to control orientation of the spherical particles, so that display is performed.
The thin film transistor 581 provided over a substrate 580 is a bottom-gate thin film transistor, and is in contact with an In—Sn—O-based oxide semiconductor layer 587 which does not include SiOX and functions as a source region or a drain region and a pixel electrode layer through an opening formed in insulating layers 585, whereby the thin film transistor 581 is electrically connected to the In—Sn—O-based oxide semiconductor layer 587. Between the In—Sn—O-based oxide semiconductor layer 587 which does not include SiOX and an electrode layer 588, spherical particles 589 each having a black region 590a, a white region 590b, and a cavity 594 around the regions which is filled with liquid are provided. A space around the spherical particles 589 is filled with a filler 595 such as a resin (see
Instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of approximately 10 μm to 20 μM, in which a transparent liquid and positively charged white microparticles and negatively charged black microparticles are encapsulated, is used. In the microcapsule which is provided between the pixel electrode layer and the common electrode layer, when an electric field is applied by the pixel electrode layer and the common electrode layer, the white microparticles and the black microparticles migrate to opposite sides to each other, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is generally called electronic paper. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.
Through this process, highly reliable electronic paper can be manufactured as a semiconductor device.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
Embodiment 11An example of a light-emitting display device will be described as a semiconductor device. As a display element included in a display device, a light-emitting element utilizing electroluminescence is described here. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.
In an organic EL element, by application of a voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and a current flows. Then, the carriers (electrons and holes) recombine, so that the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.
The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. The dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission which utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.
The structure and operation of a pixel which can be driven by a digital time grayscale method will be described. An example is described here in which one pixel includes two n-channel transistors each using an In—Sn—O-based oxide semiconductor layer including SiOX for a channel formation region.
A pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. A gate of the switching transistor 6401 is connected to a scan line 6406, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 6401 is connected to a signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to a gate of the driving transistor 6402. The gate of the driving transistor 6402 is connected to a power source line 6407 through the capacitor 6403, a first electrode of the driving transistor 6402 is connected to the power source line 6407, and a second electrode of the driving transistor 6402 is connected to a first electrode (pixel electrode) of the light-emitting element 6404. A second electrode of the light-emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line provided over the same substrate.
Note that the second electrode (common electrode 6408) of the light-emitting element 6404 is set to be a low power source potential. The low power source potential is lower than a high power source potential which is supplied to the power source line 6407. For example, GND, 0 V, or the like may be set as the low power source potential. The difference between the high power source potential and the low power source potential is applied to the light-emitting element 6404 so that a current flows through the light-emitting element 6404, whereby the light-emitting element 6404 emits light. Thus, each potential is set so that the difference between the high power source potential and the low power source potential is greater than or equal to a forward threshold voltage of the light-emitting element 6404.
When the gate capacitance of the driving transistor 6402 is used as a substitute for the capacitor 6403, the capacitor 6403 can be omitted. The gate capacitance of the driving transistor 6402 may be formed between a channel region and a gate electrode.
Here, in the case of using a voltage-input voltage-driving method, a video signal is input to the gate of the driving transistor 6402 to make the driving transistor 6402 completely turned on or off. That is, the driving transistor 6402 operates in a linear region, and thus, a voltage higher than the voltage of the power source line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage greater than or equal to (power source line voltage+Vth of the driving transistor 6402) is applied to the signal line 6405.
In the case of using an analog grayscale method instead of the digital time grayscale method, the same pixel structure as in
In the case of using the analog grayscale driving method, a voltage greater than or equal to (forward voltage of the light-emitting element 6404+Vth of the driving transistor 6402) is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to a voltage to obtain a desired luminance, and includes at least a forward threshold voltage. By inputting a video signal to enable the driving transistor 6402 to operate in a saturation region, a current can flow through the light-emitting element 6404. In order that the driving transistor 6402 can operate in the saturation region, the potential of the power source line 6407 is higher than a gate potential of the driving transistor 6402. With the analog video signal, a current in accordance with the video signal flows through the light-emitting element 6404, and the analog grayscale driving method can be performed.
Note that the pixel structure is not limited to that illustrated in
Next, structures of the light-emitting element will be described with reference to
In order to extract light emitted from the light-emitting element, at least one of an anode and a cathode is required to transmit light. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure in which light is extracted through the surface opposite to the substrate, a bottom emission structure in which light is extracted through the surface on the substrate side, or a dual emission structure in which light is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure can be applied to a light-emitting element having any of these emission structures.
A light-emitting element having a top emission structure will be described with reference to
The light-emitting element 7002 corresponds to a region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005. In the case of the pixel illustrated in
Next, a light-emitting element having a bottom emission structure will be described with reference to
A region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel illustrated in
Next, a light-emitting element having a dual emission structure will be described with reference to
The light-emitting element 7022 corresponds to a region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap with one another. In the case of the pixel illustrated in
Although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.
Note that the example is described in which a thin film transistor (a driving TFT) which controls the driving of a light-emitting element is electrically connected to the light-emitting element; however, a structure may be employed in which a TFT for current control is connected between the driving TFT and the light-emitting element.
Note that the structure of the semiconductor device is not limited to those illustrated in
Next, the appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one embodiment of the semiconductor device, will be described with reference to
A sealant 4505 is provided to surround a pixel portion 4502, signal line driver circuits 4503a and 4503b, and scan line driver circuits 4504a and 4504b, which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b. Accordingly, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b are sealed together with a filler 4507, by the first substrate 4501, the sealant 4505, and the second substrate 4506. It is preferable that a display device be thus packaged (sealed) with a protective film (such as a bonding film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the display device is not exposed to the outside air.
The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b formed over the first substrate 4501 each include a plurality of thin film transistors, and a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503a are illustrated as an example in
As each of the thin film transistors 4509 and 4510, the thin film transistor described in Embodiment 1, includes an In—Sn—O-based oxide semiconductor layer including SiOX as a semiconductor layer including a channel formation region; and an In—Sn—O-based oxide semiconductor layer which does not include SiOX, as a source region and a drain region, can be used. Alternatively, the thin film transistor described in any of Embodiments 2 to 7 may be employed. The thin film transistors 4509 and 4510 are n-channel thin film transistors.
In addition, the light-emitting layer 4511 includes an In—Sn—O-based oxide semiconductor layer 4517 which does not include SiOX and functions as a pixel electrode layer. The In—Sn—O-based oxide semiconductor layer 4030 which does not include SiOX also functions as a source region or a drain region of the thin film transistor 4510 and electrically connects the thin film transistor 4510 and the light-emitting element 4511. Note that the structure of the light-emitting element 4511 is, but not limited to, the stack structure which includes the In—Sn—O-based oxide semiconductor layer 4517 which does not include SiOX, an electroluminescent layer 4512, and the electrode layer 4513. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4511, or the like.
A partition wall 4520 is made of an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall 4520 be formed of a photosensitive material to have an opening over the In—Sn—O-based oxide semiconductor layer 4517 which does not include SiOX so that a sidewall of the opening is formed as an inclined surface with continuous curvature.
The electroluminescent layer 4512 may be formed as a single layer or a plurality of layers stacked.
A protective film may be formed over the electrode layer 4513 and the partition wall 4520 in order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting element 4511. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.
A variety of signals and potentials are supplied to the signal line driver circuits 4503a and 4503b, the scan line driver circuits 4504a and 4504b, or the pixel portion 4502 from FPCs 4518a and 4518b.
A terminal electrode 4516 is formed from the same conductive film as source wirings of the thin film transistors 4509 and 4510.
The terminal electrode 4516 is electrically connected to a terminal of the FPC 4518a through an anisotropic conductive film 4519.
In the case where the first substrate 4501 and/or the second substrate 4506 is located in the direction in which light is extracted from the light-emitting element 4511, the first substrate 4501 and/or the second substrate 4506 need/needs to have a light-transmitting property. In that case, a material with a light-transmitting property, such as a glass plate, a plastic sheet, a polyester film, or an acrylic film is used.
As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen is used for the filler.
In addition, if needed, an optical film, such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter, may be provided as appropriate on a light-emitting surface of the light-emitting element. Furthermore, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.
The signal line driver circuits 4503a and 4503b and the scan line driver circuits 4504a and 4504b may be mounted as driver circuits formed using a single crystal semiconductor film or a polycrystalline semiconductor film over a substrate separately prepared. Alternatively, only the signal line driver circuits or part thereof, or only the scan line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in
Through the above process, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.
This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.
Embodiment 12A semiconductor device disclosed in this specification can be applied to electronic paper. Electronic paper can be used for electronic appliances of a variety of fields as long as they display data. For example, electronic paper can be applied to an electronic book device (electronic book), a poster, an advertisement in a vehicle such as a train, or displays of various cards such as a credit card. Examples of the electronic appliances are illustrated in
A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display portion 2705 and the display portion 2707 may display one image or different images. In the case where the display portion 2705 and the display portion 2707 display different images, for example, text can be displayed on a display portion on the right side (the display portion 2705 in
The electronic book device 2700 may have a configuration capable of wirelessly transmitting and receiving data. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server.
Embodiment 13A semiconductor device disclosed in this specification can be applied as a variety of electronic appliances (including amusement machines). Examples of electronic appliances include television sets (also referred to as televisions or television receivers), monitor of computers or the like, cameras such as digital cameras or digital video cameras, digital photo frames, cellular phones (also referred to as mobile phones or mobile phone sets), portable game consoles, portable information terminals, audio reproducing devices, large-sized game machines such as pachinko machines, and the like.
The television set 9600 can be operated with an operation switch of the housing 9601 or a separate remote controller 9610. Channels and volume can be controlled with an operation key 9609 of the remote controller 9610 so that an image displayed on the display portion 9603 can be controlled. Furthermore, the remote controller 9610 may be provided with a display portion 9607 for displaying data output from the remote controller 9610.
Note that the television set 9600 is provided with a receiver, a modem, and the like. With the receiver, a general television broadcast can be received. Furthermore, when the television set 9600 is connected to a communication network by wired or wireless connection via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver, between receivers, or the like) data communication can be performed.
Note that the digital photo frame 9700 is provided with an operation portion, an external connection portion (a USB terminal, a terminal that can be connected to various cables such as a USB cable, or the like), a recording medium insertion portion, and the like. Although they may be provided on the same surface as the display portion, it is preferable to provide them on the side surface or the back surface for the design of the digital photo frame 9700. For example, a memory storing data of an image shot by a digital camera is inserted in the recording medium insertion portion of the digital photo frame, whereby the image data can be transferred and displayed on the display portion 9703.
The digital photo frame 9700 may have a configuration capable of wirelessly transmitting and receiving data. Through wireless communication, desired image data can be transferred to be displayed.
In the portable computer of
The bottom housing 9302 includes a pointing device 9306 with which input can be performed, in addition to the keyboard 9304. Further, when the display portion 9303 is a touch input panel, input can be performed by touching part of the display portion. The bottom housing 9302 includes an arithmetic function portion such as a CPU or hard disk. In addition, the bottom housing 9302 includes another device, for example, an external connection port 9305 into which a communication cable conformable to communication standards of a USB is inserted.
The top housing 9301, which includes a display portion 9307 and can keep the display portion 9307 therein by sliding it toward the inside of the top housing 9301, can have a large display screen. In addition, the user can adjust the orientation of a screen of the display portion 9307 which can be kept in the top housing 9301. When the display portion 9307 which can be kept in the top housing 9301 is a touch input panel, input can be performed by touching part of the display portion 9307 which can be kept in the top housing 9301.
The display portion 9303 or the display portion 9307 which can be kept in the top housing 9301 are formed using an image display device of a liquid crystal display panel, a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element, or the like.
In addition, the portable computer of
This cellular phone is formed with a main body which includes a communication device including at least a telephone function, and battery; a band portion which enables the main body to be wore on the wrist; an adjusting portion 9205 for adjusting the fixation of the band portion fixed for the wrist; a display portion 9201; a speaker 9207; and a microphone 9208.
In addition, the main body includes operating switches 9203. The operating switches 9203 serve, for example, as a switch for starting a program for the Internet when the switch is pushed, in addition to serving as a switch for turning on a power source, a switch for shifting a display, a switch for instructing to start taking images, or the like, and can be used so as to correspond to each function.
Input to this cellular phone is operated by touching the display portion 9201 with a finger or an input pen, operating the operating switches 9203, or inputting voice into the microphone 9208. Note that displayed buttons 9202 which are displayed on the display portion 9201 are illustrated in
Further, the main body includes a camera portion 9206 including an image pick-up means having a function of converting an image of an object, which is formed through a camera lens, to an electronic image signal. Note that the camera portion is not necessarily provided.
The cellular phone illustrated in
An image display device of a liquid crystal display panel, a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element, or the like is used as the display portion 9201. The cellular phone illustrated in
Note that
An In—Sn—O-based oxide semiconductor film including SiOX used for a semiconductor layer included in a channel formation region of a thin film transistor was formed. The detailed description thereof is given below.
Samples A, B, and C each of which was an In—Sn—O-based oxide semiconductor film including SiO2 were formed by a sputtering method using an In—Sn—O-based oxide semiconductor target including SiO2 (In2O3:SnO2:SiO2=85:10:5 (wt %)) and the conductivity thereof was measured. The formation conditions and the conductivity of the samples A, B, and C are shown in Table 1.
In Table 1, the proportion of an oxygen flow rate is obtained by dividing an oxygen flow rate flowing at the time of film formation by the whole flow rate of oxygen flow and argon. As shown in Table 1, the conductivity of the sample A formed at 4% of the oxygen flow rate was 4.20 E+01(4.20×10) S/cm, the conductivity of the sample B formed at 29% of the oxygen flow rate was 3.76 E−07(3.73×10−7) S/cm, and the conductivity of the sample C formed at 40% of the oxygen flow rate was 9.25 E−10(9.25×10−10) S/cm.
According to the above results of computation, as for the thin film transistor in which an In—Sn—O-based oxide semiconductor layer including SiOX is used as a semiconductor layer including a channel formation region, the semiconductor layer preferably has a conductivity less than or equal to 1.6×10−3 S/cm, or more preferably less than or equal to 1.3×10−4 S/cm.
Thus, since the In—Sn—O-based oxide semiconductor films including SiO2 of the sample B and the sample C each has a low conductivity of less than or equal to 1.3×10−4 S/cm, a thin film transistor having excellent electrical characteristics can be manufactured using the In—Sn—O-based oxide semiconductor film including SiO2 of the sample B or the sample C.
This application is based on Japanese Patent Application serial no. 2009-026482 filed with Japan Patent Office on Feb. 6, 2009, the entire contents of which are hereby incorporated by reference.
Claims
1. (canceled)
2. A semiconductor device comprising:
- a gate electrode layer;
- a gate insulating layer;
- a first oxide semiconductor layer including In;
- a second oxide semiconductor layer including In and N in contact with the first oxide semiconductor layer; and
- a pixel electrode,
- wherein the pixel electrode is in the second oxide semiconductor layer.
3. A semiconductor device according to claim 2, wherein conductivity of the first oxide semiconductor layer is less than or equal to 1.6×10−3 S/cm.
4. The semiconductor device according to claim 2, wherein the first oxide semiconductor layer is formed by a sputtering method using a target including In and O.
5. A semiconductor device according to claim 2, further comprising a liquid crystal layer interposed between the pixel electrode and a counter electrode.
6. A semiconductor device according to claim 2, further comprising a light-emitting layer over an anode in the pixel electrode, and a cathode over the light-emitting layer.
7. A semiconductor device according to claim 2, further comprising a light-emitting layer provided over a cathode provided in the pixel electrode, and an anode over the light-emitting layer.
8. A semiconductor device according to claim 2, wherein nitrogen is added to the second oxide semiconductor layer.
9. A semiconductor device according to claim 2, wherein a channel region is in the first oxide semiconductor layer.
10. The semiconductor device according to claim 2, wherein the first oxide semiconductor layer further includes Si.
11. A semiconductor device comprising:
- a gate electrode layer over a substrate having an insulating surface;
- a gate insulating layer over the gate electrode layer;
- a first oxide semiconductor layer including In and Si over the gate insulating layer;
- a second oxide semiconductor layer including In in contact with the first oxide semiconductor layer; and
- a pixel electrode,
- wherein the pixel electrode is in the second oxide semiconductor layer.
12. The semiconductor device according to claim 11, wherein a conductivity of the first oxide semiconductor layer is less than or equal to 1.6×10−3 S/cm.
13. The semiconductor device according to claim 11, wherein the first oxide semiconductor layer is formed by a sputtering method using a target including In, Si, and O where a concentration of SiO2 is 5 wt % or higher and 50 wt % or lower.
14. The semiconductor device according to claim 11, wherein nitrogen is added to the second oxide semiconductor layer.
15. The semiconductor device according to claim 11, wherein a channel region is in the first oxide semiconductor layer.
16. The semiconductor device according to claim 11, wherein the first oxide semiconductor layer further includes Sn.
17. The semiconductor device according to claim 11, wherein the second oxide semiconductor layer further includes Sn.
Type: Application
Filed: Aug 4, 2016
Publication Date: Nov 24, 2016
Inventors: Yoshiaki OIKAWA (Tochigi), Hotaka MARUYAMA (Tochigi), Hiromichi GODO (Isehara), Daisuke KAWAE (Atsugi), Shunpei YAMAZAKI (Setagaya)
Application Number: 15/228,457
