VERTICAL RESISTOR IN 3D MEMORY DEVICE WITH TWO-TIER STACK
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
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The present technology relates to semiconductor memory devices.
Semiconductor memory devices are used in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
A charge-storing material such as a charge-trapping material can be used in such memory devices to store a charge which represents a data state. A charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers.
A memory device includes memory cells which may be arranged in strings, for instance, select gate transistors are provided at the ends of the string to selectively connect a channel of the string to a source line or bit line. However, various challenges are presented in providing such memory devices.
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells.
A 3D memory structure may comprise a stack formed from an array of alternating conductive and dielectric layers. A memory hole is etched in the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory hole with appropriate materials. For example, a MONOS film stack can be used. This include a metal which forms the control gate layer in the stack, as well as a film stack of oxide-nitride-oxide (ONO) followed by polysilicon (polycrystalline silicon) which are provided along the sidewall of each memory hole. A 3D memory structure can have various configurations. For example, a straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a bottom back gate.
In some memory devices, the memory cells are joined to one another such as in NAND strings in a block or sub-block. Each NAND string comprises a number of memory cells connected in series between one or more drain-side select gate transistors (SGD transistors), on a drain-side of the NAND string which is connected to a bit line, and one or more source-side select gate transistors (SGS transistors), on a source-side of the NAND string which is connected to a source line. Further, the memory cells can be arranged with a common word line) which acts a control gate. The control gates of the memory cells and select gate transistors can be provided by the conductive layers in the stack.
The stack of memory cells is provided in a memory cell area of a substrate while circuits for controlling the memory cells are provided in a peripheral area of the substrate, peripheral to the memory cell area. Such circuits can include generators which provide control gate voltages, reference voltages and reference currents, a power on circuit, and a digital-to-analog converter in a charge pump. Such circuits may be used during programming, reading and erasing operations for the memory cells. However, various challenges are presented in fabricating such circuits. For example, resistors are used in the circuits. One configuration of resistors includes a resistive material which extends across the surface of the substrate in multiple rows. However, such a configuration consumes a significant area of the substrate.
Techniques provided herein address the above and other issues by providing columnar resistors. In an example implementation, multiple columns, e.g., pillars, are created in a peripheral area of a substrate, with one column for each tier of a multi-tiered stack of memory cells. In one approach, a first column comprises polysilicon which forms a resistor, and a second column above the first column comprises metal as a contact to the resistor. The first and second columns together form a conductive path from a terminal of a transistor on the substrate to a top of the stack. A via may continue the conductive path to above-stack metal layers. The resistance of the resistor can be set by controlling a dopant level in the polysilicon. In one example approach, in-situ doping is performed during the deposition of amorphous silicon. One example of in-situ doping involves depositing multiple layers of silicon, where a different dopant concentration is provided for each layer. In one example, one layer or region is undoped, or intrinsic. In another example approach, dopants can be provided using ion implantation in the amorphous silicon. The amorphous silicon is converted to polysilicon by a heating step.
The columnar resistors may be fabricated in concert with a multi-tiered stack of memory cells, without significant changes to the lithographic process. For example, in a two-tiered stack, the first column may extend to a height of a top of the first tier, and the second column may extend from a height of the bottom of the second tier, or the height of the top of the first tier, to a height of a top of the second tier. Thus, the first column may be fabricated in concert with the first tier of the stack, and the second column may be fabricated in concert with the second tier of the stack. In general, a number N>=2 of tiers may be provided for the stack, with corresponding columns in the peripheral region, where each column is co-extensive with one of the tiers.
In another example implementation, multiple columnar resistors are connected to one metal contact. In another example, one part of a column comprises polysilicon and another part of the column comprises metal. In another example, a column comprising polysilicon is positioned above another column comprising polysilicon. Various other implementations are possible.
Various other features and benefits are described below.
The memory structure can be 2D or 3D. The memory structure may comprise one or more array of memory cells including a 3D array. The memory structure may comprise a monolithic three dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The memory structure may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.
The control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. A storage region 113 may be provided, e.g., for programming and read parameters.
The on-chip address decoder 114 provides an address interface between that used by the host or a memory controller to the hardware address used by the decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word lines, SGS and SGD transistors and source lines. The sense blocks can include bit line drivers, in one approach. An SGS transistor is a select gate transistor at a source end of a NAND string, and an SGD transistor is a select gate transistor at a drain end of a NAND string.
In some implementations, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than memory structure 126, can be thought of as at least one control circuit which is configured to perform various operations such as read, write and erase. For example, a control circuit may include any one of, or a combination of, control circuitry 110, state machine 112, decoders 114/132, power control module 116, sense blocks SBb, SB2, . . . , SBp, read/write circuits 128, controller 122, and so forth.
The off-chip controller 122 may comprise a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b and an error-correction code (ECC) engine 245. The ECC engine can correct a number of read errors which are caused when the upper tail of a Vth distribution becomes too high.
The storage device comprises code such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor can access code from a storage device 126a of the memory structure, such as a reserved area of memory cells in one or more word lines.
For example, code can be used by the controller to access the memory structure such as for programming, read and erase operations. The code can include boot code and control code (e.g., set of instructions). The boot code is software that initializes the controller during a booting or startup process and enables the controller to access the memory structure. The code can be used by the controller to control one or more memory structures. Upon being powered up, the processor 122c fetches the boot code from the ROM 122a or storage device 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.
In one embodiment, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor readable storage devices (RAM, ROM, flash memory, hard disk drive, solid state memory) that store processor readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input/output interfaces and/or one or more input/output devices in communication with the one or more processors.
Other types of non-volatile memory in addition to NAND flash memory can also be used.
Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse or phase change material, and optionally a steering element, such as a diode or transistor. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected transistors comprising memory cells and SG transistors.
A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-y direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the major surface of the substrate).
As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements. The columns may be arranged in a two dimensional configuration, e.g., in an x-y plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-y) memory device level. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
One of skill in the art will recognize that this technology is not limited to the two dimensional and three dimensional exemplary structures described but covers all relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of skill in the art.
In one possible approach, the length of the plane, in the x-direction, represents a direction in which signal paths to word lines extend in the one or more upper metal layers (a word line or SGD line direction), and the width of the plane, in the y-direction, represents a direction in which signal paths to bit lines extend in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the memory device.
Additional examples of the peripheral area of a memory device are described further below.
The stack includes a substrate 611, an insulating film 612 on the substrate, and a portion of a source line SL. NS1 has a source-end 613 at a bottom 614 of the stack and a drain-end 615 at a top 616 of the stack. Metal-filled slits 617 and 620 may be provided periodically across the stack as interconnects which extend through the stack, such as to connect the source line to a line above the stack. The slits may be used during the formation of the word lines and subsequently filled with metal or doped polysilicon. The slits may also be used to access the control gate layers to replace a scarified material with metal and to access the back side of materials in the memory holes, in some cases. A portion of a bit line BL0 is also depicted. A conductive via 621 connects the drain-end 615 to BL0.
Due to the non-uniformity in the width of the memory hole, the programming and erase speed of the memory cells can vary based on their position along the memory hole, e.g., based on their height in the stack. With a smaller diameter memory hole, the electric field across the tunnel oxide is relatively stronger, so that the programming and erase speed is relatively higher.
When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer which is associated with the memory cell. These electrons are drawn into the charge-trapping layer from the channel, and through the tunneling layer. The Vth of a memory cell is increased in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.
Each of the memory holes can be filled with a plurality of annular layers comprising a blocking oxide layer, a charge trapping layer, a tunneling layer and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are between the core region and the word line in each of the memory holes.
The NAND string can be considered to have a floating body channel because the length of the channel is not formed on a substrate. Further, the NAND string is provided by a plurality of word line layers above one another in a stack, and separated from one another by dielectric layers.
A block BLK in a 3D memory device can be divided into sub-blocks, where each sub-block comprises a set of NAND string which have a common SGD control line. Further, a word line layer in a block can be divided into regions. Each region can extend between slits which are formed periodically in the stack to process the word line layers during the fabrication process of the memory device. This processing can include replacing a sacrificial material of the word line layers with metal. Generally, the distance between slits should be relatively small to account for a limit in the distance that an etchant can travel laterally to remove the sacrificial material, and that the metal can travel to fill a void which is created by the removal of the sacrificial material. For example, the distance between slits may allow for a few rows of memory holes between adjacent slits. The layout of the memory holes and slits should also account for a limit in the number of bit lines which can extend across the region while each bit line is connected to a different memory cell. After processing the word line layers, the slits can optionally be filed with metal to provide an interconnect through the stack.
This figures and other are not necessarily to scale. In practice, the regions can be much longer in the x-direction relative to the y-direction than is depicted to accommodate additional memory holes.
In this example, there are four rows of memory holes between adjacent slits. A row here is a group of memory holes which are aligned in the x-direction. Moreover, the rows of memory holes are in a staggered pattern to increase the density of the memory holes. The word line layer is divided into regions WLL10a, WLL10b, WLL10c and WLL10d which are each connected by a connector 713. The last region of a word line layer in a block can be connected to a first region of a word line layer in a next block, in one approach. The connector, in turn, is connected to a voltage driver for the word line layer. The region WLL10a has example memory holes 710 and 711 along a line 712. See also
Each circle represents the cross-section of a memory hole at a word line layer or SG layer. Each circle can alternatively represent a memory cell which is provided by the materials in the memory hole and by the adjacent word line layer.
Metal-filled slits 701, 702, 703 and 704 (e.g., metal interconnects) may be located between and adjacent to the edges of the regions WLL10a-WLL10d. The metal-filled slits provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device. See also
The region DL19a has the example memory holes 710 and 711 along a line 712a which is coincident with a bit line BL0. A number of bit lines extend above the memory holes and are connected to the memory holes as indicated by the “X” symbols. BL0 is connected to a set of memory holes which includes the memory holes 711, 715, 717 and 719. Another example bit line BL1 is connected to a set of memory holes which includes the memory holes 710, 714, 716 and 718. The metal-filled slits 701, 702, 703 and 704 from
Different subsets of bit lines are connected to cells in different rows. For example, BL0, BL4, BL8, BL12, BL16 and BL20 are connected to cells in a first row of cells at the right hand edge of each region. BL2, BL6, BL10, BL14, BL18 and BL22 are connected to cells in an adjacent row of cells, adjacent to the first row at the right hand edge. BL3, BL7, BL11, BL15, BL19 and BL23 are connected to cells in a first row of cells at the left hand edge of each region. BL1, BL5, BL9, BL13, BL17 and BL21 are connected to cells in an adjacent row of cells, adjacent to the first row at the left hand edge.
Additionally, NS0_SBa include SGS transistors 800 and 801, dummy memory cells 802 and 803, data memory cells 804, 805, 806, 807, 808, 809, 810, 811, 812, 813 and 814, dummy memory cells 815 and 816, and SGD transistors 817 and 818.
NS0_SBb include SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833 and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.
NS0_SBc include SGS transistors 840 and 841, dummy memory cells 842 and 843, data memory cells 844, 845, 846, 847, 848, 849, 850, 851, 852, 853 and 854, dummy memory cells 855 and 856, and SGD transistors 857 and 858.
NS0_SBd include SGS transistors 860 and 861, dummy memory cells 862 and 863, data memory cells 864, 865, 866, 867, 868, 869, 870, 871, 872, 873 and 874, dummy memory cells 875 and 876, and SGD transistors 877 and 878.
Memory cells on WL8 include memory cells 812, 832, 852 and 872. Memory cells on WL9 include memory cells 813, 833, 853 and 873. In this example, the programming of the block may occur sub-block by sub-block. For example, SBa may be programmed from WLL0-WLL10, then SBb may be programmed from WLL0-WLL10, then SBc may be programmed from WLL0-WLL10 and then SBd may be programmed from WLL0-WLL10.
Step 903 includes depositing memory films in the memory holes (
Step 916 includes filling the vertical holes in the first dielectric peripheral area with amorphous silicon, and performing doping, heating and chemical-mechanical polishing (CMP). See, e.g.,
Step 920 includes depositing oxide-nitride oxide (ONO) films in the memory holes. See, e.g.,
Step 925 includes removing the sacrificial material in the non-resistor columns which was provided in step 916. See, e.g.,
Step 926 includes etching vertical holes in the second dielectric peripheral area, down to the first dielectric peripheral area, for resistor columns. See, e.g.,
Note that some of the steps can be performed in a different order than the order shown in
A first dielectric peripheral area 1010 includes example transistors 1020, 1030 and 1040. These transistors may be components in a circuit for controlling the stack, for instance. An etch stop material 1021 or layer such as SiN is formed on top of each transistor and a substrate etch stop material 1023 is formed on top of the substrate, between the transistors. The dielectric peripheral area may be, e.g., a plasma-enhanced oxide such as tetraethyl orthosilicate (TEOS) or a coating material such as silicon on glass (SOG).
The memory cell area includes a plurality of memory holes. An example memory hole 1004 (also referred to as a column or pillar when the memory hole is filled) includes a widened top portion 1006 above an elongated portion 1005. A source side region 1007 is below the memory hole. A top 1052t and a bottom 1052b of the stack are also depicted.
An etchant used to etch the second dielectric peripheral area 1610 to provide the vertical holes 2220 and 2221 may be selective of the dielectric but not of the polysilicon column 1501.
An example transistor 2820 is a MOSFET. The substrate includes n or p type diffusion regions (see
Subsequently, the contacts to the control gate layers and the resistor and non-resistor columns may be connected to metal paths above the stack. For example, a via 2630a connects the resistor column 2612 to an above-stack metal path 2630b. A via 2630c connects the metal contact 2615 to the above-stack metal path 2630a. In this case, the resistor column 2612 could be a component in a circuit which provides a voltage to the control gate layer 2511. Many other types of circuits can be provided as well.
A z-axis depicts different heights in the semiconductor device including z0 (substrate surface or height of transistor terminal in substrate), z1 (height of transistor terminal above substrate), z2 (height of top of first tier), and z3 (height of top of second tier or top of stack).
The semiconductor structure is an example of a three-dimensional structure in which memory cells are arranged in NAND strings.
By using different doping concentrations, the overall resistance of the polysilicon resistor can be set to a desired level. Generally, the resistance can be decreased by doping a relatively larger portion of the polysilicon and by using a relatively larger doping concentration.
In one approach, the providing the polysilicon in the first vertical hole comprises separately depositing intrinsic amorphous silicon in the first vertical hole and depositing doped amorphous silicon in the first vertical hole, and performing a heating step which converts the intrinsic amorphous silicon to intrinsic polysilicon and which converts the doped amorphous silicon to doped polysilicon.
The approach of
Another option involves multiple polysilicon pillars where one pillar has a relatively high doping concentration and acts as a contact to the other pillar, which has a relatively low doping concentration.
In
An example transistor 2820 is a MOSFET. The substrate includes n or p type diffusion regions 2821 and 2822 which act as source/drain terminals of the transistor. For example, the diffusion region 2822 may be the source terminal and the diffusion region 2821 may be the drain terminal. The transistor also includes a control gate 2824 (e.g., doped polysilicon) and a gate oxide 2825. When an appropriate voltage is applied to the control gate, a conductive channel is formed in the substrate under the gate oxide between the source and drain terminals. A conductive etch stop layer 2823 is provided above the control gate. A silicon nitride layer extends in a blanket deposition on the substrate and over the transistor. The silicon nitride layer includes a portion 2826 on the substrate, a portion 2827 on a sidewall of the transistor and a portion 2828 on a top of the transistor. A sidewall insulation layer 2829 may also be present on the sidewall of the transistor.
The substrate includes shallow trench isolation regions 2804 and 2805 which isolate the transistor from neighboring transistors.
A columnar resistor 2810 extends down though the dielectric and the portion 2828 of the silicon nitride layer to the etch stop layer 2823. A bottom 2810a of the columnar resistor touches the etch stop layer. The etch stop layer may be a conductive material which acts as a contact to the control gate 2824 of the transistor. Or, the etch stop layer 2823 may be omitted, in which case the bottom 2810a of the columnar resistor touches the control gate 2824. Another columnar resistor 2812 extends down though the dielectric, the transistor layer 2802 and the portion 2826 of the silicon nitride layer to the diffusion region 2822 of the substrate. A bottom 2812a of the columnar resistor touches the diffusion region.
This example shows columnar resistors connected to two terminals of a transistor. Generally, one or more columnar resistors can be connected to one or more terminals of a transistor. Another option is for a columnar resistor to be connected to one terminal of a transistor while a columnar metal contact, e.g., a non-resistor column, is connected to another terminal of the transistor. It is also possible for multiple columnar metal contacts to be connected to one terminal of a transistor. The diameter of the resistor pillar can be the same or different than the diameter of the memory hole. Generally, the diameter of the resistor pillar will be on the same order of magnitude as the diameter of the memory hole. Further, the shape of the resistor pillar can be a circle, square, ellipse, rectangle or line, for instance. Various other transistor and columnar resistor configurations may be provided.
The transistor 2920 has a body 2930 comprising three regions 2922, 2923 and 2924 such as n+, p− and n+ type silicon regions, respectively, where the top region 2922 is the drain terminal and the bottom region 2924 is the source terminal. A voltage is applied to side control gates to control whether a conductive channel exists between the source and the drain. For example, a control gate 2905 is separated from the body by an oxide region 2906. A silicon nitride layer includes a portion 2926 on the substrate, a portion 2927 on a sidewall of the transistor and a portion 2928 on a top of the transistor. A conductive line 2940 such as metal extends below the transistor and is in contact with the source region 2924 of the transistor. If a conductive channel exists between the source and the drain, a voltage on the conductive line is passed to the drain terminal.
A columnar resistor 2910 extends down though the dielectric and the portion 2928 of the silicon nitride layer to a etch stop layer 2921. A bottom 2910a of the columnar resistor touches the etch stop layer. The etch stop layer may be a conductive material which acts as a contact to the drain 2922 of the transistor. Or, the etch stop layer may be omitted, in which case the bottom 2910a of the columnar resistor touches the drain 2922.
Accordingly, it can be seen that, in one embodiment, a semiconductor device comprises: a substrate; a stack in a memory cell area of the substrate, the stack comprising a first tier and a second tier on the first tier, the first tier comprising a first set of alternating control gate layers and dielectric layers and the second tier comprising a second set of alternating control gate layers and dielectric layers, the stack comprising memory holes, each memory hole comprises a portion in the first tier and a portion in the second tier, and memory films extend along a wall of each memory hole; a transistor formed on the substrate in a peripheral area, peripheral to the memory cell area, the transistor is in a circuit; a first column in the peripheral area, the first column comprises polysilicon, a resistor in the circuit comprises the polysilicon in the first column, and the first column extends from a terminal of the transistor to a height of a top of the first tier; and a second column which extends from the height of the top of the first tier to a height of a top of the second tier, the second column is electrically connected to the first column.
In another embodiment, a method for fabricating a memory device comprises: forming a first tier of a stack in a memory cell area of a substrate, the first tier of the stack comprising a first set of alternating control gate layers and dielectric layers; forming vertical holes in the first tier of the stack; providing a sacrificial material in the vertical holes in the first tier of the stack; forming a first vertical hole in a dielectric peripheral area, the dielectric peripheral area is on the substrate and peripheral to the memory cell area; providing polysilicon in the first vertical hole; forming a second tier of the stack on the first tier of the stack, the second tier of the stack comprising a second set of alternating control gate layers and dielectric layers; forming vertical holes in the second tier of the stack, aligned with the sacrificial material in the vertical holes in the first tier; removing the sacrificial material from the vertical holes in the first tier; providing memory films in the vertical holes in the second tier and the vertical holes in the first tier; forming a second vertical hole in the dielectric peripheral area, above the first vertical hole; and providing a conductive material in the second vertical hole, the conductive material is electrically connected to the polysilicon.
In another embodiment, a semiconductor device comprises: a substrate; a transistor formed on the substrate, the transistor is in a circuit; a doped polysilicon column which is a resistor in the circuit, the doped polysilicon column is tapered, becoming narrower at a bottom of the doped polysilicon column; and a metal column which is above the doped polysilicon column, wherein a bottom of the doped polysilicon column contacts a terminal of the transistor, a bottom of the metal column is on a top of the doped polysilicon column, and the metal column is tapered, becoming narrower at a bottom of the metal column.
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
Claims
1. A semiconductor device, comprising:
- a substrate;
- a stack in a memory cell area of the substrate, the stack comprising a first tier and a second tier on the first tier, the first tier comprising a first set of alternating control gate layers and dielectric layers and the second tier comprising a second set of alternating control gate layers and dielectric layers, the stack comprising memory holes, each memory hole comprises a portion in the first tier and a portion in the second tier, and memory films extend along a wall of each memory hole;
- a transistor formed on the substrate in a peripheral area, peripheral to the memory cell area, the transistor is in a circuit;
- a first column in the peripheral area, the first column comprises polysilicon, a resistor in the circuit comprises the polysilicon in the first column, and the first column extends from a terminal of the transistor to a height of a top of the first tier, wherein a doping concentration of the first column varies radially relative to a central longitudinal axis of the resistor; and
- a second column which extends from the height of the top of the first tier to a height of a top of the second tier, the second column is electrically connected to the first column.
2. The semiconductor device of claim 1, wherein:
- the second column comprises a metal contact to the polysilicon.
3. The semiconductor device of claim 1, wherein:
- at least a bottom portion of the second column comprises polysilicon; and
- the resistor in the circuit comprises the polysilicon in the at least the bottom portion of the second column.
4. The semiconductor device of claim 1, wherein:
- the second column comprises polysilicon; and
- a doping concentration of the polysilicon in the second column is different than a doping concentration of the polysilicon in the first column by at least an order of magnitude.
5. The semiconductor device of claim 1, wherein:
- the polysilicon in the first column comprise a core along a central vertical axis of the first column and a surrounding region which surrounds the core; and
- the core is intrinsic and the surrounding region is doped.
6. (canceled)
7. The semiconductor device of claim 1, wherein:
- a bottom of the resistor is in contact with an n or p type diffusion region of the transistor in the substrate.
8. The semiconductor device of claim 1, wherein:
- a bottom of the resistor is in contact with a control gate of the transistor.
9. The semiconductor device of claim 1, further comprising:
- an additional column in the peripheral area, the additional column extends from the terminal of the transistor on the substrate to the height of the top of the first tier, wherein the second column is electrically connected to the additional column.
10. The semiconductor device of claim 1, wherein:
- the first column is tapered, becoming narrower at a bottom of the first column;
- the second column is tapered, becoming narrower at a bottom of the second column; and
- a top of the first column is wider than a bottom of the second column.
11. The semiconductor device of claim 1, wherein:
- a top of the first column at the height of the top of the first tier comprises, in a dielectric layer, a widened region which is wider than a remaining portion of the first column; and
- for each memory hole, a top of the portion in the first tier has, in the dielectric layer, a widened region which is wider than a remaining portion of each memory hole in the first tier.
12. The semiconductor device of claim 1, wherein:
- the control gate layers comprise control gates for memory cells;
- the memory films comprise a charge trapping layer and tunnel oxide for the memory cells; and
- the memory cells are arranged in NAND strings in a three-dimensional structure.
13. The semiconductor device of claim 1, wherein:
- the first column extends through a silicon nitride layer to the terminal of the transistor.
14.-18. (canceled)
19. A semiconductor device, comprising:
- a substrate;
- a transistor formed on the substrate, the transistor is in a circuit;
- a polysilicon column which is a resistor in the circuit, the polysilicon column is tapered, becoming narrower at a bottom of the polysilicon column, the polysilicon column comprise a core along a central vertical axis of the polysilicon column and a layer which surrounds the core, and the layer has a different doping concentration than the core; and
- a metal column which is above the polysilicon column, wherein a bottom of the polysilicon column contacts a terminal of the transistor, a bottom of the metal column is on a top of the polysilicon column, and the metal column is tapered, becoming narrower at a bottom of the metal column.
20. The semiconductor device of claim 19, further comprising:
- a three-dimensional array of NAND strings on the substrate, wherein the polysilicon column and the metal column are peripheral to the three-dimensional array of NAND strings, and the circuit is for providing a voltage to the three-dimensional array of NAND strings.
21. The semiconductor device of claim 19, wherein:
- a doping concentration in the polysilicon column varies radially relative to a central vertical axis of the polysilicon column.
22. The semiconductor device of claim 1, wherein:
- the doping concentration decreases when moving radially outward from the central longitudinal axis.
23. The semiconductor device of claim 1, wherein:
- the doping concentration increases when moving radially outward from the central longitudinal axis.
24. The semiconductor device of claim 1, wherein:
- the polysilicon in the first column comprise a core and a surrounding region which surrounds the core; and
- the core is doped and the surrounding region is intrinsic.
25. The semiconductor device of claim 1, wherein:
- the polysilicon in the first column comprise a core and a layer surrounding the core; and
- the layer has a different doping concentration than the core.
26. The semiconductor device of claim 1, wherein:
- the polysilicon in the first column comprise a core and first and second layers surrounding the core; and
- the first layer, the second layer and the core have different doping concentrations.
Type: Application
Filed: Dec 4, 2015
Publication Date: Jun 8, 2017
Applicant: SanDisk Technologies Inc. (Plano, TX)
Inventors: Masatoshi Nishikawa (Yokkaichi), Kota Funayama (Kuwana City), Toru Miwa (Yokohama), Hiroyuki Ogawa (Nagoya)
Application Number: 14/959,169