SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES
An integrated circuit product includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. A source/drain region is positioned between the two laterally spaced-apart transistors, and a conformal etch stop layer is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the sidewall spacer of each of the two laterally spaced-apart transistors. A self-aligned conductive contact extends through an opening in the conformal etch stop layer and is conductively coupled to the source/drain region.
1. Field of the Disclosure
The present disclosure generally relates to integrated circuit products, and more particularly, to integrated circuit products having self-aligned device level contact structures.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. FETs come in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. These FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region. The gate structures for such transistor devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. In contrast to a planar transistor device, which as the name implies has a generally planar structure, a so-called FinFET device has a three-dimensional (3D) structure. That is, the gate structure of a FinFET device may be positioned around both the sides and the upper surface of a portion of a fin that was previously defined in the substrate to thereby form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. That is, unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. For a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices.
For many early device technology generations, the gate structures of most transistor elements (planar or FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode and a silicon nitride gate cap layer. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. The replacement gate process may be used when forming planar devices or 3D devices.
The various components and structures of the device 10 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 14 may be comprised of silicon dioxide, the sacrificial gate electrode 15 may be comprised of polysilicon or amorphous silicon, the sidewall spacer 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopants for PMOS devices) that are implanted into the substrate 12 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 10 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon/germanium that are typically found in high performance PMOS transistors. At the point of fabrication depicted in
Next, as shown in
Ultimately, as shown in
In the case of a gate-first process, the material(s) of the gate insulation layer are initially formed above the substrate 12, typically by oxidation (silicon dioxide) or by deposition (a high-k insulating material). Thereafter, the material(s) that will constitute the gate electrode structure (e.g., polysilicon or one or more layers of metal) are deposited above the gate insulation layer. Thereafter, the material for the gate cap layer, e.g., silicon nitride, is deposited above the uppermost gate material layer. A patterned layer of photoresist is then formed above the layer of gate cap material and an etching process is performed to pattern the layer of gate cap material. The patterned layer of photoresist is then removed and the gate material(s) are patterned by performing one or more etching processes using the patterned gate cap layer as an etch mask. Thereafter, silicon nitride spacers are formed adjacent the patterned gate electrode structure which, in combination with the gate cap layer, serves to encapsulate and protect the gate electrode.
Over recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the performance of the individual transistor elements but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements (e.g., transistors) formed in the semiconductor material with the metallization layers, an appropriate vertical device level contact structure is provided, a first end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of a transistor, and a second end that is connected to a respective metal line in the so-called M1 metallization layer by a conductive via. As device dimensions have decreased, the conductive device level contact elements have to be provided with critical dimensions on the same order of magnitude. The device level contact elements typically represent plugs or lines, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. For this reason, device level contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate structures. That is, after completing the transistor structure, the silicon nitride materials (the spacer 16 and the gate cap layer 31) that surround and encapsulate the gate electrode structures 30 are effectively used as etch masks for selectively removing the silicon dioxide material between adjacent gate structures in order to expose the source/drain regions of the transistors, thereby providing self-aligned trenches or openings which are substantially laterally delineated by the spacer structures 16 on adjacent gate electrode structures 30.
However, the aforementioned process of forming self-aligned contacts can result in an undesirable loss of the materials that protect the conductive gate electrode, i.e., the gate cap layer and/or the sidewall spacer, as will be explained with reference to
Given that the cap layer 46 and the spacers 48 are attacked in the contact etch process, the thickness of these protective materials must be sufficient such that, even after the contact etch process is completed, there remains sufficient cap layer material and spacer material to protect the gate structures 41. Accordingly, device manufacturers tend to make the cap layers 46 and spacers 48 “extra thick,” i.e., with an additional thickness that may otherwise not be required but for the consumption of the cap layers 46 and the spacers 48 during the contact etch process. In turn, increasing the thickness of such structures, i.e., increasing the thickness of the gate cap layers 46, causes other problems, such as increasing the aspect ratio of the contact opening 54 due to the increased height, increasing the initial gate height, which makes the gate etching and spacer etching processes more difficult, etc.
What is needed in the art is a novel process flow that addresses and corrects or lessens at least some of the problems identified above. Accordingly, the present disclosure is directed to various methods of forming self-aligned device level contact structures on integrated circuit products that may avoid, or at least reduce, the effects of one or more of the problems identified above.
SUMMARY OF THE DISCLOSUREThe following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the subject matter that is described in further detail below. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to integrated circuit products having self-aligned device level contact structures. One illustrative integrated circuit product disclosed herein includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. The disclosed integrated circuit product further includes, among other things, a source/drain region that is positioned between the two laterally spaced-apart transistors, a conformal etch stop layer that is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the sidewall spacer of each of the two laterally spaced-apart transistors, and a self-aligned conductive contact that extends through an opening in the conformal etch stop layer and is conductively coupled to the source/drain region.
In another exemplary embodiment of the present disclosure, an integrated circuit product includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a silicon dioxide gate cap layer positioned above the gate structure, and a silicon nitride sidewall spacer positioned adjacent to sidewalls of the gate structure, wherein the silicon nitride spacer covers a lower sidewall surface portion of the gate cap layer. Each of the two laterally spaced-apart transistors also includes a silicon dioxide spacer cap layer positioned on and in contact with an upper surface of the silicon nitride sidewall spacer, wherein the silicon dioxide spacer cap layer covers an upper sidewall surface portion of the gate cap layer. The illustrative integrated circuit product further includes a layer of silicon dioxide insulating material positioned above each of the two laterally spaced-apart transistors, a source/drain region positioned between the two laterally spaced-apart transistors, and a conformal silicon dioxide etch stop layer that is positioned on and in contact with an upper surface of the source/drain region, on and in contact with a sidewall surface of the silicon nitride sidewall spacer of each of the two laterally spaced-apart transistors, and on and in contact with a sidewall surface of the silicon dioxide spacer cap layer of each of the two laterally spaced-apart transistors. Additionally, the disclosed integrated circuit product includes a self-aligned conductive contact positioned in an opening that extends through the layer of silicon dioxide insulating material and through the conformal silicon dioxide etch stop layer, wherein the self-aligned conductive contact is conductively coupled to the source/drain region.
In yet a further illustrative embodiment, an exemplary integrated circuit product includes, among other things, two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a silicon dioxide gate cap layer positioned above the gate structure, and a silicon nitride sidewall spacer positioned adjacent to sidewalls of the gate structure, wherein the silicon nitride spacer covers a lower sidewall surface portion of the gate cap layer. The disclosed integrated circuit product also includes a layer of silicon dioxide insulating material positioned above each of the two laterally spaced-apart transistors, a silicon nitride liner layer positioned between the layer of silicon dioxide insulating material and at least the silicon dioxide gate cap layer of each of the two laterally spaced-apart transistors, and a source/drain region positioned between the two laterally spaced-apart transistors. Additionally, the illustrative integrated circuit product further includes a conformal silicon dioxide etch stop layer that is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the silicon nitride sidewall spacer of each of the two laterally spaced-apart transistors, as well as a self-aligned conductive contact positioned in an opening that extends through the layer of silicon dioxide insulating material, through the silicon nitride liner layer, and through the conformal silicon dioxide etch stop layer, wherein the self-aligned conductive contact is conductively coupled to the source/drain region.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the claimed invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the claimed invention.
DETAILED DESCRIPTIONVarious illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various systems, structures and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure generally relates to various methods of forming self-aligned device level contact structures on integrated circuit products. The methods and devices disclosed herein may be employed in manufacturing products using a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they may be employed in manufacturing a variety of different devices, e.g., memory products, logic products, ASICs, etc. As will be appreciated by those skilled in the art after a complete reading of the present application, the inventions disclosed herein may be employed in forming integrated circuit products using transistor devices in a variety of different configurations, e.g., planar devices, FinFET devices, nanowire devices, etc. The gate structures for such devices may be formed using either “gate first” or “replacement gate” manufacturing techniques. Thus, the presently disclosed inventions should not be considered to be limited to any particular form of transistors or the manner in which the gate structures of the transistor devices are formed. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail. The various layers of material described below may be formed by any of a variety of different known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. Moreover, as used herein and in the attached claims, the word “adjacent” is to be given a broad interpretation and should be interpreted to cover situations where one feature actually contacts another feature or is in close proximity to that other feature.
As noted above, the subject matter disclosed herein may be employed where the gate structures for the illustrative transistor devices may be formed using well-known “gate first” or “replacement gate” manufacturing techniques. In the example depicted in
The next major process sequence involves formation of the replacement gate structures 124 for the product 100. The replacement gate structures 124 that will be depicted herein are intended to be representative in nature of any type of gate structure that may be employed in manufacturing integrated circuit products using so-called gate-last (replacement-gate) manufacturing techniques. Of course, as noted above, the presently disclosed inventions may be employed in situations where the gate structures for the transistor devices are formed using well-known gate first manufacturing techniques. In the context of an illustrative replacement gate process, with reference to
Thereafter, multiple conductive layers, such as metal layers, were sequentially deposited above the substrate 102 and within the gate cavities 122 such that the gate cavities 122 were substantially overfilled with material. Then, one or more CMP processes were performed to remove excess materials positioned outside of the gate cavities 122. Next, one or more recess etching processes were performed to recess the materials within the gate cavities 122 so as to thereby make room for a gate cap layer. These process operations result in the definition of the illustrative and simplistically depicted replacement gate structures 124B depicted in
An analogous structure to that depicted in
In the example depicted herein, the pitch of the gate structures 124 is such that the final pattern for the contact openings will be defined in the hard mask layer 130 by performing two separate masking and etching processes. Of course, in some applications, the final pattern for the contact openings may be defined in the hard mask layer 130 by performing a single masking and etching process. Accordingly,
One advantage of the presently disclosed subject matter lies in the fact that the process of forming the self-aligned contact openings 140 (see
As noted above, in the example depicted herein, the pitch of the gate structures 124 is such that the final pattern for the contact openings will be defined in the hard mask layer 154 by performing two separate masking and etching processes, just like the process described above for the hard mask layer 130. Accordingly,
The particular embodiments disclosed above are illustrative only, as the claimed invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the claimed invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various structures in this specification and in the attached claims is only used as a shorthand reference to such structures and does not necessarily imply that such structures are formed in that ordered sequence. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. An integrated circuit product, comprising:
- two laterally spaced-apart transistors, each of said two laterally spaced-apart transistors comprising: a gate structure; a gate cap layer positioned above said gate structure; and a sidewall spacer positioned adjacent to sidewalls of said gate structure;
- a source/drain region positioned between said two laterally spaced-apart transistors;
- a conformal etch stop layer positioned on and in contact with an upper surface of said source/drain region and on and in contact with a sidewall surface of said sidewall spacer of each of said two laterally spaced-apart transistors; and
- a self-aligned conductive contact that extends through an opening in said conformal etch stop layer and is conductively coupled to said source/drain region.
2. The integrated circuit product of claim 1, wherein said conformal etch stop layer is a silicon dioxide etch stop layer and said sidewall spacers are silicon nitride sidewall spacers.
3. The integrated circuit product of claim 1, wherein each of said two laterally spaced-apart transistors further comprises a spacer cap layer positioned on and in contact with an upper surface of said sidewall spacer.
4. The integrated circuit product of claim 3, wherein said spacer cap layer covers an upper sidewall surface portion of said gate cap layer and covers an upper sidewall surface portion of a substantially vertically oriented portion of said etch stop layer.
5. The integrated circuit product of claim 3, wherein said self-aligned conductive contact is positioned on and in contact with said upper surface of said source/drain region, said conformal etch stop layer, said spacer cap layers, and said gate cap layers.
6. The integrated circuit product of claim 1, wherein said gate structure of each of said two laterally spaced-apart transistors is a replacement gate structure that comprises a high-k gate insulation layer and a conductive gate electrode comprising at least one work function adjusting metal layer.
7. The integrated circuit product of claim 1, wherein said source/drain region comprises a raised epi semiconductor material that is positioned on and in contact with a lower sidewall surface portion of said sidewall spacer of each of said two laterally spaced-apart transistors.
8. The integrated circuit product of claim 1, further comprising a layer of insulating material positioned above each of said two laterally spaced-apart transistors, wherein said self-aligned conductive contact extends through said layer of insulating material.
9. The integrated circuit product of claim 8, further comprising a liner layer positioned between said layer of insulating material and at least said gate cap layer of each of said two laterally spaced-apart transistors.
10. The integrated circuit product of claim 1, wherein said sidewall spacer of each of said two laterally spaced-apart gate structures is positioned on and in contact with a lower sidewall surface portion of a respective gate cap layer.
11. An integrated circuit product, comprising:
- two laterally spaced-apart transistors, each of said two laterally spaced-apart transistors comprising: a gate structure; a silicon dioxide gate cap layer positioned above said gate structure; a silicon nitride sidewall spacer positioned adjacent to sidewalls of said gate structure, said silicon nitride sidewall spacer covering a lower sidewall surface portion of said gate cap layer; and a silicon dioxide spacer cap layer positioned on and in contact with an upper surface of said silicon nitride sidewall spacer, said silicon dioxide spacer cap layer covering an upper sidewall surface portion of said gate cap layer;
- a layer of silicon dioxide insulating material positioned above each of said two laterally spaced-apart transistors;
- a source/drain region positioned between said two laterally spaced-apart transistors;
- a conformal silicon dioxide etch stop layer positioned on and in contact with an upper surface of said source/drain region, on and in contact with a sidewall surface of said silicon nitride sidewall spacer of each of said two laterally spaced-apart transistors, and on and in contact with a sidewall surface of said silicon dioxide spacer cap layer of each of said two laterally spaced-apart transistors; and
- a self-aligned conductive contact positioned in an opening that extends through said layer of silicon dioxide insulating material and through said conformal silicon dioxide etch stop layer, wherein said self-aligned conductive contact is conductively coupled to said source/drain region.
12. The integrated circuit product of claim 11, wherein said self-aligned conductive contact is positioned on and in contact with said upper surface of said source/drain region, said conformal silicon dioxide etch stop layer, said silicon dioxide spacer cap layers, said silicon dioxide gate cap layers, and said layer of silicon dioxide insulating material.
13. The integrated circuit product of claim 11, wherein said gate structure of each of said two laterally spaced-apart transistors is a replacement gate structure that comprises a high-k gate insulation layer and a conductive gate electrode comprising at least one work function adjusting metal layer.
14. The integrated circuit product of claim 11, wherein said source/drain region comprises a raised epi semiconductor material that is positioned on and in contact with a lower sidewall surface portion of said silicon nitride sidewall spacer of each of said two laterally spaced-apart transistors.
15. An integrated circuit product, comprising:
- two laterally spaced-apart transistors, each of said two laterally spaced-apart transistors comprising: a gate structure; a silicon dioxide gate cap layer positioned above said gate structure; and a silicon nitride sidewall spacer positioned adjacent to sidewalls of said gate structure, said silicon nitride sidewall spacer covering a lower sidewall surface portion of said gate cap layer;
- a layer of silicon dioxide insulating material positioned above each of said two laterally spaced-apart transistors;
- a silicon nitride liner layer positioned between said layer of silicon dioxide insulating material and at least said silicon dioxide gate cap layer of each of said two laterally spaced-apart transistors;
- a source/drain region positioned between said two laterally spaced-apart transistors;
- a conformal silicon dioxide etch stop layer positioned on and in contact with an upper surface of said source/drain region and on and in contact with a sidewall surface of said silicon nitride sidewall spacer of each of said two laterally spaced-apart transistors; and
- a self-aligned conductive contact positioned in an opening that extends through said layer of silicon dioxide insulating material, through said silicon nitride liner layer, and through said conformal silicon dioxide etch stop layer, wherein said self-aligned conductive contact is conductively coupled to said source/drain region.
16. The integrated circuit product of claim 15, wherein each of said two laterally spaced-apart transistors further comprises a silicon dioxide spacer cap layer positioned on and in contact with an upper surface of said silicon nitride sidewall spacer.
17. The integrated circuit product of claim 16, wherein said spacer cap layer of each of said two laterally spaced-apart transistors covers an upper sidewall surface portion of a respective gate cap layer and covers an upper sidewall surface portion of a substantially vertically oriented portion of said conformal silicon dioxide etch stop layer.
18. The integrated circuit product of claim 16, wherein said self-aligned conductive contact is positioned on and in contact with said upper surface of said source/drain region, said conformal silicon dioxide etch stop layer, said silicon dioxide spacer cap layers, said silicon nitride liner layer, and said layer of silicon dioxide insulating material.
19. The integrated circuit product of claim 15, wherein said gate structure of each of said two laterally spaced-apart transistors is a replacement gate structure that comprises a high-k gate insulation layer and a conductive gate electrode comprising at least one work function adjusting metal layer.
20. The integrated circuit product of claim 15, wherein said source/drain region comprises a raised epi semiconductor material that is positioned on and in contact with a lower sidewall surface portion of said silicon nitride sidewall spacer of each of said two laterally spaced-apart transistors.
Type: Application
Filed: Mar 27, 2017
Publication Date: Jul 20, 2017
Inventors: Chanro Park (Clifton Park, NY), Ruilong Xie (Niskayuna, NY), Min Gyu Sung (Latham, NY), Hoon Kim (Clifton Park, NY)
Application Number: 15/470,006