Circuit with Impedance Elements Connected to Sources and Drains of PMOSFET Headers
A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state.
To reduce power consumption, a circuit may employ header pMOSFETs (Metal Oxide Semiconductor Field Effect Transistor) in power gating modules, whereby power may be reduced to various sub-blocks of the circuit when not in operation. However, there may be unwanted IR (current-resistance product) voltage drops across the header pMOSFETs when various driven sub-blocks are dynamically switching on and off.
Implementations of various techniques are described herein with reference to the accompanying drawings. It should be understood, however, that the accompanying drawings illustrate only various implementations described herein and are not meant to limit implementations of various techniques described herein.
In the description that follows, the scope of the term “some implementations” is not to be so limited as to mean more than one implementation, but rather, the scope may include one implementation, more than one implementation, or perhaps all implementations.
Implementations described herein include pMOSFETs in an integrated circuit that may be configured as header pMOSFETs for power gating or as decoupling pMOSFETs to mitigate IR voltage drops.
A power gating module 106 includes one or more header switches to implement power gating to the functional block 102. In practice, a header switch may comprise one or more pMOSFETs, and will be referred to as a header pMOSFET. A controller 108 provides one or more control signals to the power gating module 106. The one or more control signals may be gate voltage signals applied to the gate terminals of various header pMOSFETs within the power gating module 106.
A supply rail 109 provides power to various modules illustrated in
A power decoupling module 110 includes one or more pMOSFETs configured as decoupling capacitors, where a decoupling capacitor can be referred to as a decoupling pMOSFET. The decoupling pMOSFETs in the power decoupling module 110 are connected between the functional block 104 and the supply rail 109, and mitigate voltage drop in the supply voltage provided to the functional block 104, where a voltage drop may be incurred as various transistors in the functional block 104 switch from OFF to ON during normal operation.
When a decoupling pMOSFET is configured as a decoupling capacitor, the pMOSFET has its gate terminal held at a logic voltage level LOW, which in practice can be at or near a ground or substrate voltage, denoted as Vss and labeled 112 in
The source terminal of a decoupling pMOSFET is connected (or shorted) to its drain terminal. The connection may be implemented as a metal interconnect in a metal layer or a polysilicon diffusion. In
In the implementation of
In the case where the fuse element is a fuse, the fuse is put into a high impedance state by blowing the fuse (open circuit), whereas in the case of an antifuse the fuse element is initially in a high impedance state. As an example, the fuse element 406 comprises metallization where a laser is used to cut away a portion of the metallization to create an open circuit.
The state of the programmable impedance elements for the implementation illustrated in
The header and decoupling pMOSFETs described in the implementations may be located in various sub-blocks of a memory circuit as illustrated in
It should be appreciated that the implementation illustrated in
Furthermore, the implementation illustrated in
In step 702, a circuit instance is generated in which a plurality of pMOSFET may be configured as header pMOSFET or decoupling pMOSFETs. The source terminals of the pMOSFET are connected to one or more supply rails. In step 704, the circuit instance is further generated to include impedance elements, where corresponding to each configurable pMOSFET is an impedance element connected to its source terminal and its drain terminal. For example, the fuse element 406 or the programmable resistor 506 are examples of an impedance element.
In step 706, the pMOSFETs are configured as header pMOSFETs or decoupling pMOSFETs, depending upon a set of requirements that may be provided by a customer. For the case in which the pMOSFETs are configured as header pMOSFETs, in step 708 the impedance elements are configured to be in a high impedance state, and in step 710 the pMOSFETs are configured so that their gate terminals are connected to a controller, for example the controller 108 of
For the case in which the pMOSFETs are configured as decoupling pMOSFETs, in step 712 the impedance elements are configured to be in a low impedance state. Furthermore, in step 714 the pMOSFETs are configured so that their gate terminals are connected to a LOW voltage, meaning that when the circuit is in operation, a voltage having the logic level LOW is provided to the gate terminals.
In step 716, one or more lithography masks based upon the generated circuit instance are fabricated so that a wafer make be fabricated with circuits according to the circuit instance.
Upon fabrication of the integrated circuit, various steps may be taken depending upon the type of impedance elements and whether the customer desires the pMOSFETs to be configured as header pMOSFETs or decoupling pMOSFETs. This is represented by step 809, where the impedance elements may be configured in several ways indicated by steps 810, 812, and 814. In step 810, the impedance elements may be fuse elements, where the state of the fuse elements are set according to a set of requirements, such as customer requirements. For example, as discussed previously, a fuse element may be set to a high impedance state if its corresponding pMOSFET is to be configured as a header pMOSFET, and the fuse element may be set to a low impedance state if its corresponding pMOSFET is to be configured as a decoupling pMOSFET.
In step 812, the impedance elements may be interconnects, in which case those interconnects for which their corresponding pMOSFETs are to be configured as header pMOSFETs are cut. In step 814, the impedance elements are programmable resistors, and a programmable resistor is programmed to be either in a high impedance or low impedance state so that its corresponding pMOSFET is configured as a header pMOSFET or decoupling pMOSFET, respectively.
In some implementations, all configurable pMOSFETs fabricated according to the steps 702 and 704 or the steps 802 and 804 may be configured as either header pMOSFET or decoupling pMOSFETs. Other implementations may be such that the pMOSFETs in an integrated circuit, fabricated according to the steps 702 and 704 or the steps 802 and 804, may be configured so that some of the pMOSFETs are configured as header pMOSFETs and some of the pMOSFETs are configured as decoupling pMOSFETs.
Many of the steps illustrated in the flow diagrams of
Implementations of various technologies described herein may be operational with numerous general purpose or special purpose computing system environments or configurations. Examples of computing systems, environments, and/or configurations that may be suitable for use with the various technologies described herein include, but are not limited to, personal computers, server computers, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, smart phones, tablets, wearable computers, cloud computing systems, virtual computers, marine electronics devices, and the like.
The various technologies described herein may be implemented in the general context of computer-executable instructions, such as program modules, being executed by a computer. Program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Further, each program module may be implemented in its own way, and all need not be implemented the same way. While program modules may execute on a single computing system, it should be appreciated that, in some implementations, program modules may be implemented on separate computing systems or devices adapted to communicate with one another. A program module may also be some combination of hardware and software where particular tasks performed by the program module may be done either through hardware, software, or some combination of both.
The various technologies described herein may be implemented in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network, e.g., by hardwired links, wireless links, or various combinations thereof. In a distributed computing environment, program modules may be located in both local and remote computer storage media including, for example, memory storage devices and similar.
Further, the discussion provided herein may be considered directed to certain specific implementations. It should be understood that the discussion provided herein is provided for the purpose of enabling a person with ordinary skill in the art to make and use any subject matter defined herein by the subject matter of the claims. It should be intended that the subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort may be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having benefit of this disclosure.
Described herein are various implementations of a method comprising: generating a circuit instance to include a plurality of pMOSFET instances, wherein each pMOSFET instance has a source terminal instance connected to one or more supply rail instances; generating the circuit instance to include impedance element instances, wherein each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance; depending upon a set of requirements, generating the circuit instance to indicate that one or more of the impedance element instances are in a high impedance state or a low impedance state; and fabricating one or more masks according to the generated circuit instance.
Described herein are various implementations of a method comprising: generating a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances; generating the circuit instance to include impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance; fabricating one or more masks according to the generated circuit instance; fabricating an integrated circuit based upon the one or more masks, the integrated circuit comprising pMOSFETs according to the pMOSFET instances and impedance elements according to the impedance element instances; and after fabricating the integrated circuit, configuring each impedance element to have a high impedance or a low impedance.
Described herein are various implementations of a memory circuit comprising: one or more supply rails; a word driver; a plurality of input/output circuits; a plurality of column muxes; a plurality of pMOSFETs, each pMOSFET in the plurality of pMOSFETs having a source terminal connected to at least one of the one or more supply rails, a gate terminal, and a drain terminal coupled to the word driver, an input/output circuit, or a column mux; a plurality of impedance elements, each impedance element connected to a source terminal and a drain terminal of a corresponding pMOSFET in the plurality of pMOSFETs, wherein each impedance element is configurable to have a low impedance or a high impedance; and a controller to provide a control voltage, wherein each pMOSFET in the plurality of pMOSFETs is configurable to have its gate terminal connected to the controller or held at a LOW voltage when the circuit is in operation.
Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. Numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure details of the implementations.
If one or more circuits are used to realize some or all instances of an implementation, reference may be made to a node or terminal of a circuit or circuit element as an input port or an output port. For a circuit in which a port is a two terminal structure (e.g., circuits modeled as lumped-parameter systems), a recited node or terminal forms one terminal of the two terminal structure, where it is understood that a ground rail (or substrate) serves as another terminal of the two terminal structure.
It should also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element. The first element and the second element are both elements, respectively, but they are not to be considered the same element.
The terminology used in the description of the disclosure provided herein is for the purpose of describing particular implementations and is not intended to limit the disclosure provided herein. As used in the description of the disclosure provided herein and appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify a presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context. The terms “up” and “down”; “upper” and “lower”; “upwardly” and “downwardly”; “below” and “above”; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some implementations of various technologies described herein.
While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described herein are disclosed as example forms of implementing the claims.
Claims
1. A method comprising:
- generating a circuit instance to include a plurality of pMOSFET instances, wherein each pMOSFET instance has a source terminal instance connected to one or more supply rail instances;
- generating the circuit instance to include impedance element instances, wherein each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance;
- depending upon a set of requirements, generating the circuit instance to indicate that one or more of the impedance element instances are in a high impedance state or a low impedance state; and
- fabricating one or more masks according to the generated circuit instance.
2. The method as set forth in claim 1, further comprising:
- generating the circuit instance to include a controller instance coupled to gate terminals of those pMOSFET instances for which their corresponding impedance element instances are in a high impedance state; and
- generating the circuit instance to indicate a LOW voltage on gate terminals of those pMOSFET instances for which their corresponding impedance element instances are in a low impedance state.
3. The method as set forth in claim 2, wherein the circuit instance includes a memory instance.
4. The method as set forth in claim 3, wherein the memory instance includes a word driver instance, wherein connected to the word driver instance is at least one of the pMOSFET instances.
5. The method as set forth in claim 3, wherein the memory instance includes a plurality of column mux instances, where connected to each column mux instance is at least one of the pMOSFET instances.
6. The method as set forth in claim 3, wherein the memory instance includes a plurality of input/output instances, wherein connected to each input/output instance is at least one of the pMOSFET instances.
7. The method as set forth in claim 1, wherein all of the impedance element instances are indicated to either have a high impedance or a low impedance.
8. The method as set forth in claim 1, wherein at least one of the impedance element instance is a fuse element instance.
9. The method as set forth in claim 1, wherein at least one of the impedance element instance is an interconnect instance.
10. The method as set forth in claim 1, wherein at least one of the impedance element instance is a programmable resistor instance.
11. The method as set forth in claim 1, wherein the circuit instance is represented by a data structure stored in a computer memory.
12. A method comprising:
- generating a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances;
- generating the circuit instance to include impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance;
- fabricating one or more masks according to the generated circuit instance;
- fabricating an integrated circuit based upon the one or more masks, the integrated circuit comprising pMOSFETs according to the pMOSFET instances and impedance elements according to the impedance element instances; and
- after fabricating the integrated circuit, configuring each impedance element to have a high impedance or a low impedance.
13. The method as set forth in claim 12, wherein in fabricating the integrated circuit, a controller is coupled to gate terminals of those pMOSFETs for which their corresponding impedance elements are in a high impedance state, and wherein a LOW voltage is provided to gate terminals of those pMOSFETs for which their corresponding impedance elements are in a low impedance state.
14. The method as set forth in claim 12, wherein the integrated circuit includes a memory circuit.
15. The method as set forth in claim 14, wherein the memory circuit includes a word driver, wherein connected to the word driver is at least one of the pMOSFETs.
16. The method as set forth in claim 14
- wherein the memory circuit includes a plurality of column muxes, where connected to each column mux is at least one of the pMOSFETs; and
- wherein the memory instance includes a plurality of input/output circuits, wherein connected to each input/output circuit is at least one of the pMOSFETs.
17. The method as set forth in claim 12, wherein each impedance element is an interconnect, the method further comprising:
- after fabricating the integrated circuit, cutting each interconnect.
18. The method as set forth in claim 12, wherein each impedance element is a fuse element, the method further comprising:
- after fabricating the integrated circuit, setting each fuse element to a low impedance or a high impedance.
19. The method as set forth in claim 12, wherein each impedance element is a programmable resistor, the method further comprising:
- after fabricating the integrated circuit, programming each programmable resistor to a low impedance or a high impedance.
20. A memory circuit comprising:
- one or more supply rails;
- a word driver;
- a plurality of input/output circuits;
- a plurality of column muxes;
- a plurality of pMOSFETs, each pMOSFET in the plurality of pMOSFETs having a source terminal connected to at least one of the one or more supply rails, a gate terminal, and a drain terminal coupled to the word driver, an input/output circuit, or a column mux;
- a plurality of impedance elements, each impedance element connected to a source terminal and a drain terminal of a corresponding pMOSFET in the plurality of pMOSFETs, wherein each impedance element is configurable to have a low impedance or a high impedance; and
- a controller to provide a control voltage, wherein each pMOSFET in the plurality of pMOSFETs is configurable to have its gate terminal connected to the controller or held at a LOW voltage when the circuit is in operation.
Type: Application
Filed: Jun 28, 2017
Publication Date: Jan 3, 2019
Inventors: Andy Wangkun Chen (Austin, TX), Yew Keong Chong (Austin, TX), Yicong Li (Austin, TX), Hsin-Yu Chen (Austin, TX), Sriram Thyagarajan (Austin, TX)
Application Number: 15/636,428