3DIC STRUCTURE WITH PROTECTIVE STRUCTURE AND METHOD OF FABRICATING THE SAME AND PACKAGE
Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The metal circuit structure is disposed over a back side of the second die. The protective structure is disposed within the back side of the second die and separates one of a plurality of through-substrate vias (TSVs) of the second die from the metal circuit structure.
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In recent years, the semiconductor industry has experienced rapid growth due to continuous improvement in integration density of various electronic components, e.g., transistors, diodes, resistors, capacitors, etc. Such improvement in integration density is mostly attributed to successive reductions in minimum feature sizes, which allows more components to be integrated into a given area.
These smaller electronic components also require smaller packages that occupy less area than previous packages. Some types of packages for semiconductors include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices. Some 3DICs are prepared by placing chips over chips on a semiconductor wafer level. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked chips. However, there are quite a few challenges to be handled for the technology of 3DICs.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
Referring to
As shown in
In some embodiments, the semiconductor substrate 102 may include silicon or other semiconductor materials. Alternatively, or additionally, the first semiconductor substrate 102 may include other elementary semiconductor materials such as germanium. In some embodiments, the first semiconductor substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide or indium phosphide. In some embodiments, the first semiconductor substrate 102 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the first semiconductor substrate 102 includes an epitaxial layer. For example, the first semiconductor substrate 102 has an epitaxial layer overlying a bulk semiconductor.
In some embodiments, the first device layer 103 is formed over the first semiconductor substrate 102 in a front-end-of-line (FEOL) process. The first device layer 103 includes a wide variety of devices. In some embodiments, the devices comprise active components, passive components, or a combination thereof. In some embodiments, the devices may include integrated circuits devices. The devices are, for example, transistors, capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the first device layer 103 includes a gate structure, source and drain regions, and isolation structures, such as shallow trench isolation (STI) structures (not shown). In the first device layer 103, various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors or memories and the like, may be formed and interconnected to perform one or more functions. Other devices, such as capacitors, resistors, diodes, photodiodes, fuses and the like may also be formed over the first semiconductor substrate 102. The functions of the devices may include memory, processors, sensors, amplifiers, power distribution, input/output circuitry, or the like.
Referring to
Referring to
Referring to
In some embodiments, the first bonding metal layers 118 and 120 may include copper, copper alloys, nickel, aluminum, tungsten, a combination of thereof. In some embodiments, the first bonding metal layers 118 and 120 are formed at the same time with the same material. In some other embodiments, the first bonding metal layers 118 and 120 are successively formed with different materials. The first bonding metal layers 118 and 120 may be formed by depositing a conductive material in trenches and via holes (not shown) in the first bonding dielectric layer 116 and then removing the conductive material over a top surface of the first bonding dielectric layer 116 by a planarization process such as a CMP process. After the planarization process, the top surface of the first bonding dielectric layer 116, the top surfaces of the first bonding metal layers 118 and 120 are substantially coplanar.
Referring to
In some embodiments, one of the first die 100 and the second die 200 may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chips, for example. In some alternative embodiments, the first die 100 and the second die 200 may include the same function or different functions. The die stack structure 10 illustrated in
Referring to
In some embodiments, the second bonding metal layer 218 may include copper, copper alloys, nickel, aluminum, tungsten, a combination of thereof. The second bonding metal layer 218 may be formed by depositing a conductive material in trenches and via holes (not shown) in the second bonding dielectric layer 216 and then removing the conductive material over a top surface of the second bonding dielectric layer 216 by a planarization process such as a CMP process. After the planarization process, the top surface of the second bonding dielectric layer 216 and the top surface of the second bonding metal layer 218 are substantially coplanar.
Referring to
The first bonding structure 114 and the second bonding structure 214 are hybrid bonded together by the application of pressure and heat. It is noted that the hybrid bonding involves at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding such as dielectric-to-dielectric bonding or fusion bonding. As shown in
In addition, as shown in
After performing the thinning process, the back surface 202b of the second semiconductor substrate 202 is lower than the top surfaces 205s of the TSVs 205 to make sure the TSVs 205 being able to be connected to the to-be-formed metal circuit structure 400 (as shown in
A planarization process (or referred as a first planarization process) is then performed. In some embodiments, the planarization process is a CMP process. After performing the planarization process, the excess dielectric layer 226, the excess nitride layer 224, the excess oxide layer 222, and the excess nitride layer 220 are removed, so that the top surfaces 205s of the TSVs 205 and the top surface 222t of the remaining oxide layer 222 are exposed, as shown in
It should be noted that a recess R1 is formed in the back side 200b of the second die 200 after performing the planarization process (or referred as the first planarization process) or the thinning process. The recess R1 may be various defects, such as cracks, sharp morphology, bulge, etc. The recess R1 is formed because some undesired particles may be dropped on the to-be-ground surface, the planarization process or the thinning process is then performed to damage the back side 200b of the second die 200. As shown in
Referring to
In addition, in some embodiments, before the conformal layer 305 is formed, a nitride layer 304 (e.g., silicon nitride layer) is formed on the second die 200. In some embodiments, the nitride layer 304 is formed by a suitable deposition process, such as a CVD process or ALD process and a thickness of the nitride layer 304 is 300 Å to 1000 Å. In alternative embodiments, the thickness of the conformal layer 305 is greater than the thickness of the nitride layer 304. In other embodiments, the nitride layer 304 and the conformal layer 305 include the same material or different materials.
Referring to
After forming the filling layer 306, a mask pattern 307 is formed over the filling layer 306. In some embodiments, the mask pattern 307 includes photoresist and is formed by a suitable process, such as a spin coating and a photolithography process. After the mask pattern 307 is formed, an etching process is performed by using the mask pattern 307 as etching mask to remove portions of the filling layer 306, the conformal layer 305, the nitride layer 304, the dielectric layer 226, the nitride layer 224, the oxide layer 222, and the nitride layer 220, so that an opening 308 is formed. As shown in
Referring to
Referring to
Referring to
After the metal feature 404 is formed, a passivation layer 406 is formed to cover the dielectric layer 402 and expose a portion of the metal feature 404. In some embodiments, the passivation layer 406 includes silicon oxide, silicon nitride, benzocyclobutene (BCB) polymer, polyimide (PI), polybenzoxazole (PBO) or a combination thereof and is formed by a suitable process such as spin coating, CVD or the like. A bonding pad 408 is formed over the passivation layer 408 and extends to cover the metal feature 404. A material of the bonding pad 408 is different from the material of the first metal feature 404. In some embodiments, the material of the bonding pad 408 is softer than the material of the first metal features 404. In some embodiments, the bonding pad 408 includes a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof. The bonding pad 408 may be formed by depositing a metal material layer through a suitable process such as electro-chemical plating process, CVD, atomic layer deposition (ALD), PVD or the like, and then patterning the metal material layer.
It should be noted that the protective structure 300 filled in the recess R1 is disposed between the TSV 205b of the second die 200 and the metal feature 404 of the metal circuit structure 400, so as to separate or electrically isolate the TSV 205b of the second die 200 from the metal feature 404 of the metal circuit structure 400. As shown in
Referring to
Referring to
Referring to
In the embodiment, the 3DIC structure 4 further includes a plurality of connectors 18 and a passivation layer 19. The connectors 18 are formed over and electrically connected to the bonding pads 408 not covered by the passivation layer 410. Other components below the bonding pads 408, such as the dielectric layer 402 and the metal feature 404 shown in
Referring to
In other words, the redistribution layer RDL1 penetrates through the polymer layer PM1 and is electrically connected to the connectors 18 of the 3DIC structure 4 and the conductive posts 14. The redistribution layer RDL2 penetrates through the polymer layer PM2 and is electrically connected to the redistribution layer RDL1. The redistribution layer RDL3 penetrates through the polymer layer PM3 and is electrically connected to the redistribution layer RDL2. The redistribution layer RDL4 penetrates through the polymer layer PM4 and is electrically connected to the redistribution layer RDL3. In some embodiments, each of the polymer layers PM1, PM2, PM3 and PM4 includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. In some embodiments, each of the redistribution layers RDL1, RDL2, RDL3 and RDL4 includes conductive materials. The conductive materials include metal such as copper, nickel, titanium, a combination thereof or the like, and are formed by an electroplating process. In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes a seed layer (not shown) and a metal layer formed thereon (not shown). The seed layer may be a metal seed layer such as a copper seed layer. In some embodiments, the seed layer includes a first metal layer such as a titanium layer and a second metal layer such as a copper layer over the first metal layer. The metal layer may be copper or other suitable metals. In some embodiments, the redistribution layers RDL1, RDL1, RDL3 and RDL4 respectively includes a plurality of vias and a plurality of traces connected to each other. The vias connects the traces, and the traces are respectively located on the polymer layers PM1, PM2, PM3 and PM 4, and are respectively extending on the top surface of the polymer layers PM1, PM2, PM3 and PM4.
In some embodiments, the topmost redistribution layer RDL4 includes RDL4a and RDL4b. The redistribution layer RDL4a is also referred as under-ball metallurgy (UBM) layer for ball mounting. The redistribution layer RDL4b may be micro bump for connecting to an integrated passive device (IPD) 26 formed in the subsequent process.
Thereafter, a plurality of connectors 24 are formed over and electrically connected to the redistribution layer RDL4a of the redistribution layer structure 23. In some embodiments, the connectors 24 are made of a conductive material with low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi or an alloy thereof, and are formed by a suitable process such as evaporation, plating, ball drop, or screen printing. An IPD 26 is formed over and electrically connected to the redistribution layer RDL4b of the redistribution layer structure 23 through the solder bumps 28. The IPD 26 may be a capacitor, a resistor, an inductor or the like, or a combination thereof. The number of the IPD 26 is not limited to that is shown in
As shown in
According to some embodiments, a three-dimensional integrated circuit (3DIC) structure includes a die stack structure, a metal circuit structure, and a protective structure. The first die has a front side and a back side and a second die has a front side and a back side. The front side of the first die is bonded to the front side of the second die. The second die includes a plurality of through-substrate vias (TSVs). The metal circuit structure is disposed over the back side of the second die. The protective structure is disposed within the back side of the second die and separates one of the plurality of TSVs from the metal circuit structure.
According to some embodiments, a method of manufacturing a 3DIC structure includes the following steps. A die stack structure including a first die and a second die face-to-face bonded together is formed. A first planarization process is performed to expose a plurality of through-substrate vias (TSVs) of the second die at a back side of the second die. The second die has a recess that extends into one of the plurality of TSVs of the second die. A protective structure is formed in the recess with a conformal layer. A metal circuit structure is formed over the back side of the second die to electrically connected to the die stack structure through another of the plurality of TSVs.
According to some embodiments, a package includes a 3DIC structure, an insulating encapsulation, a redistribution layer (RDL) structure, and a plurality of connectors. The 3DIC structure includes a die stack structure, a metal circuit structure, and a protective structure between the die stack structure and the metal circuit structure. The metal circuit structure is electrically connected to the die stack structure through one of a plurality of through-substrate vias (TSVs) of the die stack structure. The protective structure separates and electrically isolates one of a TSVs of the die stack structure from the metal circuit structure. The insulating encapsulation laterally encapsulates the 3DIC structure. The RDL structure is disposed over the 3DIC structure and the insulating encapsulation. The plurality of connectors are disposed over and electrically connected to the 3DIC structure through the RDL structure.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A three-dimensional integrated circuit (3DIC) structure, comprising:
- a die stack structure comprising a first die having a front side and a back side and a second die having a front side and a back side, the front side of the first die bonded to the front side of the second die, the second die including a plurality of through-substrate vias (TSVs);
- a metal circuit structure disposed over the back side of the second die; and
- a first protective structure disposed within the back side of the second die and separating and electrically isolating one of the plurality of TSVs of the second die from the metal circuit structure.
2. The 3DIC structure of claim 1, wherein a top surface of the first protective structure and the back side of the second die are substantially coplanar.
3. The 3DIC structure of claim 1, wherein the first protective structure comprises a conformal layer.
4. The 3DIC structure of claim 1, wherein the first protective structure comprises a composite structure comprising a conformal layer and a filling layer disposed over the conformal layer, and the conformal layer and the filling layer are formed of different materials.
5. The 3DIC structure of claim 1, wherein the die stack structure further comprises a hybrid bonding structure disposed between the first die and the second die.
6. The 3DIC structure of claim 5, further comprising a second protective structure disposed within the back side of the second die, wherein the first protective structure is in direct contact with one of the plurality of TSVs and the second protective structure is spaced apart from the plurality of TSVs.
7. The 3DIC structure of claim 5, wherein the first protective structure extends from the back side of the second die into the hybrid bonding structure.
8. The 3DIC structure of claim 1, wherein another of the plurality of TSVs is electrically connected to the metal circuit structure, and a top surface of the one of the plurality of TSVs of the second die is lower than a top surface of the another of the plurality of TSVs of the second die.
9. The 3DIC structure of claim 1, further comprising:
- a dielectric layer, laterally encapsulating the second die; and
- a through-dielectric via (TDV), disposed in the dielectric layer and electrically connected to the first die and the metal circuit structure.
10. The 3DIC structure of claim 9, wherein a top surface of the dielectric layer, a top surface of TDV, the top surface of the first protective structure and the back side of the second die are substantially coplanar.
11. The 3DIC structure of claim 1, wherein the die stack structure comprises a chip-on-wafer (CoW) structure, a chip-on-chip structure, a die-on-die structure or a combination thereof.
12. A method of manufacturing a 3DIC structure, comprising:
- forming a die stack structure comprising a first die and a second die face-to-face bonded together;
- performing a first planarization process to expose a plurality of through-substrate vias (TSVs) of the second die at a back side of the second die, wherein the back side of the second die has a first recess that extends into one of the plurality of TSVs of the second die;
- filling a protective structure in the first recess with a conformal layer; and
- forming a metal circuit structure over the back side of the second die to electrically connected to the die stack structure through another of the plurality of TSVs, wherein the protective structure electrically isolates the one of the plurality of TSVs of the second die from the metal circuit structure.
13. The method of claim 12, wherein the filling the protective structure in the first recess comprises:
- performing an atomic layer deposition (ALD) process to form the conformal layer over the back side of the second die, wherein the conformal layer completely covers a surface of the first recess;
- performing a chemical vapor deposition (CVD) process to forming a filling layer over the conformal layer; and
- performing a second planarization process to expose another of the plurality of TSVs of the second die.
14. The method of claim 12, wherein the forming the die stack structure comprises:
- providing the first die and the second die; and
- forming a hybrid bonding structure between the first die and the second die to bond the first die and the second die.
15. The method of claim 14, wherein the back side of the second die includes a second recess after performing the first planarization process, the first and second recesses extend along a direction from the back side of the second die toward the hybrid bonding structure, and the second recess is spaced apart from the plurality of TSVs of the second die.
16. The method of claim 14, wherein the first recess extends from the back side of the second die into the hybrid bonding structure after performing the first planarization process.
17. The method of claim 12, wherein a top surface of the one of the plurality of TSVs of the second die is lower than a top surface of the another of the plurality of TSVs of the second die after performing the first planarization process.
18. The method of claim 12, wherein a top surface of the protective structure and the back side of the second die are substantially coplanar after performing the second planarization process.
19. A package, comprising:
- a 3DIC structure comprising a die stack structure, a metal circuit structure, and a protective structure between the die stack structure and the metal circuit structure, wherein the metal circuit structure is electrically connected to the die stack structure through one of a plurality of through-substrate vias (TSVs) of the die stack structure, and the protective structure separates and electrically isolates another of the plurality of TSVs of the die stack structure from the metal circuit structure;
- an insulating encapsulation, laterally encapsulating the 3DIC structure;
- a redistribution layer (RDL) structure, disposed over the 3DIC structure and the insulating encapsulation; and
- a plurality of connectors, disposed over and electrically connected to the 3DIC structure through the RDL structure.
20. The package of claim 19, wherein the die stack structure comprises a first die and a plurality of second dies arranged in parallel over the first die.
Type: Application
Filed: Jun 25, 2018
Publication Date: Dec 26, 2019
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. (Hsinchu)
Inventors: Hsien-Wei Chen (Hsinchu City), Ching-Jung Yang (Taoyuan City), Ming-Fa Chen (Taichung City)
Application Number: 16/016,670