SEMICONDUCTOR DEVICE PACKAGE
A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.
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This application is a continuation of U.S. patent application Ser. No. 15/250,713 filed Aug. 29, 2016, which claims the benefit of and priority to U.S. Provisional Patent Application No. 62/257,488 filed Nov. 19, 2015 to Chiu et al., titled “Semiconductor Device Package,” the contents of which are incorporated herein by reference in their entirety.
BACKGROUND 1. Technical FieldThe present disclosure relates to a semiconductor device package and a method of manufacturing the same. In particular, the present disclosure relates to a semiconductor device package structure including an improved conductive base and a method for manufacturing the same.
2. Description of the Related ArtA semiconductor device package structure includes a semiconductor die bonded to a leadframe. An insulating material (e.g., pre-impregnated composite fiber (p.p.)) can be used to cover and protect the semiconductor die and leadframe. However, the semiconductor die may be cracked during a process of laminating the insulating material to the semiconductor die and the leadframe. Thus, an improved technique for forming the semiconductor device package would be beneficial.
SUMMARYIn one or more embodiments, a semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.
In one or more embodiments, a semiconductor device package includes: (1) a conductive base including (a) a sidewall; (b) a first surface and a second surface opposite the first surface; and (c) a cavity defined from the first surface of the conductive base, the cavity having a bottom surface, a sidewall and a depth; and (2) a semiconductor die disposed on the bottom surface of the cavity and having a first thickness, wherein at least one corner of the conductive base is smoothed.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. Embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings.
DETAILED DESCRIPTIONDescribed in this disclosure are techniques for providing devices with reduced package sizes. In particular, the present disclosure relates to a semiconductor device package structure including an improved conductive base for avoiding the cracking of the semiconductor die during a process of laminating the insulating material.
Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated by such arrangement.
The conductive base 101 includes an upper surface 101u and a surface 101b opposite to the upper surface 101u. The material of the conductive base 101 may be, for example, copper or other metal, or a metal alloy, or other conductive material. In some embodiments, the conductive base 101 may be a die paddle. In some embodiments, the conductive base 101 includes one or more smoothed corners 32 of the conductive base 101 to reduce or minimize stress at the respective corners 32 during a manufacturing operation relative to the formation of the protection layer 70. The smoothing of the corners 32 may further be designed in a manner to redistribute stress across the conductive base 101, such as to more evenly apportion stress across the conductive base 101, or to transfer a stress point from one portion of the conductive base 101 to another portion of the conductive base 101. Accordingly, different corners 32 may have different radii of curvature and/or may form different angles of taper with respect to the upper surface 101u of the conductive base 101. The conductive base 101 includes one or more protrusions 80.
A cavity 30 is recessed from the upper surface 101u of the conductive base 101. The cavity 30 has a bottom surface 301, sidewalls 302 and a depth D. The cavity 30 is defined by the sidewalls 302 and the bottom surface 301. In some embodiments, the cavity 30 is defined by three or four sidewalls 302. In some embodiments, the depth D may be about 80 micrometers (μm) to about 120 μm. A semiconductor die 20 is disposed on the bottom surface 301 of the cavity 30. The cavity 30 is formed in the conductive base 101 to receive the semiconductor die 20 to decrease the package thickness. A compact three-dimensional (3-D) embedded package can be achieved by a design with the cavity 30.
In some embodiments, the semiconductor die 20 has an upper surface 201 and a surface 202 opposite the upper surface 201. The surface 202 of the semiconductor die 20 is bonded to the bottom surface 301 of the cavity 30 through the conductive adhesive layer 50. The conductive adhesive layer 50 may be, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material), or other conductive material.
The conductive adhesive layer 50 is disposed between the surface 202 of the semiconductor die 20 and the bottom surface 301 of the cavity 30. In some embodiments, the conductive adhesive layer 50 completely covers the bottom surface 301 of the cavity 30, and extends to and contacts at least one sidewall 302 of the cavity 30. The conductive adhesive layer 50 may contact a portion of one or more sidewalls of the semiconductor die 20. The conductive adhesive layer 50 attaches the semiconductor die 20 to the conductive base 101. In the embodiment illustrated in
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The protection layer 70 is disposed on the conductive base 101 and on the semiconductor die 20. The protection layer 70 includes an upper surface 701 and a surface 702 opposite to the upper surface 701. In some embodiments, the material of the protection layer 70 is a polypropylene resin; however, other suitable materials may be additionally or alternatively used. As noted above, the upper surface 201 of the semiconductor die 20 can be higher than the upper surface 101u of the conductive base 101 (e.g., as illustrated in the embodiment of
The interconnection structure 42 is electrically connected to pads on the upper surface 201 of the semiconductor die 20. The interconnection structure 40 is electrically connected to the upper surface 101u of the conductive base 101. The interconnection structure 44 is electrically connected to the upper surface 101u of the conductive base 101 and to a pad on the upper surface 201 of the semiconductor die 20. In some embodiments, the interconnection structures 40, 42 and 44 are vias formed through the protection layer 70. A material of interconnection structures 40, 42 and 44 may be, for example, copper or other metal, or a metal alloy, or other conductive material.
In some embodiments, a first distance from the upper surface 201 of the semiconductor die 20 to the upper surface 701 of the protection layer 70 is different from a second distance from the upper surface 101u of the conductive base 101 to the upper surface 701 of the protection layer 70. The first distance may be smaller than or greater than the second distance.
The insulating layer 72 is disposed on the upper surface 701 of the protection layer 70 and over the interconnection structures 40, 42 and 44. An insulating layer 74 is disposed on the surface 702 of the protection layer 70 and the surface 101b of the conductive base 101. In some embodiments, a material of one or both of the insulating layers 72 and 74 is a solder mask; however, polypropylene resin or other insulating materials may be used additionally or alternatively. The conductive base 101 defines a stepped structure which is filled with an insulating material 34. The insulating material 34 may be, for example, a polypropylene resin or other suitable material. The insulating layer 74 covers the insulating material 34 in the stepped structure. The stepped structure can minimize or prevent damage to the insulating layer 74 during separation (singulation) of individual semiconductor device packages 1 from a larger package (e.g., panel). In some embodiments, opening(s) may be formed in one or more of the sidewalls 302 of the cavity 30 to control a flow of the insulating material 34 during lamination of the protection layer 70.
The conductive pad 62 is formed on and electrically connected to the interconnection structure 42. A material of the conductive pad 62 may be, for example, copper or other metal, or a metal alloy, or other conductive material. The conductive connect 60 (e.g., a solder ball) is disposed on the conductive pad 62.
The conductive base 103 is disposed above and electrically connected to the semiconductor die 20, and the semiconductor die 22 is bonded to and electrically connected to the conductive base 103. A width of the semiconductor die 22 is substantially the same as a width of the conductive adhesive layer 50 disposed between the semiconductor die 22 and the conductive base 103, and sidewalls of the semiconductor die 22 are respectively aligned with sidewalls of the conductive adhesive layer 50. The conductive adhesive layer 50 is a suitable adhesive film. In some embodiments, the conductive adhesive layer 50 disposed between the semiconductor die 22 and the conductive base 103 is not an epoxy material. The protection layer 70 is disposed on the conductive base 101, the semiconductor die 20, the conductive base 103 and the semiconductor die 22.
The interconnection structures 46 are electrically connected to the semiconductor die 22. The insulating layer 72 is disposed on the upper surface 701 of the protection layer 70 and over the interconnection structures 40a, 44a, 46. The conductive pads 62 are formed on and electrically connected to the interconnection structures 40a, 44a. The conductive connects 60 (e.g., solder balls) are disposed on respective conductive pads 62.
The semiconductor device package 2′ is similar to the semiconductor device package 2 of
In some embodiments, the semiconductor die 20 is embedded in the protection layer 70. The semiconductor die 20 is bonded to the protection layer 70 through the conductive adhesive layer 50. The conductive adhesive layer 50 may be, for example, a conductive gel or epoxy film (epoxy mixed with a conductive material).
The protection layer 70 surrounds the semiconductor die 20. The semiconductor die 20 is electrically connected to the interconnection structures 42 and 43. In some embodiments, the interconnection structures 42 are vias formed in the protection layer 70 and the interconnection structures 43 are vias formed in the protection layer 70 and conductive adhesive layer 50. The conductive pads 62 are disposed on and electrically connected to the interconnection structures 42. A material of the conductive pads 62 may be, for example, copper or other metal, or a metal alloy, or other conductive material. Conductive connects 60 (e.g., solder balls) are disposed on respective conductive pads 62.
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The conductive base 101 includes one or more protrusions 80. Corners 32 of the conductive base 101 are smoothed to redistribute stress to avoid damage to the protection layer 70 during lamination.
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A conductive layer 42a is disposed on an upper surface 701 of the protection layer 70 by coating, sputtering, plating or another suitable technique. In one or more embodiments, the conductive layer 42a includes aluminum or copper, or an alloy thereof (such as AlCu). An insulating material 34 is disposed to fill the vias 36.
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An insulating layer 70b′ is disposed to cover the semiconductor dies 20 and the conductive bases 101, 102. A conductive layer 42a′ is disposed on the upper surface 701 of the insulating layer 70b′. A material of the conductive layer 42a′ is, for example, copper or other metal, or a metal alloy, or other conductive material. A material of the insulating layers 70b, 70b′ may be, for example, a polypropylene resin or other suitable material.
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The semiconductor device package 1″ illustrated in
As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. Thus, the term “approximately equal” in reference to two values can refer to a ratio of the two values being within a range between and inclusive of 0.9 and 1.1.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
Two surfaces or sides can be deemed to be aligned if a displacement between the two surfaces is no greater than 0.5 μm, no greater than 1 μm, no greater than 5 μm, no greater than 10 μm, or no greater than 15 μm.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims
1-20. (canceled)
21. A semiconductor device package, comprising:
- a first conductive base comprising a sidewall;
- a second conductive base;
- wherein the first conductive base is electrically connected to the second conductive base;
- a semiconductor die disposed on first conductive base, the semiconductor die having a first surface and a second surface opposite the first surface; and
- a first insulating material covering the semiconductor die, the second conductive base and the sidewall of the first conductive base.
22. The semiconductor device package of claim 21, the first conductive base further comprises a cavity defined from a first surface of the first conductive base, the cavity having a bottom surface and a depth, the second surface of the semiconductor die bonded to the bottom surface of the cavity.
23. The semiconductor device package of claim 21, wherein the second conductive base further comprises a vertical sidewall and a curved lateral surface, and the vertical sidewall of the second conductive base is coplanar with a lateral surface of the first insulating material.
24. The semiconductor device package of claim 21, wherein the second conductive base further comprises a vertical sidewall and a curved lateral surface, and a portion of the curved lateral surface of the second conductive base faces a bottom surface of the second conductive base.
25. The semiconductor device package of claim 21, further comprising a conductive layer extending from the semiconductor die and disposed on the first insulating material.
26. The semiconductor device package of claim 21, wherein the second conductive base further comprises a vertical sidewall and a curved lateral surface and the vertical sidewall of the second conductive base is exposed and the curved lateral surface of the second conductive base is covered by the first insulating material.
27. The semiconductor device package of claim 21, wherein the first conductive base further comprises a curved lateral surface and the second conductive base further comprises a vertical sidewall and a curved lateral surface, and wherein the curved lateral surface of the first conductive base is opposite to a curved lateral surface of the second conductive base.
28. The semiconductor device package of claim 21, wherein the first insulating material covers the sidewall of the first conductive base.
29. The semiconductor device package of claim 21, wherein the second conductive base comprises a stepped structure, wherein the stepped structure is filled with the first insulating material.
30. The semiconductor device package of claim 21, further comprising a conductive layer extending from the semiconductor die to the second conductive base.
31. The semiconductor device package of claim 21, wherein the second conductive base further comprises a vertical sidewall and a curved lateral surface, and the vertical sidewall of the second conductive base is the outermost surface.
32. The semiconductor device package of claim 21, wherein the first conductive base further comprises a plurality of protrusions from a top view perspective.
33. A semiconductor device package, comprising:
- a first conductive base comprising: a sidewall; a first surface and a second surface opposite the first surface; and
- a second conductive base;
- wherein the first conductive base is electrically connected to the second conductive base;
- a semiconductor die disposed on the first conductive base, the semiconductor die having a first surface and a second surface opposite the first surface;
- a protection layer disposed on the first conductive base and the semiconductor die, the protection layer having a first surface; and
- a first insulating material covering the second conductive base and the sidewall of the first conductive base.
34. The semiconductor device package of claim 33, the first conductive base further comprises a cavity defined from the first surface of the first conductive base, the cavity having a bottom surface and a depth, the second surface of the semiconductor die bonded to the bottom surface of the cavity.
35. The semiconductor device package of claim 33, wherein the second conductive base further comprises a vertical sidewall and a curved lateral surface, and a portion of the curved lateral surface of the second conductive base faces a bottom surface of the second conductive base and wherein the vertical sidewall of the second conductive base is a singulation portion.
36. The semiconductor device package of claim 33, further comprising a conductive layer extending from the semiconductor die and disposed on the first insulating material.
37. The semiconductor device package of claim 33, wherein the second conductive base further comprises a vertical sidewall and a curved lateral surface, and the vertical sidewall of the second conductive base is exposed and the curved lateral surface of the second conductive base is covered by the first insulating material.
38. The semiconductor device package of claim 33, wherein the first conductive base further comprises a curved lateral surface and the second conductive base further comprises a vertical sidewall and a curved lateral surface, and wherein the curved lateral surface of the first conductive base is opposite to the curved lateral surface of the second conductive base.
39. A semiconductor device package, comprising:
- a first conductive base comprising a sidewall;
- a second conductive base comprising a vertical sidewall and a curved lateral surface;
- wherein the first conductive base is electrically connected to the second conductive base;
- a semiconductor die disposed on first conductive base, the semiconductor die having a first surface and a second surface opposite the first surface; and
- a first insulating material covering the semiconductor die and the sidewall of the first conductive base.
40. The semiconductor device package of claim 39, wherein the first conductive base further comprises a curved lateral surface, and wherein the curved lateral surface of the first conductive base is opposite to the curved lateral surface of the second conductive base.
41. The semiconductor device package of claim 39, wherein the vertical sidewall of the second conductive base is coplanar with a lateral surface of the first insulating material.
Type: Application
Filed: Feb 26, 2020
Publication Date: Jun 18, 2020
Applicant: Advanced Semiconductor Engineering, Inc. (Kaohsiung)
Inventors: Chi-Tsung CHIU (Kaohsiung), Meng-Jen WANG (Kaohsiung), Cheng-Hsi CHUANG (Kaohsiung), Hui-Ying HSIEH (Kaohsiung), Hui Hua LEE (Kaohsiung)
Application Number: 16/802,468