VERTICAL CAPACITOR STRUCTURE, CAPACITOR COMPONENT, AND METHOD FOR MANUFACTURING THE VERTICAL CAPACITOR STRUCTURE

Abstract

A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

Description

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to a capacitor structure and a method, and to a vertical capacitor structure and a method for manufacturing the vertical capacitor structure.

2. Description of the Related Art

A comparative circuit may include one or more passive devices, where a passive device is a component such as a capacitor, a resistor or an inductor. To achieve microminiaturization, there is a trend to integrate passive devices into a semiconductor device. However, a plane type capacitor includes three stacked plane layers, and when integrated by disposing the capacitor on a surface of an insulating layer, the capacitor can occupy a large space. In addition, within a limited area, the capacitance of the capacitor is low.

SUMMARY

In some embodiments, a vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

In some embodiments, a capacitor component includes a first conductive layer, a first dielectric layer and a second conductive layer. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The capacitor component has at least one first portion in a truncated hollow cone shape, and a second potion in a substantially plane shape extending from a lower edge of the first portion.

In some embodiments, a method for manufacturing a vertical capacitor structure includes: (a) forming a cavity in a substrate; (b) forming at least one pillar in the cavity; (c) forming a first conductive layer covering and conformal to the cavity of the substrate and the pillar, wherein the first conductive layer is insulated from the substrate and the pillar; (d) forming a first dielectric layer covering and conformal to the first conductive layer; and (e) forming a second conductive layer covering and conformal to the first dielectric layer, wherein the first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of an example of a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 2 illustrates a cross-sectional view taken along line I-I of the vertical capacitor structure shown in FIG. 1.

FIG. 3 illustrates a cross-sectional view of an example of a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 4 illustrates a cross-sectional view of an example of a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 5 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 6 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 7 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 8 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 9 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 10 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 11 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 12 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 13 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 14 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 15 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 16 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 17 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 18 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 19 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 20 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 21 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 22 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 23 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 24 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 25 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 26 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 27 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 28 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 29 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

FIG. 30 illustrates one or more stages of an example of a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure.

DETAILED DESCRIPTION

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

The following disclosure provides for many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

To improve the capacitance of the plane type capacitor, a vertical capacitor is provided. In a method for manufacturing an example vertical capacitor, a glass wafer (or a glass substrate) is provided, and a plurality of holes is formed thereon by, for example, drilling. Then, the capacitor is formed on the side walls of the holes. However, an aspect ratio of the holes may not be large enough, thus the capacitance of such vertical capacitor is constrained. In a method for manufacturing another example vertical capacitor, a silicon wafer is etched to form a plurality of deep holes to increase a surface area of thereof. An aspect ratio of the deep holes may be as large as about 20:1. Then, the surface of the silicon wafer is polarized by an implanter process, such that the surface of the silicon wafer is doped with N/P to form a conductive surface. A dielectric layer, a conductive layer and electrodes are then formed on the conductive surface of the silicon wafer, thus forming the vertical capacitor. However, the etching process for the deep holes and the implanter process may be difficult and expensive.

The present disclosure addresses at least the above concerns and provides for a method for an improved vertical capacitor structure, and improved techniques for manufacturing the vertical capacitor structure. The vertical capacitor may be manufactured without the need of the etching process for the deep holes and the implanter process

FIG. 1 illustrates a cross-sectional view of a vertical capacitor structure 1 according to some embodiments of the present disclosure. FIG. 2 illustrates a cross-sectional view taken along line I-I of the vertical capacitor structure 1 shown in FIG. 1. The vertical capacitor structure 1 includes a substrate 2, at least one pillar 3, a first conductive layer 41, a first dielectric layer 42, a second conductive layer 43, a dielectric structure 5 and a circuit layer 6.

The substrate 2 may be a substrate of any type. For example, the substrate 2 may be made of semiconducting material (e.g., silicon) or insulating material (e.g., glass). The substrate 2 has an upper surface 21 and defines a cavity 20 recessed from the upper surface 21. As shown in FIG. 1, the cavity 20 is defined by a bottom surface 201 and a lateral surface 202. For example, the lateral surface 202 extends from an edge of the bottom surface 201 to the upper surface 21. In some embodiments, the lateral surface 202 may be substantially perpendicular to the bottom surface 201 and the upper surface 21. The bottom surface 201 and the upper surface 21 may be substantially parallel to each other.

In some embodiments, the substrate 2 may include an insulating layer 26 (e.g., a barrier layer). The insulating layer 26 is disposed in and covers the cavity 20, such as covering the bottom surface 201 and the lateral surface 202. The insulating layer 26 may further cover the upper surface 21 of the substrate 2. Due to the arrangement of the insulating layer 26, the substrate 2 is insulated from other components disposed thereon, such as the first conductive layer 41. For example, the insulating layer 26 may be formed by oxidizing surfaces of the substrate 2 (e.g., the upper surface 21, and the bottom surface 201 and the lateral surface 202 of the cavity 20). A material of the insulating layer 26 may be silicon oxide. However, the insulating layer 26 may be omitted if the substrate 2 is made of an insulating material (e.g., glass).

The pillar 3 is disposed in the cavity 20 of the substrate 2. FIGS. 1 and 2 show 2×2 pillars 3 for illustration purpose. In some embodiments, the vertical capacitor structure 1 may include at least about 20×20 pillars 3. However, the amount and arrangement of the pillar 3 are not limited in the present disclosure. The pillar 3 has a bottom surface 31, an upper surface 32 opposite to the bottom surface 31, and a lateral surface 33 extending between the bottom surface 31 and the upper surface 32. As shown in FIG. 1, the pillar 3 stands on the insulating layer 26. The bottom surface 31 is disposed on and contacts the insulating layer 26. That is, the bottom surface 31 is a boundary between the pillar 3 and the insulating layer 26. For example, the bottom surface 31 is adhered to the insulating layer 26. However, in other embodiments, the insulating layer 26 may be omitted, thus the pillar 3 may stand directly on the bottom surface 201 of the cavity 20 of the substrate 2. That is, the bottom surface 31 is a boundary between the pillar 3 and the substrate 2. In some embodiments, a height of the pillar 3 may be substantially equal to the depth of the cavity 20 of the substrate 2.

As shown in FIG. 1, the pillar 3 tapers upward. In some embodiments, the pillar 3 is in a truncated cone-shape (as shown in FIG. 14). For example, the pillar 3 may be in a shape of a right circular cone, while a portion including an apex of the circular cone is omitted. Accordingly, an area of the bottom surface 31 may be greater than an area of the upper surface 32. The lateral surface 33 is not perpendicular to the bottom surface 201 of the cavity 20 of the substrate 2. For example, an angle θ between the lateral surface 33 of the pillar 3 and the bottom surface 201 of the cavity 20 of the substrate 2 is in a range of about 91 degrees to about 95 degrees.

The pillar 3 is preferably made of an insulating material. For example, the pillar 3 may be made of a cured photoimageable dielectric (PID) material such as epoxy or polyimide (PI) including photoinitiators. In some embodiments, a material of the pillar 3 is different from a material of the substrate 2 and a material of the insulating layer 26.

In some embodiments, the pillar 3 has a minimum diameter “D”. For example, the minimum diameter “D” may be located at or adjacent to the upper surface 32 of the pillar 3. A pitch “P” is defined as a distance between the centers of adjacent two pillars 3. The pitch “P” is substantially equal to or greater than twice the minimum diameter “D”. If the pitch “P” is too small, other components (e.g., the first conductive layer 41, the first dielectric layer 42 and the second conductive layer 43) disposed on the adjacent two pillars 3 may contact each other, thus forming a short circuit therebetween. On the other hand, an increased “P” may reduce the maximum amount of the pillars 3 disposed in the cavity 20 of the substrate 2. For example, the minimum diameter “D” may be about 20 μm and the pitch “P” may be equal to or greater than about 40 μm.

The first conductive layer 41 is disposed in the cavity 20 of the substrate 2 and on the pillar 3. The first conductive layer 41 covers and is conformal to the cavity 20 of the substrate 2 and the pillar 3. For example, the first conductive layer 41 covers and is conformal to the upper surface 32 and the lateral surface 33 of the pillar 3, and covers the insulating layer 26 disposed on portions of the bottom surface 201 of the cavity 20 which is not covered by the pillar 3, the lateral surface 202 of the cavity 20, and the upper surface 21 of the substrate 2, such that the first conductive layer 41 is insulated from the substrate 2. The first conductive layer 41 is further disposed on the upper surface 21 of the substrate 2. However, in other embodiments, the first conductive layer 41 may directly contact and be conformal to the upper surface 32 and the lateral surface 33 of the pillar 3, portions of the bottom surface 201 of the cavity 20 which is not covered by the pillar 3, the lateral surface 202 of the cavity 20, and the upper surface 21 of the substrate 2. The first conductive layer 41 has a pad portion 413 on the upper surface 21 of the substrate 2. The first conductive layer 41 may be made of a conductive material, and may be formed by physical or chemical vapor deposition. A thickness of the first conductive layer 41 may be about 0.5 μm to about 3 μm.

The first dielectric layer 42 covers and is conformal to the first conductive layer 41. For example, the first dielectric layer 42 is disposed on and contacts the first conductive layer 41. The first dielectric layer 42 may further be disposed on the upper surface 21 of the substrate 2. The first dielectric layer 42 covers the first conductive layer 41 on the upper surface 21 of the substrate 2, while the pad portion 413 of the first conductive layer 41 is exposed from the first dielectric layer 42. The first dielectric layer 42 may be made of a dielectric material, such as Ta₂O₅, Al₂O₃, TiO₂ or HfO₂. A relative permittivity of the first dielectric layer 42 may be about 8 to about 80. The first dielectric layer 42 may also be formed by physical or chemical vapor deposition, or by atomic layer deposition (ALD). A thickness of the first dielectric layer 42 may be about 10 nm to about 20 nm.

The second conductive layer 43 covers and is conformal to the first dielectric layer 42. For example, the second conductive layer 43 is disposed on and contacts the first dielectric layer 42. The second conductive layer 43 may further be disposed on the upper surface 21 of the substrate 2. The second conductive layer 43 has a pad portion 433 on the upper surface 21 of the substrate 2. The second conductive layer 43 may be made of a conductive material, and may be formed by physical or chemical vapor deposition. A thickness of the second conductive layer 43 may be about 0.5 μm to about 3 μm.

The first conductive layer 41, the first dielectric layer 42 and the second conductive layer 43 jointly form a capacitor component 4. That is, the capacitor component 4 may include the first conductive layer 41, the first dielectric layer 42, and the second conductive layer 43. The capacitor component 4 is a vertical capacitor. A cross section of the capacitor component 4, as shown in FIG. 1, is substantially in a serpentine shape or a rectangular wave shape.

The capacitor component 4 may have at least one first portion 44, a second potion 45, a third portion 46 and a fourth portion 47. The first portion 44 is in a truncated hollow cone shape, and is disposed on and conformal to the pillar 3. That is, the first portion 44 is disposed on the upper surface 32 and the lateral surface 33 of the pillar 3. The first portion 44 may taper upward. The second potion 45 extends from a lower edge of the first portion 44 to the edge of the bottom surface 201 of the cavity 20 of the substrate 2, and is disposed on a bottom surface 201 of the cavity 20 of the substrate 2. The second portion 45 is substantially in a plane shape. The third portion 46 extends from an edge of the second portion 45 to the top edge of the cavity 20 of the substrate 2, and is disposed on a lateral surface 202 of the cavity 20 of the substrate 2. The third portion 46 is substantially perpendicular to the second portion 45. An angle θ at an intersection of the first portion 44 and the second portion 45 is in a range between about 91 degrees to about 95 degrees. The fourth portion 47 extends from an upper edge of the third portion 46, and is disposed on the upper surface 21 of the substrate 2. The fourth portion 47 is substantially perpendicular to the third portion 46.

In some embodiments, the capacitor component 4 has a plurality of first portions 44, and the second portion 45 connects the first portions 44. A pitch “P” between adjacent two of the first portions 44 is equal to or greater than twice a minimum diameter “D” of the first portions 44.

The dielectric structure 5 is disposed on and covers the capacitor component 4. The dielectric structure 5 is disposed in the cavity 20 and on the upper surface 21 of the substrate 2. For example, the dielectric structure 5 fills the cavity 20 of the substrate 2, and has an upper surface 51 which may substantially be planar. A material of the dielectric structure 5 may include an insulating material, a passivation material, a dielectric material or a solder resist material, such as, for example, a benzocyclobutene (BCB) based polymer or a polyimide (PI). As shown in FIG. 1, the dielectric structure 5 covers the first portion 44 of the capacitor component 4. That is, the peripheral outer surface of the first portion 44 of the capacitor component 4 is surrounded by the dielectric structure 5. The dielectric structure 5 defines a first opening 54 extending through the dielectric structure 5 to expose a portion of the first conductive layer 41, and a second opening 56 extending through the dielectric structure 5 to expose a portion of the second conductive layer 43. The first opening 54 and the second opening 56 may be located on the upper surface 21 of the substrate 2. For example, the first opening 54 exposes the pad portion 413 of the first conductive layer 41. The second opening 56 exposes the pad portion 433 of the second conductive layer 43.

The circuit layer 6 is disposed on the upper surface 51, and in the first opening 54 and the second opening 56 of the dielectric structure 5. The circuit layer 6 may be a redistribution layer (RDL) that includes a trace 63, a first terminal 64 and a second terminal 66. The trace 63 is disposed on the upper surface 51 of the dielectric structure 5. The first terminal 64 is disposed in the first opening 54 of the dielectric structure 5 and contacts the first conductive layer 41, such as the pad portion 413 of the first conductive layer 41. The second terminal 66 is disposed in the second opening 56 of the dielectric structure 5 and contacts the second conductive layer 43, such as the pad portion 433 of the second conductive layer 43. As can be seen in FIG. 1, the circuit layer 6 includes a seed layer 61 and a conductive layer 62. The seed layer 61 may be made of copper and/or titanium, and the conductive layer 62 may be made of copper.

In the vertical capacitor structure 1, since the capacitor component 4 (including the first conductive layer 41, the first dielectric layer 42 and the second conductive layer 43) is conformal to the cavity 20 of the substrate 2 and the pillar 3, a total area of the capacitor component 4, especially of the first dielectric layer 42, is dramatically increased. Accordingly, a capacitance density of the vertical capacitor structure 1 (e.g., the capacitance density of the capacitor component 4) is also increased.

Comparing to the exemplary vertical capacitor structure mentioned above, since the vertical capacitor structure 1 utilizes the pillars 3, instead of deep holes, to increase the surface area of the substrate, the etching process for forming deep holes can be omitted. Besides, the implanted process is not necessary for forming the vertical capacitor structure 1.

The capacitance “C” of the capacitor component 4 may be calculated by using the equation below, with “κ” representing a relative permittivity of the first dielectric layer 42, “ϵ₀” representing vacuum permittivity, “A” representing a total area of the first dielectric layer 42, and “d” representing a thickness of the first dielectric layer 42.

$C=\kappa {\varepsilon }_0\frac{A}{d}$

In some embodiments, an area of the bottom surface 201 may be 800 μm×800 μm, and a depth of the cavity 20 may be about 100 μm. The minimum diameter “D” of the pillar 3 may be about 20 μm, and the pitch “P” between adjacent two pillars 3 may be about 20 μm. The height of the pillar 3 is substantially equal to the depth of the cavity 20. The thickness of the first dielectric layer 42 may be about 10 nm to about 20 nm, and the relative permittivity of the first dielectric layer 42 may be about 8 to about 80. The “capacitance density” may be defined as a capacitance in a predetermined area, e.g., the capacitance of the capacitor component 4 divided by the area of the capacitor component 4 on a plane of the upper surface 21 of the substrate 2, which is approximately the area of the bottom surface 201. According to the above criteria, a capacitance density of the capacitor component 4 may be greater than about 70 nF/mm².

FIG. 3 illustrates a cross-sectional view of a vertical capacitor structure 1a according to some embodiments of the present disclosure. The vertical capacitor structure 1a is similar to the vertical capacitor structure 1 shown in FIGS. 1 and 2, except for the structure of the pillar 3a.

As shown in FIG. 3, the pillar 3a also has a bottom surface 31a, an upper surface 32a opposite to the bottom surface 31a, and a lateral surface 33a extending between the bottom surface 31a and the upper surface 32a. However, the pillar 3a is substantially in a cylinder shape. That is, the lateral surface 33a is substantially perpendicular to the bottom surface 31a and the upper surface 32a, and is substantially perpendicular to the bottom surface 201 of the cavity 20 of the substrate 2. Besides, an area of the bottom surface 31a may substantially be equal to the upper surface 32a.

FIG. 4 illustrates a cross-sectional view of a vertical capacitor structure 1b according to some embodiments of the present disclosure. The vertical capacitor structure 1b is similar to the vertical capacitor structure 1 shown in FIGS. 1 and 2, except for the structure of the capacitor component 4b, the dielectric structure 5b and the circuit layer 6b.

As shown in FIG. 4, the capacitor component 4b also includes the first conductive layer 41, the first dielectric layer 42 and the second conductive layer 43, but further includes a second dielectric layer 44 and a third conductive layer 45. The first conductive layer 41, the first dielectric layer 42 and the second conductive layer 43 of the capacitor component 4b are similar to those of the capacitor component 4 shown in FIGS. 1 and 2.

The second dielectric layer 44 is similar to the first dielectric layer 42. The second dielectric layer 44 covers and is conformal to the second conductive layer 43. For example, the second dielectric layer 44 is disposed on and contacts the second conductive layer 43. The second dielectric layer 44 may further be disposed on the upper surface 21 of the substrate 2. The second dielectric layer 44 covers the second conductive layer 43 on the upper surface 21 of the substrate 2, while the pad portion 433 of the second conductive layer 43 is exposed from the second dielectric layer 44. Material, thickness and forming process of the second dielectric layer 44 may be the same as the first dielectric layer 42.

The third conductive layer 45 is similar to the second conductive layer 43 and/or the first conductive layer 41. The third conductive layer 45 covers and is conformal to the second dielectric layer 44. For example, the third conductive layer 45 is disposed on and contacts the second dielectric layer 44. The third conductive layer 45 may further be disposed on the upper surface 21 of the substrate 2. The third conductive layer 45 has a pad portion 453 on the upper surface 21 of the substrate 2. Material, thickness and forming process of the third conductive layer 45 may be the same as the second conductive layer 43 and/or the first conductive layer 41.

Accordingly, the dielectric structure 5 further defines a third opening 58 to expose a portion of the third conductive layer 45. The third opening 58 may be located on the upper surface 21 of the substrate 2. For example, the third opening 58 exposes the pad portion 453 of the third conductive layer 45.

In the vertical capacitor structure 1b, since the capacitor component 4b includes two dielectric layers (e.g., the first dielectric layer 42 and the second dielectric layer 44), a capacitance density thereof may be twice the capacitance density of the vertical capacitor structure 1 shown in FIGS. 1 and 2. For example, the capacitance density of the vertical capacitor structure 1b may be greater than about 140 NF/mm².

FIG. 5 through FIG. 30 illustrate a method for manufacturing a vertical capacitor structure according to some embodiments of the present disclosure. In some embodiments, the method is for manufacturing a vertical capacitor structure such as the vertical capacitor structure 1 shown in FIGS. 1 and 2.

Referring to FIG. 5, a substrate 2 is provided, and a photoresist layer 81 is disposed thereon. The substrate 2 may be a substrate of any type. For example, the substrate 2 may be made of semiconducting material (e.g., silicon) or insulating material (e.g., glass). The substrate 2 has an upper surface 21, and the photoresist layer 81 is disposed on the upper surface 21.

Referring to FIG. 6, the photoresist layer 81 is patterned to define a through hole 82. Processes for patterning the photoresist layer 81 may include exposure and development. For example, the photoresist layer 81 may be exposed to a patterned light, thus a portion of the photoresist layer is cured. Then, the photoresist layer 81 is developed. Another portion of the photoresist layer 81 which is not cured is removed during the development process.

Referring to FIG. 7, the substrate 2 is etched with the photoresist layer 81 serving as a mask, thus forming a cavity 20 in the substrate 2 corresponding to the through hole 82 of the photoresist layer 81. The cavity 20 is recessed from the upper surface 21 of the substrate 2. As shown in FIG. 7, the cavity 20 is defined by a bottom surface 201 and a lateral surface 202. For example, the lateral surface 202 extends from an edge of the bottom surface 201 to the upper surface 21. In some embodiments, the lateral surface 202 may be substantially perpendicular to the bottom surface 201 and the upper surface 21. The bottom surface 201 and the upper surface 21 may be substantially parallel to each other.

Referring to FIG. 8, the photoresist layer 81 is removed, and the upper surface 21 of the substrate 2 is exposed. FIG. 9 illustrates a perspective view of the substrate 2. In some embodiments, an area of the bottom surface 201 of the cavity 20 may be about 800 nm×800 nm, and a depth thereof may be about 100 nm. Since the bottom surface 201 of the cavity 20 has a large area relative to the depth of the cavity 20, the etching process for forming the cavity 20 may be easier and cheaper than the etching process for forming the deep holes in the exemplary vertical capacitor structure.

Referring to FIG. 10, an insulating layer 26 (e.g., a barrier layer) is formed to cover the cavity 20 of the substrate 2 such as covering the bottom surface 201 and the lateral surface 202. The insulating layer 26 may further cover the upper surface 21 of the substrate 2. Due to the arrangement of the insulating layer 26, the substrate 2 is insulated from other components disposed thereon. For example, the insulating layer 26 may be formed by oxidizing surfaces of the substrate 2 (e.g., the upper surface 21, and the bottom surface 201 and the lateral surface 202 of the cavity 20). A material of the insulating layer 26 may be silicon oxide. However, the insulating layer 26 may be omitted if the substrate 2 is made of an insulating material (e.g., glass).

Referring to FIG. 11, a photoimageable dielectric material 83 is disposed in the cavity 20 and on the upper surface 21 of the substrate 2. For example, the photoimageable dielectric material 83 is disposed on the insulating layer 26. The photoimageable dielectric material 83 may be epoxy or polyimide (PI) including photoinitiators, and may not yet be cured. In some embodiments, the photoimageable dielectric material 83 may be applied in a dry film form, thus an upper surface 84 of the photoimageable dielectric material 83 may not be planar.

Referring to FIG. 12, a photomask 85 is disposed on the photoimageable dielectric material 83. The photomask 85 defines at least one through hole 86. Then, the photoimageable dielectric material 83 is exposed to a radiation source, and at least a portion of the photoimageable dielectric material 83 which is not covered by the photomask 85 is cured to form at least one pillar 3 in the cavity 20 of the substrate 2. That is, the pillar 3 is the cured portion of the photoimageable dielectric material 83. The pillar 3 is disposed in the cavity 20 of the substrate 2. The pillar 3 has a bottom surface 31, an upper surface 32 opposite to the bottom surface 31, and a lateral surface 33 extending between the bottom surface 31 and the upper surface 32. The upper surface 32 is a portion of the upper surface 84 of the photoimageable dielectric material 83.

Referring to FIG. 13, the photoimageable dielectric material 83 is developed, and the lateral surface 33 of the pillar 3 is exposed. That is, a portion (e.g., uncured portion) of the photoimageable dielectric material 83, excluding the pillar 3, is removed. Thus, the pillar 3 stands on the insulating layer 26. The bottom surface 31 is disposed on and contacts the insulating layer 26. That is, the bottom surface 31 is a boundary between the pillar 3 and the insulating layer 26. For example, the bottom surface 31 is adhered to the insulating layer 26. In some embodiments, a height of the pillar 3 may be substantially equal to the depth of the cavity 20 of the substrate 2.

As shown in FIG. 13, the pillar 3 tapers upward. In some embodiments, the pillar 3 is in a truncated cone-shape (as shown in FIG. 14). For example, the pillar 3 may be in a shape of a right circular cone, while a portion including an apex of the circular cone is omitted. Accordingly, an area of the bottom surface 31 may be greater than an area of the upper surface 32. The lateral surface 33 is not perpendicular to the bottom surface 201 of the cavity 20 of the substrate 2. For example, an angle θ between the lateral surface 33 of the pillar 3 and the bottom surface 201 of the cavity 20 of the substrate 2 is in a range of about 91 degrees to about 95 degrees. In some embodiments, the pillar 3 has a minimum diameter “D”. For example, the minimum diameter “D” may be located at or adjacent to the upper surface 32 of the pillar 3. A pitch “P” is defined as a distance between the centers of adjacent two pillars 3. For example, the minimum diameter “D” may be about μm and the pitch “P” may be equal to or greater than about 40 μm.

FIG. 14 illustrates a perspective view of the structure shown in FIG. 13. FIG. 14 shows 2×2 pillars 3 for illustration purpose. However, the amount and arrangement of the pillar 3 are not limited in the present disclosure. As shown in FIG. 13 and FIG. 14, there is an empty space surrounding the pillars 3. That is, the empty space is disposed between the lateral surfaces 33 of the pillars 3, and between the lateral surface 33 of the pillar 3 and the lateral surface 202 of the cavity 20 of the substrate 2.

Referring to FIG. 15, a first conductive layer 41 is formed to cover and conformal to the cavity 20 of the substrate 2 and the pillar 3. For example, the first conductive layer 41 covers and is conformal to the upper surface 32 and the lateral surface 33 of the pillar 3, portions of the bottom surface 201 of the cavity 20 which is not covered by the pillar 3, and the lateral surface 202 of the cavity 20 of the substrate 2. Since the angle θ between the lateral surface 33 of the pillar 3 and the bottom surface 201 of the cavity 20 of the substrate 2 is in a range of about 91 degrees to about 95 degrees, the first conductive layer 41 may be disposed on and extend smoothly along the lateral surface 33 of the pillar 3.

The first conductive layer 41 is insulated from the substrate 2. For example, the first conductive layer 41 covers the insulating layer 26, such that the first conductive layer 41 is insulated from the substrate 2. The first conductive layer 41 is further disposed on the upper surface 21 of the substrate 2. The first conductive layer 41 may be made of a conductive material, and may be formed by physical or chemical vapor deposition.

Referring to FIG. 16, a first dielectric layer 42 is formed to cover and conformal to the first conductive layer 41. For example, the first dielectric layer 42 is disposed on and contacts the first conductive layer 41. The first dielectric layer 42 may further be disposed on the upper surface 21 of the substrate 2. The first dielectric layer 42 covers the first conductive layer 41 on the upper surface 21 of the substrate 2. The first dielectric layer 42 may be made of a dielectric material, such as Ta₂O₅; Al₂O₃, TiO₂ or HfO₂. A relative permittivity of the first dielectric layer 42 may be about 8 to about 80. The first dielectric layer 42 may also be formed by physical or chemical vapor deposition, or by atomic layer deposition (ALD). A thickness of the first dielectric layer 42 may be about 10 nm to about 20 nm.

Referring to FIG. 17, a second conductive layer 43 is formed to cover and conformal to the first dielectric layer 42. For example, the second conductive layer 43 is disposed on and contacts the first dielectric layer 42. The second conductive layer 43 may further be disposed on the upper surface 21 of the substrate 2. The second conductive layer 43 may be made of a conductive material, and may be formed by physical or chemical vapor deposition.

Referring to FIG. 18, a photoresist layer 88 is disposed on the second conductive layer 43. The photoresist layer 88 may be applied in a dry film form, and may be laminated to the second conductive layer 43. Thus, the photoresist layer 88 may not extend into the cavity 20.

Referring to FIG. 19, the photoresist layer 88 is patterned to define a through hole 89.

Referring to FIG. 20, the first dielectric layer 42 and the second conductive layer 43 is etched with the photoresist layer 88 serving as a mask to form a pad portion 433 of the second conductive layer 43, and to expose a portion of the first conductive layer 41. That is, portions of the first dielectric layer 42 and the second conductive layer 43 corresponding to the through hole 89 of the photoresist layer 88 are removed. Then, the photoresist layer 88 is removed.

Referring to FIG. 21, a photoresist layer 90 is disposed on the second conductive layer 43 and on the first conductive layer 41. The photoresist layer 90 may be applied in a dry film form, and may be laminated to the second conductive layer 43. Thus, the photoresist layer 90 may not extend into the cavity 20.

Referring to FIG. 22, the photoresist layer 90 is patterned to define a through hole 91.

Referring to FIG. 23, the first conductive layer 41 is etched with the photoresist layer 90 serving as a mask to form a pad portion 413 of the first conductive layer 41. The pad portion 413 of the first conductive layer 41 is exposed from the first dielectric layer 42 and the first second conductive layer 43. That is, portions of the first conductive layer 41 corresponding to the through hole 91 of the photoresist layer 90 are removed. Then, the photoresist layer 90 is removed. Accordingly, a capacitor component 4 is formed and includes the first conductive layer 41, the first dielectric layer 42, and the second conductive layer 43. That is, the first conductive layer 41, the first dielectric layer 42 and the second conductive layer 43 jointly form the capacitor component 4. The capacitor component 4 is a vertical capacitor. A cross section of the capacitor component 4, as shown in FIG. 23, is substantially in a serpentine shape or a rectangular wave shape.

The capacitor component 4 may have at least one first portion 44, a second potion 45, a third portion 46 and a fourth portion 47. The first portion 44 is in a truncated hollow cone shape, and is disposed on and conformal to the pillar 3. That is, the first portion 44 is disposed on the upper surface 32 and the lateral surface 33 of the pillar 3. The first portion 44 may taper upward. The second potion 45 extends from a lower edge of the first portion 44 to the edge of the bottom surface 201 of the cavity 20 of the substrate 2, and is disposed on a bottom surface 201 of the cavity 20 of the substrate 2. The second portion 45 is substantially in a plane shape. The third portion 46 extends from an edge of the second portion 45 to the top edge of the cavity 20 of the substrate 2, and is disposed on a lateral surface 202 of the cavity 20 of the substrate 2. The third portion 46 is substantially perpendicular to the second portion 45. An angle θ at an intersection of the first portion 44 and the second portion 45 is in a range between about 91 degrees to about 95 degrees. The fourth portion 47 extends from an upper edge of the third portion 46, and is disposed on the upper surface 21 of the substrate 2. The fourth portion 47 is substantially perpendicular to the third portion 46.

Referring to FIG. 24, a dielectric structure 5 is formed to covers the capacitor component 4. The dielectric structure 5 is disposed in the cavity 20 and on the upper surface 21 of the substrate 2. For example, the dielectric structure 5 fills the cavity 20 of the substrate 2, and has an upper surface 51 which may substantially be planar. A material of the dielectric structure 5 may include an insulating material, a passivation material, a dielectric material or a solder resist material, such as, for example, a benzocyclobutene (BCB) based polymer or a polyimide (PI). As shown in FIG. 24, the dielectric structure 5 covers the first portion 44 of the capacitor component 4. That is, the peripheral outer surface of the first portion 44 of the capacitor component 4 is surrounded by the dielectric structure 5.

Referring to FIG. 25, a first opening 54 and a second opening 56 are formed in and extend through the dielectric structure 5. The first opening 54 and the second opening 56 may be located on the upper surface 21 of the substrate 2. The first opening 54 exposes a portion of the first conductive layer 41, such as the pad portion 413 of the first conductive layer 41. The second opening 56 exposes a portion of the second conductive layer 43, such as the pad portion 433 of the second conductive layer 43.

Referring to FIG. 26, a seed layer 61 is formed in the first opening 54 and the second opening 56, and on the upper surface 51 of the dielectric structure 5. The seed layer 61 may be made of copper and/or titanium, and may be formed by sputtering.

Referring to FIG. 27, a photoresist layer 92 is disposed on the seed layer 61. The photoresist layer 92 may be applied in a dry film form.

Referring to FIG. 28, the photoresist layer 92 is patterned to define a first through hole 93 on the seed layer 61, a second through hole 94 corresponding to (or above) the first opening 54 of the dielectric structure 5, and a third through hole 95 corresponding to (or above) the second opening 56 of the dielectric structure 5.

Referring to FIG. 29, a conductive layer 62 is formed in the first through hole 93, the second through hole 94 and the third through hole 95 of the photoresist layer 92. The conductive layer 62 may be made of copper, and may be formed by plating. Accordingly, conductive layer 62 includes a trace 63 disposed in the first through hole 93 of the photoresist layer 92, a first terminal 64 disposed in the second through hole 94 of the photoresist layer 92 and in the first opening 54 of the dielectric structure 5, and a second terminal 66 disposed in the second through hole 95 of the photoresist layer 92 and in the second opening 56 of the dielectric structure 5. That is, a metal material is disposed in the first opening 54 of the dielectric structure 5 to contact the first conductive layer 41 to form the first terminal 64, and a metal material is disposed in the second opening 56 of the dielectric structure 5 to contact the second conductive layer 43 to form the second terminal 66.

Referring to FIG. 30, the photoresist layer 92 is removed. Then, a portion of the seed layer 61 which is not covered by the conductive layer 62 is removed, thus forming the circuit layer 6. The circuit layer 6 may be a redistribution layer (RDL) that includes the trace 63, the first terminal 64 and the second terminal 66. Then, a singulation process is conducted to form the vertical capacitor structure 1 as shown in FIGS. 1 and 2.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.

As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 10⁴ S/m, such as at least 10⁵ S/m or at least 10⁶ S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.

Claims

1. A vertical capacitor structure, comprising:

a substrate defining a cavity;

at least one pillar disposed in the cavity;

a first conductive layer covering and conformal to the cavity of the substrate and the pillar, wherein the first conductive layer is insulated from the substrate;

a first dielectric layer covering and conformal to the first conductive layer; and

a second conductive layer covering and conformal to the first dielectric layer, wherein the first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

2. The vertical capacitor structure of claim 1, wherein the substrate includes an insulating layer disposed in and covers the cavity, and the first conductive layer covers the insulating layer, such that the first conductive layer is insulated from the substrate.

3. The vertical capacitor structure of claim 2, wherein the pillar stands on the insulating layer.

4. The vertical capacitor structure of claim 1, wherein the pillar is in a truncated cone-shape.

5. The vertical capacitor structure of claim 1, wherein the pillar tapers upward.

6. The vertical capacitor structure of claim 1, wherein a material of the pillar is different from a material of the substrate.

7. The vertical capacitor structure of claim 1, wherein a cross section of the capacitor component is substantially in a serpentine shape.

8. The vertical capacitor structure of claim 1, wherein the capacitor component has at least one first portion in a truncated hollow cone shape disposed on the pillar, and a second potion extending from a lower edge of the first portion and disposed on a bottom surface of the cavity of the substrate.

9. The vertical capacitor structure of claim 1, wherein the capacitor component further has a third portion extending from an edge of the second portion and disposed on a lateral surface of the cavity of the substrate.

10. The vertical capacitor structure of claim 1, wherein the substrate has an upper surface, the cavity is recessed from the upper surface of the substrate, and the first conductive layer is further disposed on the upper surface of the substrate.

11. The vertical capacitor structure of claim 1, wherein the substrate has an upper surface, the cavity is recessed from the upper surface of the substrate, and the first dielectric layer is further disposed on the upper surface.

12. The vertical capacitor structure of claim 1, wherein the substrate has an upper surface, the cavity is recessed from the upper surface of the substrate, and the second conductive layer is further disposed on the upper surface.

13. The vertical capacitor structure of claim 1, further comprising a dielectric structure disposed on and covering the capacitor component.

14. The vertical capacitor structure of claim 13, wherein the dielectric structure is disposed in the cavity and on an upper surface of the substrate.

15. The vertical capacitor structure of claim 1, wherein an angle between a lateral surface of the pillar and a bottom surface of the cavity is in a range of about 91 degrees to about 95 degrees.

16-20. (canceled)

21. A method for manufacturing a vertical capacitor structure, comprising:

(a) forming a cavity in a substrate;

(b) forming at least one pillar in the cavity;

(c) forming a first conductive layer covering and conformal to the cavity of the substrate and the pillar, wherein the first conductive layer is insulated from the substrate;

(d) forming a first dielectric layer covering and conformal to the first conductive layer; and

(e) forming a second conductive layer covering and conformal to the first dielectric layer, wherein the first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.

22. The method of claim 21, wherein after (b), the method further comprises:

forming an insulating layer to cover the cavity of the substrate, such that the pillar formed in (b) stands on the insulating layer.

23. The method of claim 21, wherein before (c), the method further comprises:

forming an insulating layer to cover the cavity of the substrate, such that the first conductive layer formed in (c) is insulated from the substrate.

24. The method of claim 21, wherein after (e), the method further comprises:

(f) forming a dielectric structure covering the capacitor component.