CROSS REFERENCE TO RELATED APPLICATIONS This application is a divisional application of and claims the benefit of U.S. patent application Ser. No. 16/174,237, filed Oct. 29, 2018.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a semiconductor device and manufacturing method thereof, and more specifically to a semiconductor device and manufacturing method thereof applying photoresists.
2. Description of the Prior Art Photolithography is an essential process in the fabrication of semiconductor ICs. Principally, the photolithography is to form designed patterns such as implantation patterns or layout patterns on at least a photomask, and then to precisely transfer such patterns to a photoresist layer by exposure and development steps. Subsequently, by performing semiconductor processes such as ion implantation, etching process, or deposition, the complicated and sophisticated IC structure is obtained.
Along with miniaturization of semiconductor devices and progress in fabrication of semiconductor device, conventional lithography process meets the bottleneck due to printability and manufacturability. To meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, double patterning technique (DPT) is developed and taken as one of the most promising lithography technologies for 32 nanometer (nm) node and 22 nm node patterning since it can increase the half-pitch resolution by up to two times using current infrastructures.
SUMMARY OF THE INVENTION The present invention provides a semiconductor device and manufacturing method thereof, which forms photoresist layers several times and then etching once to shrink gaps between formed patterns.
The present invention provides a method of manufacturing a semiconductor device including the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer.
The present invention provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.
The present invention provides a semiconductor device, including a plurality of hole structures being disposed on a layer, wherein the layer includes first holes and second holes, wherein the depths of the first holes are less than the depths of the second holes.
According to the above, the present invention provides a semiconductor device and manufacturing method thereof, which forms a first patterned photoresist layer and a second patterned photoresist layer on a substrate sequentially, and then forms a liner covering sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. Therefore, pattern precision can be increased by forming photoresists many times (or respectively). Furthermore, patterns can be formed more precisely than only coating photoresists by forming the liner surrounding the first patterned photoresist layer and the second patterned photoresist layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 schematically depicts a top view and a cross-sectional view of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 2 schematically depicts a top view and a cross-sectional view of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 schematically depicts a top view and cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 4 schematically depicts a top view and cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 5 schematically depicts cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 6 schematically depicts cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 7 schematically depicts cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 8 schematically depicts cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 9 schematically depicts cross-sectional views of a method of manufacturing a semiconductor device according to another embodiment of the present invention.
FIG. 10 schematically depicts cross-sectional views of a method of manufacturing a semiconductor device according to another embodiment of the present invention.
FIG. 11 schematically depicts cross-sectional views of a method of manufacturing a semiconductor device according to another embodiment of the present invention.
FIG. 12 schematically depicts a top view of a method of manufacturing a memory cell according to an embodiment of the present invention.
FIG. 13 schematically depicts cross-sectional views of FIG. 12 along line DD′ and line EE′.
FIG. 14 schematically depicts a top view of a method of manufacturing a memory cell according to an embodiment of the present invention.
FIG. 15 schematically depicts a top view of a substrate structure.
FIG. 16 schematically depicts a top view of a substrate structure.
DETAILED DESCRIPTION FIGS. 1-4 schematically depicts top views and cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention. The upper diagram of FIG. 1 is a top view of a method of manufacturing a semiconductor device, and the lower diagram of FIG. 1 is a cross-sectional view of the upper diagram along line AA′. As shown in FIG. 1, a substrate 110 is provided. The substrate 110 may include a plurality of material layers. In this embodiment, the substrate 110 may include a tungsten silicon layer 112, a silicon nitride layer 114, an oxide layer 116, an organic dielectric layer (ODL) 118 and a silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119 stacked from bottom to top, but it is not limited thereto. A first patterned photoresist layer 10 is formed on the substrate 110. In this embodiment, the pattern of the first patterned photoresist layer 10 is night square photoresists arranged regularly, but it is not limited thereto.
The upper diagram of FIG. 2 is a top view of a method of manufacturing a semiconductor device, and the lower diagram of FIG. 2 is a cross-sectional view of the upper diagram along line AA′. As shown in FIG. 2, a second patterned photoresist layer 20 is formed on the substrate 110 after the first patterned photoresist layer 10 is formed on the substrate 110. In this embodiment, the first patterned photoresist layer 10 and the second patterned photoresist layer 20 are arranged alternatively, but it is not restricted thereto. The photoresist layers are formed several times (respectively), thereby gaps between patterns of the photoresist layers being shrunk. For instance, minimum distances P between patterns of the first patterned photoresist layer 10 and patterns of the second patterned photoresist layer 20 are less than minimum distances between patterns of the first patterned photoresist layer 10 and minimum distances between patterns of the second patterned photoresist layer 20.
The upper diagram of FIG. 3 is a top view of a method of manufacturing a semiconductor device, the left and lower diagram of FIG. 3 is a cross-sectional view of the upper diagram along line AA′ and the right and lower diagram of FIG. 3 is a cross-sectional view of the upper diagram along line BB′. As shown in FIG. 3, a liner 30 is formed to cover sidewalls of the first patterned photoresist layer 10 and the second patterned photoresist layer 20. In this embodiment, the liner 30 covers sidewalls S1 and top surfaces T1 of the first patterned photoresist layer 10, and sidewalls S2 and top surfaces T2 of the second patterned photoresist layer 20. In another embodiment, the liner 30 may only cover the sidewalls S1 of the first patterned photoresist layer 10, and the sidewalls S2 of the second patterned photoresist layer 20. That is, the liner 30 may blanketly cover the sidewalls S1 and the top surfaces T1 of the first patterned photoresist layer 10, and the sidewalls S2 and the top surfaces T2 of the second patterned photoresist layer 20, and then the liner 30 of the first patterned photoresist layer 10 and the second patterned photoresist layer 20 is removed except for the liner 30 covering the sidewalls S1 of the first patterned photoresist layer 10 and the sidewalls S2 covering the second patterned photoresist layer 20, depending upon practical requirements. By applying the present invention, gaps having minimum distances P between the first patterned photoresist layer 10 and the second patterned photoresist layer 20 are filled up by the liner 30 covering the sidewalls S1 of the first patterned photoresist layer 10 and the sidewalls S2 of the second patterned photoresist layer 20. Thus, a plurality of holes V surrounded by the liner 30 are formed. More precisely, the liner 30 covering two of the sidewalls S1 of the first patterned photoresist layer 10 and the liner 30 covering two of the corresponding sidewalls S2 of the second patterned photoresist layer 20 enclose each of the holes V, but it is not limited thereto. Compared to holes enclosed by the first patterned photoresist layer 10 and the second patterned photoresist layer 20 directly contacted to each other, patterns later formed by utilizing the liner 30 can be more precisely. Ina preferred embodiment, the liner 30 may by formed by an atomic layer deposition (ALD) process, so that the liner 30 can be formed more accurately than the first patterned photoresist layer 10 and the second patterned photoresist layer 20 being formed by spin-coating. In one case, the liner 30 may be an oxide liner, but it is not limited thereto.
The upper diagram of FIG. 4 is a top view of a method of manufacturing a semiconductor device, the left and lower diagram of FIG. 4 is a cross-sectional view of the upper diagram along line AA′, and the right and lower diagram of FIG. 4 is a cross-sectional view of the upper diagram along line BB′. The patterns of the first patterned photoresist layer 10, the second patterned photoresist layer 20 and the liner 30 are transferred into material layers in the substrate 110. In this embodiment, the patterns of the first patterned photoresist layer 10, the second patterned photoresist layer 20 and the liner 30 are transferred into material layers in the substrate 110 by several processes. As shown in FIG. 4, the patterns of the first patterned photoresist layer 10, the second patterned photoresist layer 20 and the liner 30 are transferred into the silicon nitride layer 114 and the oxide layer 116, to form a plurality of pillars 10a/20a, and each of the pillars 10a/20a includes a silicon nitride layer 114′ and an oxide layer 116′, wherein the tungsten silicon layer 112 is used as an etch stop layer while pattern transferring. The organic dielectric layer (ODL) 118 and the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119 on the silicon nitride layer 114 and the oxide layer 116 are hard masks during etching transferring processes, for transferring the patterns of the first patterned photoresist layer 10, the second patterned photoresist layer 20 and the liner 30 into the silicon nitride layer 114 and the oxide layer 116. Therefore, the organic dielectric layer (ODL) 118 and the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119 are removed while pattern transferring. Two embodiments of pattern transferring are presented in the following, but the present invention is not restricted thereto.
Only cross-sectional views are changed during pattern transferring steps, and thus cross-sectional views are only depicted in FIGS. 5-8 for simplifying.
FIGS. 5-8 schematically depict cross-sectional views of a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein left diagrams of FIGS. 5-8 are cross-sectional views of FIG. 3 along line BB′ and right diagrams of FIGS. 5-8 are cross-sectional views of FIG. 3 along line CC′. As shown in FIG. 5, a first etching process P1 is performed to remove the liner 30 of FIG. 3 covering the top surfaces T1 of the first patterned photoresist layer 10, the liner 30 of FIG. 3 covering the top surfaces T2 of the second patterned photoresist layer 20, and the liner 30 of FIG. 3 covering the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119 exposed by the first patterned photoresist layer 10 and the second patterned photoresist layer 20. Therefore, liners 30a covering the sidewalls S1 of the first patterned photoresist layer 10 only and covering the sidewalls S2 of the second patterned photoresist layer 20 only are reserved. The silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119 exposed by the first patterned photoresist layer 10 and the second patterned photoresist layer 20 is also removed to form a silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119a and expose a part of the organic dielectric layer (ODL) 118.
A second etching process P2 is performed to remove the organic dielectric layer (ODL) 118 exposed by the first patterned photoresist layer 10, the second patterned photoresist layer 20 and the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119, to form an organic dielectric layer (ODL) 118a and expose the oxide layer 116, as shown in FIG. 6.
A third etching process P3 is performed to remove the oxide layer 116, the silicon nitride layer 114 and the tungsten silicon layer 112 exposed by the liners 30a, the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119a and the organic dielectric layer (ODL) 118a, to form an oxide layer 116a, a silicon nitride layer 114a and a tungsten silicon layer 112a, as shown in FIG. 7. In this embodiment, the tungsten silicon layer 112 is also etched to form recesses R1 while the third etching process P3 is performed, thereby the tungsten silicon layer 112a having a plurality of inverted T-shaped cross-sectional profiles. Moreover, the liner 30a and the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119a having similar materials to the oxide layer 116 and the silicon nitride layer 114 are also removed while the oxide layer 116 and the silicon nitride layer 114 are etched, but only a part 118a of the organic dielectric layer (ODL) 118 is removed while an organic dielectric layer (ODL) 118b is reserved.
Thereafter, the organic dielectric layer (ODL) 118b is removed to form a hard mask H1, as shown in FIG. 8. The hard mask H1 includes the tungsten silicon layer 112a, the silicon nitride layer 114a and the oxide layer 116a stacked from bottom to top. The hard mask H1 may be a storage node hard mask of a capacitor, but it is not limited thereto. In the present invention, photoresist layers are formed sequentially, a liner surrounds the photoresist layers to form a pattern layer, and then the pattern of the pattern layer is transferred to material layers such as hard mask layers. In this way, gaps between patterns in the pattern layer can be shrunk and the pattern precision can be improved.
FIGS. 9-11 schematically depict cross-sectional views of a method of manufacturing a semiconductor device according to another embodiment of the present invention. In another embodiment, after the first etching process P1 of FIG. 5 is performed, the first patterned photoresist layer 10 and the second patterned photoresist layer 20 are removed and thus recesses R2 are formed between the liners 30a, as shown in FIG. 9.
An etching process P4 is performed to remove the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119a, the organic dielectric layer (ODL) 118, the oxide layer 116, the silicon nitride layer 114 and the tungsten silicon layer 112 exposed by the liners 30a, thereby first recesses R3 and second recesses R4 can being formed in the tungsten silicon layer 112, as shown in FIG. 10. By doing this, a tungsten silicon layer 112b, a silicon nitride layer 114b, an oxide layer 116b, an organic dielectric layer (ODL) 118c and a silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119b stacked from bottom to top can be formed, wherein depths d1 of the first recesses R3 are less than depths d2 of the second recesses R4. In one case, the first recesses R3 and the second recesses R4 are arranged alternatively.
The present invention may be applied to form a memory cell 200 as shown in FIGS. 12-13. FIG. 12 schematically depicts a top view of a method of manufacturing a memory cell according to an embodiment of the present invention. FIG. 13 schematically depicts cross-sectional views of FIG. 12 along line DD′ and line EE′. FIGS. 12-13 depict a substrate 220, active parts 222 in the substrate 220, word lines 230 embedded in the substrate 220, a mask layer 240 on the substrate 220, and recesses R5 in the mask layer 240. The tungsten silicon layer 112b of FIG. 10 may correspond to the mask layer 240 of FIGS. 12-13 on the substrate 220. Methods of forming the first recesses R3 or/and the second recesses R4 of FIG. 10 may be applied to form the recesses R5 of the memory cell 200 of FIGS. 12-13. The substrate 220 may be a silicon layer, a nitride layer and an oxide layer stacked from bottom to top, but it is not limited thereto.
A structure opposite to the structure of FIG. 12 may be formed. FIG. 14 schematically depicts a top view of a method of manufacturing a memory cell according to an embodiment of the present invention. As shown in FIG. 14, the mask layer 240 of FIG. 12 is replaced by holes V1 and holes V2, and the recesses R5 in the mask layer 240 of FIG. 12 are replaced by a mask layer 240a. In this way, a plurality of hole structures are formed, wherein the hole structures may include the holes V1 and the holes V2, and the depths of the holes V1 are different from the depths of the holes V2. For example, the depths of the holes V1 are less than the depths of the holes V2, but it is not limited thereto. A bottom of each of the hole structures exposes at least two different materials, wherein the materials of the bottom of each of the hole structures may include silicon, silicon oxide or/and silicon nitride.
Otherwise, the present invention may be applied to a layout of FIG. 15. A substrate 310 may include a plurality of line patterns 312, wherein the line patterns 312 extend along a direction x. The substrate 310 may include a silicon layer and an oxide layer stacked from bottom to top, but it is not limited thereto. The cross-sectional view of FIG. 10 may correspond to the cross-sectional view along the direction x, wherein the first recesses R3 and the second recesses R4 of FIG. 10 may correspond to the holes V3 and the holes V4, and the shapes of the openings of the holes V3 are different from the shapes of the openings of the holes V4. The depths of the holes V1 are different from the depths of the holes V2, depending upon practical requirements.
FIG. 16 schematically depicts a top view of a substrate structure. As shown in FIG. 16, a substrate 410 may include active areas 412 and active areas 414, wherein the active areas 412 may be a plurality of protruding islands, and each of the protruding islands may be isolated from an isolation layer (a location 420 of forming the isolation layer). The cross-sectional view of FIG. 10 may correspond to the cross-sectional view along line FF′ or the cross-sectional view along line GG′, wherein the first recesses R3 and the second recesses R4 of FIG. 10 may correspond to the recesses R6 or the recesses R7 between the active areas 412, depending upon practical requirements.
The liners 30a, the silicon-containing hard mask bottom anti-reflection coating (SHB) layer 119b and the organic dielectric layer (ODL) 118c are removed as shown in FIG. 11, thereby forming a hard mask H2, wherein the hard mask H2 includes the tungsten silicon layer 112b, the silicon nitride layer 114b and the oxide layer 116b stacked from bottom to top. More precisely, the hard mask H2 may include a plurality of pillars, and each of the pillars may include a protruding part 112b1 of the tungsten silicon layer 112b, the silicon nitride layer 114b and the oxide layer 116b. The hard mask H2 may be a storage node hard mask of a capacitor, but it is not limited thereto. In the present invention, photoresist layers are sequentially formed, and then a liner surrounds these photoresist layers to form a pattern layer, and then the pattern layer is transferred into material layers such as a hard mask layer. In this way, gaps between patterns of the pattern layer can be shrunk, and pattern precision can be increased.
To summarize, the present invention provides a semiconductor device and manufacturing method thereof, which forms a first patterned photoresist layer and a second patterned photoresist layer on a substrate sequentially, and then forms a liner covering sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. In this way, the patterns of the first patterned photoresist layer, the second patterned photoresist layer and the liner, or the patterns of the liner (after the first patterned photoresist layer the second patterned photoresist layer are removed) can be transferred into lower material layers. Pattern precision can be increased by forming photoresists many times (or respectively) and etching once. Furthermore, patterns in the lower material layers can be formed more precisely than only coating photoresists by forming the liner surrounding the first patterned photoresist layer and the second patterned photoresist layer, hence further increasing pattern precision. Preferably, the liner may be formed by an atomic layer deposition (ALD) process, but it is not limited thereto.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
