SEQUENCING CHIP AND MANUFACTURING METHOD THEREFOR
Provided are a chip matrix, a sequencing chip, and a manufacturing method thereof. The chip matrix includes: a wafer layer (111), the wafer layer (111) having cutting lines that are evenly distributed thereon; a first silicon oxide layer (112), the first silicon oxide layer (112) being made of silicon oxide and formed on an upper surface of the wafer layer (111); a transition metal oxide layer (113), the transition metal oxide layer (113) being made of transition metal oxide and formed on an upper surface of the first silicon oxide layer (112). The chip matrix has characteristics such as resistances against high temperature, high humidity and other harsh environments. Meanwhile, by changing pH, surfactant and other components of a solution containing sequences to be sequenced, a surface functional region of the chip matrix can specifically adsorb a sequence to be sequenced.
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The present application is a continuation of International Application No. PCT/CN2019/073332 filed Jan. 1, 28, 2019, which is incorporated herein by reference in its entirety.
TECHNICAL FIELDThe present disclosure relates to the field of biotechnology, and particularly, to a sequencing chip and a manufacturing method therefor.
BACKGROUNDThe microarray sequencing chip is one of the prerequisites for high-throughput sequencing. In the current DNA Nano Ball (DNB) sequencing technology, DNBs are required to be fixed on a sequencing chip for subsequent sequencing biochemical reactions. As an example, for the sequencing chips now in use, nearly 200 million DNB-binding sites are provided on a surface of each chip. In order to stably fix the DNBs to the binding sites, the surface of the sequencing chip is required to subject to an amination treatment. In addition, regions on the chip surface other than binding sites are required to subjected other treatments, in order to reduce non-specific adsorption as much as possible, reduce background optical signal, and improve sequencing quality. Accordingly, one of the basic tasks for achieving high-quality sequencing is to manufacture sequencing chips with microarrays efficiently and with lost cost.
The existing method for manufacturing sequencing chip mainly includes the following steps. A nano-array patterned photoresist layer is first formed on a silicon wafer through a semiconductor process. The patterned layer may include multiple units with the same structure, and each unit can serve as one sequencing chip. Then the wafer including the patterned layer is subjected to a chemical vapor deposition to form an amination layer in a functional region of the wafer. Through an assembly process, the wafer is divided into individual chips, which are assembled into sequencing chips suitable for sequencing.
The process of forming the patterned photoresist layer on the silicon wafer includes: providing a silicon wafer, and forming a silicon oxide layer on a surface of the silicon wafer; then forming a hexamethyldisiloxane (HMDS) layer on the silicon oxide layer through chemical vapor deposition (CVD) or spin coating, and forming a patterned photoresist layer through standard photolithography, developing, and oxygen plasma etching processes. In the patterned photoresist layer, a part of the photoresist layer, which has been etched away through developing and subjected to the oxygen plasma treatment, can expose the underlying silicon oxide layer. The patterned photoresist layer includes a plurality of units with the same nano-array structure, and each unit can form a sequencing chip.
The process of forming an amination layer in the functional region includes: performing an amination treatment on the silicon wafer formed with the patterned photoresist layer through chemical vapor deposition. As results, the amination layer is formed on the silicon oxide layer in a region where the photoresist is absent and the silicon oxide is exposed, while the amination layer is formed on the photoresist layer in other regions that are covered by the photoresist.
The assembly process includes: coating the wafer that has been subjected to the amination treatment with a second protective photoresist layer, cutting the wafer through a wafer dicing process to form multiple individual chips, removing the photoresist on the individual chips to form a functionalized array pattern including aminated regions and HMDS regions that are alternately arranged on the surface, and assembling the chip with a frame and a cover glass through glue or other adhesives and forming a sequencing chip containing a fluid channel and liquid inlet and outlet. The fluid channel is formed between the cover glass and the silicon chips and is isolated by the glue or adhesive, and the liquid inlet and outlet can be located on the frame or the cover glass.
After the sequencing chip is formed, the DNB sample to be sequenced is injected into the fluid channel via the liquid inlet and outlet, and contacts the functionalized array of the silicon chip including the alternately arranged aminated regions and the HMDS regions. The DNBs can be selectively adsorbed by the aminated regions and repelled by the HMDS regions, and thus they can be arranged in an array to form a DNB array on the surface. By acquiring the signal emitted by the DNB array with an optical method, the arrangement of the bases on the DNBs can be identified for sequencing applications.
The sequencing chip prepared as above can be used for sequencing in such a manner that DNBs are selectively adsorbed by the aminated regions and HMDS regions on the surface of the silicon chips. However, the aminated region and the HMDS region are a monomolecular layer on the surface of the silicon oxide, and the monomolecular layer on the surface may be easily damaged through physical and chemical contact (such as surface scratching, high temperature or contacts with other chemical reactive reagent) in the process of assembling or usage, thereby affecting the performance of the sequencing chip, or even causing scrapping of the chip. In this regard, the efficiency of generating valid data may be affected when using the sequencing chip for sequencing applications, the yield of the sequencing chip can also be reduced, which lowers the output of the sequencing chip, and indirectly increases the cost of the sequencing chip.
Therefore, it is urgent to develop an efficient, low-cost, and environmentally friendly sequencing chip.
SUMMARYIn view of the drawbacks of the existing sequencing chips mentioned above, the present disclosure provides a new sequencing chip structure and a manufacturing method, which is more stable and reliable, and have better performance. In the present disclosure, instead of using the monomolecular layer to form a DNB array, a patterned array (well-like or spot-like) of metal oxide regions and silicon oxide regions that are alternately present on a surface of a silicon wafer is adopted to selectively adsorb DNBs and to form a DNB array for sequencing. The sequencing chip of the present disclosure is also prepared by a semiconductor process. First, a patterned array of transition metal oxide regions and silicon oxide regions that are alternately present is formed on a wafer, then the wafer is cut into a plurality of individual chips by a dicing process, and a sequencing chip is formed by assembling one single chip. The DNB-binding site regions (i.e., functional regions, or transition metal oxide regions) and the DNB non-binding site regions (i.e., non-functional regions, silicon oxide regions) on the chip surface can be selectively modified by utilizing the difference in surface properties between a transition metal oxide surface and a silicon oxide surface. Moreover, in order to further improve the specific binding of the functional regions of the chip surface (the DNB-binding site regions) to the DNBs, applicants also propose for the first time to introduce amino groups onto the transition metal oxide. In addition, applicants also propose for the first time to modify the non-functional regions of the chip surface (i.e., the DNB non-binding site regions) with a copolymer having a good biocompatibility (such as polyethylene glycol-based compounds), in order to reduce the DNB-binding of the non-functional regions on the chip surface and to further improve the specific DNB-binding of the functional regions on the chip surface. In this way, the quality of sequencing can be improved. The sequencing chip of the present disclosure has the advantages in that, the surface of the silicon wafer is an array formed by the metal oxide regions and the silicon oxide regions that are alternately arranged, which is more stable and reliable than an array formed by a monomolecular layer. Thus, a data output efficiency of the sequencing chip can be improved, the output of the sequencing chip is enhanced, and the cost can be reduced. In addition, the present disclosure also provides preferred structural sizes of the sequencing chip based on optical simulation results, and these preferred structural sizes can intensify the signal emitted by the sample to be tested, thereby improving the performance of the sequencing chip.
In a first aspect of the present disclosure, the present disclosure provides a chip matrix. According to an embodiment of the present disclosure, the chip matrix includes: a wafer layer having cutting lines that are evenly distributed on the wafer layer; a first silicon oxide layer, the first silicon oxide layer being made of silicon oxide and formed on an upper surface of the wafer layer; and a transition metal oxide layer, the transition metal oxide layer being made of a transition metal oxide and formed on an upper surface of the first silicon oxide layer.
Unless otherwise specified, the “chip matrix” in the present disclosure refers to a wafer that can be divided into sequencing chip units. For example, the chip matrix according to the embodiments of the present disclosure can be divided into chip units, the chip units can be further assembled into a sequencing chip body, and a sequencing chip is formed by the sequencing chip body and a supporting frame with a liquid inlet and outlet.
The chip matrix according to the embodiments of the present disclosure has a transition metal oxide layer made of a transition metal oxide and a silicon oxide layer made of silicon oxide. The transition metal oxide and the silicon oxide have different properties. Therefore, the sequences to be sequenced, especially DNBs can be selectively adsorbed on the transition metal oxide regions of the chip matrix according to the embodiments of the present disclosure, by changing pH, surfactant composition or others of a solution containing the sequences to be tested. In this case, the chip matrix according to the embodiments of the present disclosure can be divided into two regions, i.e., a sequence-binding site region (i.e., functional region) and a sequence non-binding site region (i.e., non-functional region). It is understandable that, the transition metal oxide layer on the sequencing matrix serves as the functional region that specifically binds to the sequences to be sequenced, while the silicon oxide layer that cannot bind to the sequences to be sequenced serves as the non-functional region. In addition, the binding site regions and non-binding site regions of the sequencing sequence can be selectively modified to further enhance the transition metal oxide region's capability of selectively adsorbing the sequences to be tested. The chip matrix according to the embodiments of the present disclosure has the characteristics such as resistance against high temperature, high humidity and other harsh environments.
In a second aspect of the present disclosure, the present disclosure provides a sequencing chip. According to an embodiment of the present disclosure, the sequencing chip includes a chip body, the chip body includes a plurality of chip units, and the plurality of chip units is obtained by cutting the aforementioned chip matrix along the cutting lines of the wafer layer. Applicants found that the sequences to be sequenced can be selectively adsorbed on the transition metal oxide layer by changing pH and surfactant composition of the solution containing the sequences to be sequenced, especially DNBs. The sequencing chip according to the embodiments of the present disclosure is more stable and the sequencing results thereof is more reliable, thereby significantly improving the data output efficiency of the sequencing chip, increasing the output of the sequencing chip, and significantly reducing the sequencing cost.
In a third aspect of the present disclosure, the present disclosure provides a method for manufacturing the aforementioned chip matrix. According to the embodiments of the present disclosure, the method includes: performing surface modification on the wafer layer. The surface modification includes: treating a surface of the wafer layer with a transition metal oxide to form the transition metal oxide layer. The transition metal oxide layer is formed on an upper surface of the first silicon oxide layer, the first silicon oxide layer is provided on the upper surface of the wafer layer, and the silicon oxide layer is made of silicon oxide, and the wafer layer has cutting lines evenly distributed on the wafer layer. The method according to the embodiments of the present disclosure is simple to operate and environmentally friendly.
In a fourth aspect of the present disclosure, the present disclosure provides a method for manufacturing a sequencing chip. According to the embodiments of the present disclosure, the method includes: assembling a chip unit. The chip unit is obtained by cutting a chip matrix along cutting lines of a wafer layer of the chip matrix, and the chip matrix is as defined above or obtained by the method described above. The method according to the embodiments of the present disclosure is simple to operate, and the production yield of the sequencing chips is high.
In a fifth aspect of the present disclosure, the present disclosure provides a sequencing method. According to the embodiments of the present disclosure, the method includes: performing sequencing using a sequencing chip, the sequencing chip is as defined above or manufactured by the method described above. According to the method of the embodiments of the present disclosure, the sequencing results are more accurate and the cost is lower.
- 1-10: wafer structure
- 11 and 12: individual chips on wafer
- 111: wafer substrate structure
- 112: silicon oxide layer
- 113: patterned transition metal oxide layer (i.e., transition metal oxide “spots”)
- 1-20: multiple individual wafer structures
- 121: cutting slot
- 1-30: assembled sequencing chip formed by one individual chip
- 131: frame structure
- 132: cover glass
- 133: liquid inlet and outlet
- 134: fluid channel
- 1-40: sequencing chip formed after performing a surface functionalization modification
- 141: amino group
- 142: polyethylene glycol molecular layer
- 1-50A: sequencing chip containing DNB array formed after DNBs are loaded
- 1-50B: sequencing chip in which a DNB array is formed
- 151: DNB sample
- 152: light source and camera
- 2-10: wafer structure formed by forming a silicon oxide layer and a transition metal oxide layer on a bare wafer
- 21 and 22: individual chips
- 211: wafer substrate
- 212: silicon oxide layer
- 213: transition metal oxide layer
- 2-20: wafer formed after forming a silicon oxide layer with patterned “well” structures on a transition metal oxide layer included in a wafer
- 221: silicon oxide layer
- 222: “well” structures discretely arranged in an array
- 2-30: multiple individual chips formed after a wafer structure is subjected to a dicing process
- 231: cutting slot
- 2-40: assembled sequencing chip formed by one individual chip
- 241: frame
- 242: cover glass
- 243: liquid inlet and outlet
- 244: fluid channel
- 2-50: sequencing chip formed after performing a surface functionalization modification
- 251: silicon oxide layer
- 252: transition metal oxide layer
- 2-60A: sequencing chip with a DNB array formed after DNBs are loaded on the sequencing chip
- 2-60B: sequencing chip in which a DNB array is formed
- 261: DNB
- 262: excitation light source/camera structure
- 3-10: wafer structure having a patterned transition metal oxide layer
- 31 and 32: individual chips
- 311: wafer
- 312: silicon oxide layer
- 313: transition metal oxide layer
- 3-20: wafer structure formed after a silicon oxide layer with patterned “well” structures is formed on a wafer containing a patterned transition metal oxide layer
- 321: silicon oxide layer
- 322: “well” structure on the silicon oxide layer
- 3-30: multiple individual chips, which are separated by cutting slots and formed after performing a dicing process on a wafer structure
- 331: cutting slot
- 3-40: assembled sequencing chip formed by one individual chip
- 341: frame
- 342: cover glass
- 343: liquid inlet and outlet
- 344: fluid channel
- 3-50: sequencing chip formed after performing a surface functionalization modification
- 351: silicon oxide layer
- 352: transition metal oxide layer
- 3-60A: sequencing chip having a DNB array, which is formed after performing surface functionalization treatment on the sequencing chip and loading with DNBs
- 361: DNB
- 362: excitation light source/camera structure
- 3-60B: sequencing chip in which a DNB array is formed
- 4-10: wafer structure formed by forming a patterned transition metal oxide layer on a silicon oxide layer of a quartz wafer
- 41 and 42: individual chips on wafer
- 411: quartz wafer
- 412: silicon oxide layer
- 413: patterned transition metal oxide layer
- 4-20: multiple individual chips that are separated by cutting slots and formed after a wafer is subjected to a dicing process
- 421: cutting slot
- 4-30: sequencing chip formed by packaging one individual chip
- 431: frame
- 432: liquid inlet and outlet
- 433: fluid channel
- 4-40: sequencing chip formed after performing a surface functionalization modification
- 441: silicon oxide layer
- 442: transition metal oxide layer
- 4-50A: sequencing chip having a DNB array, formed after the sequencing chip is subjected to a surface functionalization modification and DNBs are loaded
- 4-50B: sequencing chip in which a DNB array is formed
- 451: DNB
- 452: excitation light source/camera
- 5-10: wafer structure formed by forming a silicon oxide layer and a transition metal oxide layer on a bare wafer
- 51 and 52: individual chips on wafer
- 511: wafer substrate
- 512: silicon oxide layer
- 513: patterned transition metal oxide layer
- 5-20: wafer formed by forming a silicon oxide layer with patterned “well” structures on a transition metal oxide layer included in the wafer
- 521: silicon oxide layer
- 522: transition metal oxide layer
- 5-30: multiple individual chips formed after the wafer structure is subjected to a dicing process
- 531: cutting slot
- 5-40: assembled sequencing chip formed by one individual chip
- 541: frame
- 542: liquid inlet and outlet
- 5-50: sequencing chip formed after performing a surface functionalization modification on the sequencing chip
- 551: silicon oxide layer
- 552: transition metal oxide layer
- 5-60A: sequencing chip having a DNB array, formed after the sequencing chip is subjected to a surface functionalization modification and DNBs are loaded
- 5-60B: sequencing chip in which a DNB array is formed
- 561: DNB
- 562: excitation light source/camera
- 6-10: wafer structure containing a patterned transition metal oxide layer
- 61 and 62: individual chips on a wafer
- 611: wafer
- 612: silicon oxide layer
- 613: transition metal oxide layer
- 6-20: wafer structure formed by forming a silicon oxide layer having patterned “well” structures on the wafer containing a patterned transition metal oxide layer
- 621: silicon oxide layer
- 622: “well” structure on the silicon oxide layer
- 6-30: multiple individual chips separated by cutting slots and formed after the wafer structure is subjected to a dicing process
- 631: cutting slot
- 6-40: sequencing chip formed after packaging one individual chip
- 641: frame
- 642: liquid inlet and outlet
- 6-50: sequencing chip formed after the sequencing chip is subjected to a surface functionalization modification
- 651: silicon oxide layer
- 652: transition metal oxide layer
- 6-60A: sequencing chip having a DNB array, formed after the sequencing chip is subjected to a surface functionalization modification and DNBs are loaded
- 6-60B: sequencing chip in which a DNB array is formed
- 661: DNB
- 662: excitation light source/camera
- 7-10: CMOS image sensor wafer
- 71 and 72: two chips
- 73: photosensitive layer
- 74: interconnection layer
- 75: substrate layer
- 711: silicon substrate
- 712: CMOS processing circuit layer
- 713: dielectric layer
- 714: metal wiring
- 715: semiconductor material
- 716: photosensitive part
- 717: dielectric film layer
- 718: silicon oxide layer
- 719: pad on the chip
- 720: interconnection silicon through-hole
- 7-20A: wafer structure formed after forming a patterned transition metal oxide layer with a “spot” structure on a CMOS image sensor wafer
- 721: transition metal oxide region
- 7-20B: wafer structure formed after forming a patterned transition metal oxide layer with a “well” structure on a CMOS image sensor wafer
- 722: transition metal oxide region
- 723: silicon oxide region
- 724: transition metal oxide region having a “well” structure
- 7-20C: wafer structure formed after forming a patterned transition metal oxide layer with another “well” structure on a CMOS image sensor wafer
- 725: transition metal oxide region
- 726: silicon oxide region
- 727: transition metal oxide region
- 7-30: multiple individual chips separated by a cutting slot and formed after the patterned wafer structure is subjected to a dicing process
- 731: cutting slot
- 7-40: chip structure formed after chip attaching and wire bonding
- 741: package underlay
- 742: pad on the substrate
- 743: touch point
- 744: metal connection wire
- 7-50: sequencing chip formed after a cover structure is attached to the chip structure
- 751: cover structure of support structure
- 752: liquid inlet and outlet
- 753: fluid channel
- 7-60: sequencing chip formed after the sequencing chip is subjected to a surface functionalization modification
- 761: transition metal oxide region
- 762: silicon oxide region
- 7-70A: sequencing chip with a DNB array, formed after the sequencing chip is subjected to a functionalization treatment and DNBs are loaded
- 7-70B: sequencing chip in which a DNB array is formed
- 771: DNB
- 8-10: wafer structure having a transition metal oxide layer with a structure of arrayed “spots”
- 81 and 82: individual chips on wafer
- 811: wafer substrate
- 812: silicon oxide layer
- 813: transition metal oxide layer having a structure of “spots”
- 81 and 82: multiple individual chips
- 8-20: wafer structure of multiple individual chips formed after the wafer structure is subjected to a dicing process
- 821: cutting line
- 8-30: reusable sequencing chip formed by assembling one single chip with a handle structure
- 831: handle structure
- 8-40: assembled sequencing chip immersed into a container containing a reagent
- 841: container
- 842: reagent
- 843: excitation light source/camera
Embodiments of the present disclosure are described in detail below, and examples of the embodiments are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present disclosure, but should not be construed as limitations of the present disclosure.
Unless otherwise specified, reagents, detection instruments, etc. in the examples can be self-prepared or are commercially available.
It should be noted that, a “transition metal oxide region” recited in the present disclosure refers to a region formed by transition metal oxide when viewed from a surface of a chip matrix, and a “silicon oxide region” described in the present disclosure refers to a region formed by silicon oxide when viewed from the surface of the chip matrix.
The term “patterned layer” indicates that a pattern alternately exists in a transition metal oxide region and a silicon oxide region on a wafer surface, including a “well” structure and a “spot” structure.
The term “spot” structure means that the transition metal oxide region is higher than the silicon oxide region, that is, the transition metal oxide is discretely distributed on the silicon oxide.
The expression, “the transition metal oxide layer is a continuous layer structure, and the second silicon oxide layer is formed by silicon oxide on an upper surface of the transition metal oxide layer and defines a plurality of connected wells”, means that the second silicon oxide layer has a structure of grids covering the upper surface of the transition metal oxide layer, that is, a body of the grid is made of silicon oxide, and the transition metal oxide is exposed by the recessed wells defined by the grids. It can also be understood that, the second silicon oxide layer is recessed like wells, forming a pattern of grids on the upper surface of the transition metal oxide layer. The term “chip matrix” can be divided into individual chips, which can be assembled into sequencing chips suitable for sequencing. The wafer structure may contain tens to thousands of identical individual chips (depending upon a wafer size and a chip size), and an extremely narrow non-functional spacing is reserved between the chips, and the spacing is also referred as to a cutting line.
The preparation of the sequencing chip of the present disclosure is not particularly limited, and can adopt a conventional method for manufacturing the sequencing chip from a wafer material in the related art, depending on different wafer materials used, with a difference from the sequencing chip in the related art in that the individual chip used is different.
The term “individual chip” refers to a chip obtained by cutting the “chip matrix” in the present disclosure along the cutting line, and can also be called “chip unit”.
Chip MatrixIn the first aspect of the present disclosure, the present disclosure provides a chip matrix. According to the embodiments of the present disclosure, the chip matrix includes: a wafer layer having cutting lines that are uniformly distributed on the wafer layer; a first silicon oxide layer made of silicon oxide and formed on an upper surface of the wafer layer; a transition metal oxide layer made of transition metal oxide and formed on an upper surface of the first silicon oxide layer. According to the embodiment of the present disclosure, a surface of the chip matrix includes two regions, namely a binding site region (transition metal oxide region, i.e., a functional region) of sequences to be sequenced (especially DNBs) and a non-binding site region (silicon oxide, i.e., a non-functional region) of the sequences to be sequenced. Applicants found that, by using the different surface properties of the transition metal oxide region and the silicon oxide region on the chip matrix, the sequences to be sequenced can be selectively adsorbed on the transition metal oxide layer by changing pH and a surfactant composition of a solution containing the sequences to be sequenced. In addition, the transition metal oxide region and non-functional region can be selectively modified to further enhance the transition metal oxide region's capability of selectively adsorbing DNBs.
According to an embodiment of the present disclosure, the transition metal oxide layer is constituted by a plurality of unconnected transition metal oxide spots. The transition metal oxide can be discretely distributed on the surface of silicon oxide through conventional methods such as sputtering, electron beam evaporation or thermal evaporation atomic layer deposition to form a patterned transition metal oxide layer in form of “spots”. Thus, when viewed from the surface, transition metal oxide spots that specifically bind to the sequences to be sequences and silicon oxide regions that are located between the spots and cannot bind to the sequencing sequence are formed on the chip matrix.
According to an embodiment of the present disclosure, the transition metal oxide spots have a thickness of 10-20 nm, and the first silicon oxide layer has a thickness of 80-100 nm, preferably 90 nm. Through simulation calculations, Applicants found that a chip matrix, in which the thickness of the transition metal oxide spots ranges from 10 to 20 nm and the thickness of the silicon oxide layer (i.e., the first silicon oxide layer) ranges from 80 to 100 nm, preferably 90 nm, has a higher reflectivity for light emitted by the sequences to be sequenced, especially the DNBs, so that light signals emitted by the sequences to be sequenced, especially by the DNBs, can be captured by a signal detection device as much as possible, which indirectly enhances a signal intensity of the sequences to be sequenced, especially the signal intensity of the DNBs, providing a higher signal-to-noise ratio, and significantly improving the performance of the finally obtained sequencing chip.
According to an embodiment of the present disclosure, amino groups are further connected to the transition metal oxide spots. Applicants found that amination of transition metal oxide molecules can further improve the adsorption specificity of the surface functional region of the chip matrix for the DNBs. Therefore, by adjusting the pH and surfactant composition of the reagent contain DNBs, the surface functional region of the chip matrix has stronger DNB-specific adsorption function.
According to an embodiment of the present disclosure, polyethylene glycol is further connected to the first silicon oxide layer between the plurality of unconnected transition metal oxide spots. As a result, the DNB non-specific adsorption of the non-functional region on the surface of the chip matrix is further reduced.
According to an embodiment of the present disclosure, the chip matrix further includes a second silicon oxide layer.
According to an embodiment of the present disclosure, the transition metal oxide layer is a continuous layer structure, and the second silicon oxide layer is made of silicon oxide and formed on the upper surface of the transition metal oxide layer as a plurality of wells that are connected to each other. It should be noted that the continuous layer structure means that the transition metal oxide is spread over the upper surface of the first silicon oxide layer. As a result, one or more second silicon oxide layers having wells are covered on the transition metal oxide layer, to obtain a pattern in which the patterned transition metal oxide and silicon oxide are alternately present.
According to an embodiment of the present disclosure, the transition metal oxide layer consists of a plurality of unconnected transition metal oxide spots, and the second silicon oxide layer is formed between the plurality of unconnected transition metal oxide spots on the upper surface of the first silicon oxide layer. It can be understood that the second silicon oxide layer and the transition metal oxide spots can form wells, where the transition metal oxide is located in recesses of the wells, and the second silicon oxide layer constitutes a grid body of wells. In this case, the second silicon oxide layer can be higher than the transition metal oxide layer, or be as high as the transition metal oxide layer.
According to an embodiment of the present disclosure, the wafer is a silicon wafer, the second silicon oxide layer has a thickness ranging from 40 nm to 60 nm, preferably 50 nm, the transition metal oxide layer has a thickness ranging from 5 nm to 15nm, and the first silicon oxide layer has a thickness ranging from 80 nm to 100 nm, preferably 90 nm.
Through simulation calculation, Applicants found that, the chip matrix has a higher reflectivity for light emitted by the sequences to be sequenced, especially light emitted by the DNBs, when the wafer is a silicon wafer, and in the chip matrix formed with the well structures, the thickness of the second silicon oxide layer is from 40 nm to 60 nm, preferably 50 nm, the thickness of the transition metal oxide layer is from 5 nm to 15 nm, and the thickness of the first silicon oxide layer is 80 nm to 100 nm, preferably 90 nm. Thus, the light signal emitted by the sequences to be sequenced, especially by the DNBs, can be captured by the signal detection device as much as possible, which indirectly enhances the signal strength of the sequences to be sequenced, especially the DNBs, thereby increasing the signal-to-noise ratio, and significantly improving the performance of the finally obtained sequencing chip.
According to an embodiment of the present disclosure, the wafer is a quartz wafer, the thickness of the second silicon oxide layer is 100 nm to 200 nm, the thickness of the transition metal oxide layer is 10 nm to 20 nm, and the thickness of the first silicon oxide layer is 80 nm to 100 nm, preferably 90 nm. Through simulation calculation, Applicants found that the chip matrix has a higher reflectivity for light emitted by the sequences to be sequenced, especially by the DNBs, when the wafer is a quartz wafer, and in the chip matrix formed with the well structures, the thickness of the second silicon oxide layer is 100 nm to 200 nm, the thickness of the transition metal oxide layer is 10 nm to 20 nm, and the thickness of the first silicon oxide layer is 80 nm to 100 nm, preferably 90 nm. Thus, the light signal emitted by the sequences to be sequenced, especially by the DNBs, can be captured by the signal detection device as much as possible, which indirectly enhances the signal strength of the sequences to be sequenced, especially the DNBs, thereby increasing the signal-to-noise ratio and significantly improving the performance of the finally obtained sequencing chip. Moreover, when the thickness of the second silicon oxide layer is 100 nm to 200 nm, it not only ensures that the well structures in the finally formed sequencing chip have an appropriate depth to load the sequences to be sequenced, especially the DNBs, but also enables the camera to collect fluorescence signals with a relatively higher intensity.
According to an embodiment of the present disclosure, amino groups are further connected to the transition metal oxide layer located at the recesses of the wells of the second silicon oxide layer or to the transition metal oxide spots. Applicants found that amination of transition metal oxide molecules can further improve the adsorption specificity of the surface functional region of the chip matrix for the sequences to be sequenced. Therefore, the surface of the functional region of the chip matrix can specifically adsorb the sequences to be sequenced by adjusting the pH and the surfactant composition of the sequences to be sequenced.
According to an embodiment of the present disclosure, polyethylene glycol is connected to the second silicon oxide layer. As a result, the non-specific adsorption of the non-functional region of the chip surface for the DNBs is further reduced.
According to an embodiment of the present disclosure, the amino groups are bonded to at least a part of the transition metal oxide molecules in the transition metal oxide layer through chemical bonds. The “chemical bonds” refer to transition metal-O—P bonds (such as Zr—O—P bond, Ti—O—P bond, Ta—O—P bond). As a result, the amino groups and the transition metal oxide are closely bonded together.
According to an embodiment of the present disclosure, the chemical bonds are formed by connecting the transition metal oxide molecules with phosphate groups of aminophosphonic acid-based compounds. Applicants applied the fact that the phosphonic acid group does not react with the silicon oxide layer but reacts specifically with the transition metal oxide molecules, and the aminophosphonic acid-based compounds can specifically introduce the amino groups onto the transition metal oxide molecules.
According to an embodiment of the present disclosure, the polyethylene glycol is provided by at least one selected from polyethyleneimine-polyethylene glycol and a silane coupling agent containing polyethylene glycol. As a result, the non-specific adsorption of the surface non-functional region of the chip matrix for the DNBs is further reduced.
According to an embodiment of the present disclosure, the polyethylene glycol is provided by polyethyleneimine-polyethylene glycol, and the polyethyleneimine-polyethylene glycol is electrostatically adsorbed on a surface of the first silicon oxide layer or a surface of the second silicon oxide layer.
According to an embodiment of the present disclosure, the polyethylene glycol is provided by the silane coupling agent containing polyethylene glycol, and the silane coupling agent containing polyethylene glycol is connected to the first silicon oxide layer or the second silicon oxide layer through a —Si—O—Si— chain.
It should be noted that the material of the wafer according to the embodiments of the present disclosure is not limited. According to a specific embodiment of the present disclosure, the wafer includes at least one selected from a silicon wafer, a quartz wafer, a glass wafer, and a CMOS wafer.
According to an embodiment of the present disclosure, the transition metal oxide includes at least one selected from titanium dioxide, zirconium dioxide, tantalum pentoxide, niobium hexaoxide, and hafnium dioxide.
According to an embodiment of the present disclosure, the transition metal oxide includes at least one selected from titanium dioxide, zirconium dioxide, and tantalum pentoxide.
Sequencing ChipIn a second aspect of the present disclosure, the present disclosure provides a sequencing chip. According to an embodiment of the present disclosure, the sequencing chip includes a chip body, the chip body includes a plurality of chip units, and the chip units are obtained by cutting the aforementioned chip matrix along the cutting line of the wafer layer. Applicants found that the selective adsorption of the sequences to be sequenced on the transition metal oxide layer can be achieved only by changing the pH and surfactant composition of the solution containing the sequences to be sequenced. The sequencing chip according to the embodiments of the present disclosure is more stable and the sequencing results thereof are more reliable, which can significantly improve the data output efficiency of the sequencing chip, thereby increasing the output of the sequencing chip and significantly reducing the sequencing cost.
The structure of the sequencing chip according to the embodiment of the present disclosure may not require a surface monomolecular layer, or may be subjected to surface modification after the chip preparation process is completed. Therefore, the sequencing chip of the present disclosure has the characteristics of stable properties, and thus it can withstand physical contact such as scratches without affecting the performance of the sequencing chip, and it can tolerate high temperature and chemical reagent corrosion. As a result, the chip can withstand more stringent, but more efficient processing and assembly processes, and is less likely to be damaged during packaging, transportation and preparations prior to use. Therefore, the production yield of the sequencing chip is improved, and the data output efficiency of the sequencing chip is increased, thereby reducing the cost.
Method for Manufacturing the Chip MatrixIn a third aspect of the present disclosure, the present disclosure provides a method for manufacturing the chip matrix. According to an embodiment of the present disclosure, the method includes: performing a surface modification on the wafer layer. The surface modification includes treating a surface of the wafer layer with a transition metal oxide to form a transition metal oxide layer, where the transition metal oxide layer is formed on an upper surface of the first silicon oxide layer, the first silicon oxide layer is provided on the upper surface of the wafer layer, and the silicon oxide layer is made of silicon oxide, and the wafer layer has cutting lines evenly distributed on the wafer layer. The method according to the embodiments of the present disclosure is simple to operate and environmentally friendly.
According to an embodiment of the present disclosure, the first silicon oxide layer is formed in advance on the upper surface of the wafer layer by low-temperature plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, or atomic layer deposition. It should be noted that the method of forming the first silicon oxide layer on the wafer surface is not limited, and can be performed with conventional semiconductor process techniques, such as low-temperature plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, atomic layer deposition, etc.
According to an embodiment of the present disclosure, the surface modification of the wafer layer is achieved by thin film deposition, photolithography or etching to form a continuous transition metal oxide layer or a transition metal oxide layer in form of spots.
According to a specific embodiment of the present disclosure, a patterned transition metal oxide layer is formed on the upper surface of the silicon oxide layer. The transition metal oxide can be titanium dioxide, zirconium dioxide, tantalum pentoxide, niobium hexaoxide, hafnium dioxide, or any combinations thereof. The transition metal oxide layer is discretely distributed on the silicon oxide layer, and forms a specific array pattern (i.e., an array of transition metal oxide spots and specially designed graphics or lines, for calibration of optical sequencing in the later stage), and has the same pattern arrangement on each individual chip. This patterned layer can be realized by conventional semiconductor process technique, such as thin film deposition, photolithography, and etching processes. That is, a transition metal oxide layer is first formed on the silicon oxide layer to cover the entire wafer by sputtering, electron beam evaporation, thermal evaporation atomic layer deposition or other thin film deposition techniques, then a hard mask material layer corresponding to the desired patterned layer is formed on the metal oxide layer through thin film deposition, photolithography, and etching, and finally the pattern of the hard mask material layer is re-etched onto the transition metal oxide layer through an etching process to form a patterned transition metal oxide layer, i.e., the discretely arranged transition metal oxide is arranged as orderly arranged “spots” on the silicon oxide layer, and the region without the transition metal oxide “spots” exposes the silicon oxide layer. The size of a “spot”-like transition metal oxide region is the same as or slightly smaller than the size of the DNB, so that one “spot” adsorbs only one DNB.
According to an embodiment of the present disclosure, the transition metal oxide layer is a continuous layer structure, and the method further includes forming a second silicon oxide layer from silicon oxide on the upper surface of the transition metal oxide layer. The second silicon oxide layer is arranged in form of continuous wells. Said forming is mainly achieved by atomic layer deposition. According to a specific embodiment of the present disclosure, a first silicon oxide layer is first formed on the wafer, then one transition metal oxide layer is formed on the first silicon oxide layer, and then an array of discretely arranged “well” structures is formed on the transition metal oxide layer through photolithography and etching techniques known in the conventional semiconductor process. The transition metal oxide layer is exposed at a bottom of the “well” structure, and the periphery of the “well” structure is the silicon oxide layer higher than the transition metal oxide layer. The size of the “well” is the same as or slightly smaller than a size of a DNB, so that each “well” structure only bonds to one DNB.
According to an embodiment of the present disclosure, the transition metal oxide layer is arranged in form of spots, and the method further includes depositing silicon oxide between the spots of the transition metal oxide layer to form a second silicon oxide layer. Said depositing is mainly achieved by atomic layer deposition. According to a specific embodiment of the present disclosure, a first silicon oxide layer is formed on the wafer first, and then an array of discretely arranged “well” structures is formed on the silicon oxide layer by photolithography and etching techniques in the conventional semiconductor process. The bottom of the “well” structure is the exposed transition metal oxide layer, the periphery of the silicon oxide layer “well” structure is higher than or as high as the transition metal oxide layer. The size of the “well” is the same as or slightly smaller than the size of the DNB, so that each “well” structure only bonds to one DNB.
According to an embodiment of the present disclosure, the method further includes performing an amination treatment on the transition metal oxide. As a result, amino groups can be introduced into the functional region of the chip matrix to further improve the functional region's capability of selectively adsorbing the sequences to be sequenced, especially the DNBs.
According to an embodiment of the present disclosure, the amination treatment is achieved by reacting the transition metal oxide with an aminophosphonic acid-based compound. As a result, the aminophosphonic acid-based compound and the transition metal oxide can form a transition metal-O—P bond (such as a Zr—O—P bond, a Ti—O—P bond, and a Ta—O—P bond). Furthermore, amino groups can be introduced to the functional region of the chip matrix to further improve the functional region's capability of selectively adsorbing the sequences to be sequenced, especially the DNBs.
According to the embodiment of the present disclosure, the method further includes performing a surface modification on the first silicon oxide layer or the second silicon oxide layer to introduce polyethylene glycol to the first silicon oxide layer or the second silicon oxide layer. As a result, the adsorption capability of the non-functional region of the chip matrix for the sequences to be sequenced, especially the DNBs, can be further reduced.
According to an embodiment of the present disclosure, the polyethylene glycol is provided by at least one selected from polyethyleneimine-polyethylene glycol and a silane coupling agent containing polyethylene glycol.
According to an embodiment of the present disclosure, the polyethylene glycol is provided by polyethyleneimine-polyethylene glycol, and the surface modification is performed by electrostatic adsorption of polyethyleneimine-polyethylene glycol on the surface of the first silicon oxide layer or the surface of the second silicon oxide layer. Thus, polyethylene glycol can be introduced into the non-functional region of the chip matrix.
According to an embodiment of the present disclosure, the polyethylene glycol is provided by the silane coupling agent containing polyethylene glycol, and the surface modification is performed by condensation reaction of the silane coupling agent containing polyethylene glycol with hydroxyl groups of the first silicon oxide layer or the second silicon oxide layer, and the hydroxyl groups are provided by Si—OH generated after the ionized first or second silicon oxide layer adsorbs hydroxide ions in the water. Thus, polyethylene glycol can be introduced into the non-functional region of the chip matrix.
Method for Manufacturing Sequencing ChipIn a fourth aspect of the present disclosure, the present disclosure provides a method for manufacturing a sequencing chip. According to an embodiment of the present disclosure, the method includes: assembling a chip unit. The chip unit is obtained by cutting the chip matrix along the cutting lines of the wafer layer, and the chip matrix is as defined as above or obtained by the method described as above. The method according to the embodiment of the present disclosure is simple to operate, and has a high yield of the prepared sequencing chip.
According to an embodiment of the present disclosure, the cutting is realized by a semiconductor wafer dicing method.
According to an embodiment of the present disclosure, said assembling includes: placing the chip unit in a supporting frame containing a liquid inlet and outlet, and bonding the chip unit to the supporting frame with a glue or adhesive, with a fluid channel being formed between the frame and the chip unit.
According to an embodiment of the present disclosure, the wafer is a silicon wafer, and the assembling includes: bonding the chip unit to the supporting frame, with an upper surface the chip unit facing upward, and placing a cover glass on the upper surface of the chip unit to obtain the sequencing chip.
According to an embodiment of the present disclosure, the wafer is a quartz wafer or a glass wafer, and said assembling includes: attaching the chip unit to the supporting frame, with a lower surface of the chip unit facing upward, to obtain the sequencing chip.
According to an embodiment of the present disclosure, the wafer is a CMOS wafer, and said assembling includes: bonding a lower surface of the chip unit to a substrate (i.e., a photosensitive element). The chip unit is connected to the substrate by a lead, and the lead is configured to transmit an electrical signal on the chip unit to the substrate.
According to an embodiment of the present disclosure, the substrate is in form of, but not limited to, LGA, CLCC, PLCC, or the like.
According to an embodiment of the present disclosure, a metal wire used for the wire bonding includes, but is not limited to, gold wire, aluminum wire, and the like.
Sequencing MethodIn a fifth aspect of the present disclosure, the present disclosure provides a sequencing method. According to the embodiments of the present disclosure, the method includes: performing sequencing using a sequencing chip. The sequencing chip is defined as above or prepared by the method described above. According to the method of the embodiment of the present disclosure, the sequencing has a more accurate result and a lower cost.
According to an embodiment of the present disclosure, the transition metal oxide layer of the sequencing chip is pre-fixed with DNBs. A DNB sample can be considered as a point light source, and the light emitted by the DNB sample can be collected by a camera or CMOS image sensor, and then sequenced.
The embodiments of the present disclosure are described in detail below.
Example 1: Method for Manufacturing a Sequencing Chip Having “Spot”-Structured Transition Metal Oxide on a Silicon or Quartz WaferReferring to
The results are shown in
When the thickness of the silicon oxide layer is about 90 nm, the silicon oxide layer has the optimal reflection effect for the light signal emitted by the DNB sample, that is, the intensity of fluorescence signal captured by the camera is the highest. Then, during the simulation calculation, a relation between a change in the thickness of the transition metal oxide layer and the intensity of fluorescence signal is determined when the thickness of the silicon oxide layer is 90 nm, and the results are shown in
Referring to
Applicants has found optimal thicknesses of the transition metal oxide layer and the silicon oxide layer through optical simulation calculation. In this embodiment, the transition metal oxide layer is a thin film layer structure, a first silicon oxide layer is disposed under the transition metal oxide layer, and a second silicon oxide layer having arrayed “well” structures is arranged on the transition metal oxide layer. According to the simulation results in Embodiment 1, Applicants learned that, when the thickness of the transition metal oxide layer varies from 0 to 40 nm, the reflectivity of the thin film gradually decreases with an increase in the thickness of the transition metal oxide layer, resulting in a gradual decrease in the intensity of fluorescence signal acquired by the camera. Accordingly, a relation between the intensity of fluorescence signal and the thickness of the second silicon oxide layer having the arrayed “well” structures is simulated in the circumstances that the thickness of the first silicon oxide layer is 90 nm, and the thickness of the transition metal oxide layer is 0 nm, 10 nm, and 20 nm. The simulation results are shown in
When the thickness of the first silicon oxide layer is 90 nm and the thickness of the second silicon oxide layer is 50 nm, a relation between different thicknesses of the transition metal oxide layer and the intensity of fluorescence signal is simulated and calculated correspondingly. The simulation results are shown in
As shown in
In this embodiment, the transition metal oxide layer is formed as an array of “spot” structures on a first silicon oxide layer, a second silicon oxide layer having arrayed “well” structures is formed on the first silicon oxide layer, and the “well” structures of the silicon oxide layer correspond to the “spots” of the transition metal oxide layer. In the above Embodiment 1, through simulation calculation, it is determined that when the thickness of the first silicon oxide layer is 90 nm and the thickness of the transition metal oxide layer is about 10 nm to 20 nm, the reflectivity is optimized and the intensity of fluorescence signal is maximized. On this basis, a change of the intensity of fluorescence signal with the varying thickness of the second silicon oxide layer is simulated in presence of the second silicon oxide layer with the arrayed “well” structures. The simulation results are shown in
As shown in
In Embodiment 4, a silicon oxide layer is first formed on a transparent quartz wafer, then an array of transition metal oxide “spot” structures is formed on the silicon oxide layer, and the DNB sample is loaded on the transition metal oxide “spot” structures. However, in this embodiment, the camera is placed above the back of the quartz substrate, and the light signal emitted by the DNBs can be captured by the camera only after transmitting through the transition metal oxide layer, the silicon oxide layer, and the quartz substrate. Therefore, in Embodiment 4, the signal intensities of fluorescence signals, which are emitted by the DNB and can be captured by the camera after transmitting through the transition metal oxide layer, the silicon oxide layer, and the quartz substrate of different thicknesses, are calculated and compared. The simulation results are shown in
As shown in
In Embodiment 5, a first silicon oxide layer is first formed on the quartz wafer, a transition metal oxide layer is then formed on the first silicon oxide layer, and a second silicon oxide layer with arrayed “well” structures is formed on the transition metal oxide layer. In this case, the DNB sample is also loaded on the transition metal oxide layer in the “well” structures, and the light signal emitted by the DNB sample can be captured by the camera placed above the back of the quartz substrate after transmitting through the transition metal oxide layer, the first silicon oxide layer, and the quartz substrate. In this case, influences of different thicknesses of the second silicon oxide layer on the intensity of fluorescence signal transmitted through the thin film layers are simulated when the thickness of the first silicon oxide layer is 90 nm and the thickness of the transition metal oxide layer is 10 nm or 20 nm. The simulation results are shown in
As shown in
In Embodiment 6, a first silicon oxide layer is formed on the quartz wafer, then a transition metal oxide layer having arrayed “spot” structures is formed on the first silicon oxide layer, and then a second silicon oxide layer having arrayed “well” structures is formed above the transition metal oxide layer. The “well” structures of the second silicon oxide layer correspond to the “spot” structures of the transition metal oxide layer, and the transition metal oxide “spot” is located at a bottom of the “well” structure of the second silicon oxide layer. In this case, the DNB sample is also loaded on the transition metal oxide layer in the “well” structures, and the light signal emitted by the DNB sample is captured by the camera placed above the back of the quartz substrate after transmitting through the transition metal oxide layer, the first silicon oxide layer, and the quartz substrate.
In this case, influences of different thicknesses of the second silicon oxide layer on the intensity of fluorescence signal are first simulated when the thickness of the first silicon oxide layer is 90 nm, and the thickness of the transition metal oxide layer is 10 nm or 20 nm. The simulation results are shown in
As shown in
Those skilled in the art should appreciate that the structure of the CMOS image sensor chip described in the present disclosure is merely illustrative, but is not restrictive, and image sensor chips having any structures can be used in the present disclosure.
Then, as described below with reference to
In Embodiment 7, similar to the foregoing embodiments, the transition metal oxide layer and the second silicon oxide layer form three types of “spot” or “well” structures on a photosensitive structure-containing CMOS wafer provided with the first silicon oxide layer.
The three types of “spot” or “well” structures include: 1. forming, on the first silicon oxide layer, a transition metal oxide layer having arrayed “spot” structures, and loading DNBs on the “spot” structures of the transition metal oxide layer; 2. forming the transition metal oxide film on the first silicon oxide layer, forming the second silicon oxide layer having arrayed “well” structures on the transition metal oxide film, and loading DNBs on the transition metal oxide layer at the bottom of each “well” structure of the second silicon oxide layer; and 3. forming the transition metal oxide layer having arrayed “spot” structures on the first silicon oxide layer, then forming the second silicon oxide layer having arrayed “well” structures on the transition metal oxide layer, and loading DNBs on the transition metal oxide “spot” structures located at the bottoms of the “well” structures of the silicon oxide layer. In these three types of “spot” or “well” structures, the light signal emitted by DNBs can be acquired by a photosensitive structure on the CMOS wafer after passing through the transition metal oxide, the first silicon oxide layer, and an anti-reflection layer (ARC layer, usually made of tantalum pentoxide) and a PIN layer (usually made of hafnium dioxide) on the CMOS wafer. Thus, intensities of signals acquired by the photosensitive structure after the light emitted by the DNBs passes through these films is simulated. The thicknesses of the PIN layer and the ARC layer depend upon the process of the CMOS wafer and are usually constant. The thickness of the PIN layer is 6 nm, and the thickness of the ARC layer is 50 nm. Accordingly, for the above-mentioned three types of “spot” or “well” structures, the influences of the varying thicknesses of the first silicon oxide layer, the transition metal oxide layer and the second silicon oxide layer on the intensity of fluorescence signal are simulated.
For the first situation described in the present embodiment, i.e., when the first silicon oxide layer is the only one silicon oxide layer, a relation between the intensity of fluorescence signal and the thickness of the first oxide layer is simulated. The simulation results are shown in
When the thickness of the first silicon oxide layer is 150 nm, a relation between the intensity of fluorescence signal and the thickness of the transition metal oxide layer having arrayed “spot” structures on the first silicon oxide layer is then simulated. The simulation results are shown in
Then, for the second situation in Embodiment 7, a relation between the thickness of the transition metal oxide layer film and the intensity of fluorescence signal is simulated to determine the thickness of the transition metal oxide layer film, when the thickness of the first silicon oxide layer is 150 nm and the transition metal oxide layer film is formed on the first silicon oxide layer. The simulation results are shown in
Further, when the second silicon oxide layer having the “well” structures is formed thereon, a relation between the thickness of the second silicon oxide layer and the intensity of fluorescence signal is simulated. The simulation results are shown in
In this embodiment, a new method for packaging a sequencing chip is provided. The sequencing chip used in this packaging method can be reused after subjected to a special processing process, thereby greatly reducing the costs of the sequencing chip.
A patterned array of transition metal oxide “spot” or “well” structures is first formed on a semiconductor wafer. The structure of such a patterned array can be any one of the structures present on the wafers described in the above Embodiments 1 to 3 with reference to
As shown in
After a complete sequencing operation is finished, the sequencing chip in such a package structure can be treated and reused. The specific processing method is described as below.
After the sequencing is finished, the sequencing chip is pre-treated, the handle structure is removed to completely expose the entire chip, and then the chip is immersed in an SC1 washing solution (Slide Clean 1, 50 mM potassium hydroxide solution containing Triton) for 10 min, then the chip was taken out, the surface of the chip is repeatedly cleaned 3 with deionized water 3 times or more, and the chip is placed in a nitrogen stream to be dried completely.
The SC1 washing solution can be replaced by an SC2 washing solution. The specific operation steps are as below. The handle structure is removed from the sequencing chip after sequencing, the chip is placed in the SC2 washing solution (Slide Clean 2, a mixture of ammonium hydroxide and hydrogen peroxide in a certain ratio), the washing solution is heated to 80° C. and keeps the chip for 5 min, then the chip is taken out and repeatedly cleaned three times or more with deionized water, and the chip is placed in a nitrogen stream to be dried completely.
The cleaning with the washing solution described above can be replaced by plasma drying, which includes: after the sequencing, placing the sequencing chip in an argon plasma atmosphere for 30 minutes, taking out, cleaning the chip with deionized water to remove dust, and placing the chip in a nitrogen stream to dry completely.
Embodiment 9: Formation of a Microarray by Changing Loading Conditions Without Chip Surface ModificationA silicon dioxide surface is used to simulate the non-binding site region, and transition metal oxide surface of titanium dioxide or tantalum pentoxide is used to simulate the binding site region. titanium dioxide. The three types of surfaces are cleaned by using a plasma cleaner, and then further cleaned with ethanol. A DNB solution (160BP, 10 ng/μl), which is conditionally optimized by changing pH and a surfactant content of the solution, is used to load DNBs on the surface of the chip. After the loading of DNBs is completed, the DNBs are fluorescently labeled using cy3 dye, and then the surface of the chip is analyzed with a fluorescence microscope. The results are shown in
Conclusion: Due to the different surface properties of metal oxides and silicon dioxide, through changing the pH, the surfactant, and other components of the DNB solution, DNBs can be selectively adsorbed by the functional regions on the surface of the chip.
Embodiment 10: Detection of Effect on DNB Adsorption After Performing Selective Functionalization on Silicon Crystal Having an Array of Transition Metal Oxide SpotsA silicon crystal chip having an array of transition metal oxide spots is cleaned with a plasma cleaner and ethanol, then is immersed into an aminoethylphosphonic acid solution (10 mM) for 24 hours. Then the silicon crystal chip is taken out, and the surface is cleaned with ethanol and water. Elemental analysis is conducted on each of the three types of surfaces using X-ray photoelectron spectrometer. The results indicate that, before and after amination, the silicon dioxide surface does not contain phosphorus components, while a phosphorus concentration on the titanium dioxide and tantalum pentoxide surface is increased from 0 before the amination to 2% after the amination. The DNB solution (160BP, 10 ng/μl), which is identical to that used in sequencing, is used for loading DNBs on the surface of the chip. After DNB loading is finished, the DNBs are fluorescently labeled using cy3 dye, and then the surface of the chip was analyzed using a fluorescence microscope. The results are shown in
The silicon crystal chip having an array of transition metal oxide spots is manufactured by oxidizing a surface of silicon dioxide wafer available in the industry, and then plating an array of transition metal oxide spots through ALD.
Conclusion: the silicon dioxide surface has no aminophosphonic acid component, and the aminophosphonic acid component is detected on the titanium dioxide and tantalum pentoxide surface, which proves the selectivity of the phosphonic acid reaction. The modified surface allows the transition metal oxide region to be selectively aminated, and enables the functional regions on the surface of the chip to specifically adsorb DNBs.
Embodiment 11: Detection of Effect After Further Modifying Non-Functional Regions With Copolymer Containing Polyethylene GlycolIn this embodiment, a chip with special design was used. The transition metal oxide regions on the chip have a size of 200 μm, and spaced apart from each other with a spacing of 500 μm. After the chip is cleaned and modified with aminophosphonic acid as described in Embodiment 9, the chip is immersed in an aqueous solution (10 mg/ml) of polyethyleneimine-polyethylene glycol (PEI-PEG) copolymer for 10 min, and then cleaned with pure water. Then a DNB solution (160BP, 10 ng/μl), which is the same as that used in sequencing, is used to load DNBs on the surface of the chip. After DNB loading is finished, the DNBs are fluorescently labeled by using cy3 dye, and then the surface of the chip was analyzed using a fluorescence microscope. The results are shown in
Conclusion: the adsorption of DNBs and impurities on the non-functional regions of the surface of the chip can be further reduced by using copolymer containing polyethylene glycol.
Embodiment 12: Detection of Effect After Further Modifying Non-Functional Regions With Silane Coupling Agent Containing Polyethylene GlycolA silicon crystal chip having an array of transition metal oxide spots is cleaned with a plasma cleaner and ethanol, and then placed in a silane coupling agent solution modified with alendronic acid and polyethylene glycol. After a period of reaction, the silicon crystal chip was taken out, and cleaned with ethanol and water. Then a DNB solution (160 BP, 10 ng/μl), which is the same as that used in sequencing, is used to load DNBs on the surface of the chip. After DNB loading is completed, the DNBs were fluorescently labeled by using cy3 dye, and then the surface of the chip was analyzed using a fluorescence microscope, as shown in
Conclusion: the adsorption of DNBs and impurities on the non-functional regions of the silicon dioxide surface can be further reduced by using the silane coupling agent containing polyethylene glycol.
In the specification, descriptions with reference to the terms “an embodiment”, “some embodiments”, “examples”, “specific examples”, or “some examples” etc. mean that specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the above terms do not necessarily refer to the same embodiment or example. Moreover, the mentioned specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine the different embodiments or examples and combine the features of the different embodiments or examples described in this specification, as long as they are not contradictory to each other.
Although the embodiments of the present disclosure have been illustrated and described above, it shall be understood that the above-mentioned embodiments are illustrative and should not be construed as limitations of the present disclosure. Those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present disclosure.
Claims
1. A chip matrix, comprising:
- a wafer, wherein the wafer has cutting lines that are evenly distributed on the wafer;
- a first silicon oxide layer, wherein the first silicon oxide layer is made of silicon oxide and is formed on an upper surface of the wafer; and
- a transition metal oxide layer, wherein the transition metal oxide layer is made of a transition metal oxide and is formed on an upper surface of the first silicon oxide layer.
2. The chip matrix according to claim 1, wherein the transition metal oxide layer consists of a plurality of transition metal oxide spots that are unconnected to each other;
- the plurality of transition metal oxide spots has a thickness of 10 nm to 20 nm; and the first silicon oxide layer has a thickness of 80 nm to 100 nm, preferably 90 nm;
- the plurality of transition metal oxide spots is connected with amino groups; and
- optionally, the first silicon oxide layer located among the plurality of transition metal oxide spots that are unconnected to each other is connected with polyethylene glycol.
3. The chip matrix according to claim 1, further comprising a second silicon oxide layer, wherein
- the transition metal oxide layer is of a continuous layer structure, and the second silicon oxide layer is made of silicon oxide and formed on an upper surface of the transition metal oxide layer as a plurality of wells that are connected to each other; or
- the transition metal oxide layer consists of a plurality of transition metal oxide spots that are unconnected to each other, and the second silicon oxide layer is formed on the upper surface of the first silicon oxide layer located among the plurality of transition metal oxide spots that are unconnected to each other.
4. The chip matrix according to claim 3, wherein
- the wafer is a silicon wafer, the second silicon oxide layer has a thickness ranging from 40 nm to 60 nm, preferably 50 nm, the transition metal oxide layer has a thickness ranging from 5 nm to 15nm, and the first silicon oxide layer has a thickness ranging from 80 nm to 100 nm, preferably 90 nm; or
- the wafer is a quartz wafer, the second silicon oxide layer has a thickness ranging from 100 nm to 200 nm, the transition metal oxide layer has a thickness ranging from 10 nm to 20 nm, and the first silicon oxide layer has a thickness ranging from 80 nm to 100 nm, preferably 90 nm.
5. The chip matrix according to claim 3, wherein,
- when the transition metal oxide layer is of a continuous layer structure, amino groups are connected to the transition metal oxide layer at a bottom of each well of the second silicon oxide layer; or when the transition metal oxide layer consists of a plurality of transition metal oxide spots, amino groups are connected to the plurality of transition metal oxide spots; and
- optionally, the second silicon oxide layer is connected with polyethylene glycol.
6. The chip matrix according to claim 5, wherein the amino groups are connected to at least a part of transition metal oxide molecules in the transition metal oxide layer through chemical bonds;
- optionally, the chemical bonds are formed by the at least part of transition metal oxide molecules and phosphate groups of aminophosphonic acid-based compounds.
7. The chip matrix according to claim 5, wherein the polyethylene glycol is provided by at least one selected from polyethyleneimine-polyethylene glycol and a silane coupling agent containing polyethylene glycol;
- when the polyethylene glycol is provided by the polyethyleneimine-polyethylene glycol, and the polyethyleneimine-polyethylene glycol is electrostatically adsorbed on a surface of the first silicon oxide layer or a surface of the second silicon oxide layer; and
- when the polyethylene glycol is provided by the silane coupling agent containing polyethylene glycol, and the silane coupling agent containing polyethylene glycol is connected to the first silicon oxide layer or the second silicon oxide layer through a —Si—O—Si— chain.
8. The chip matrix according to claim 1, wherein the transition metal oxide comprises at least one of titanium dioxide, zirconium dioxide, tantalum pentoxide, niobium hexaoxide, or hafnium dioxide.
9. A sequencing chip, comprising a chip body, wherein the chip body comprises a number of chip units obtained by cutting the chip matrix according to claim 1 along the cutting lines of the wafer.
10. The sequencing chip according to claim 9, wherein the sequencing chip is reusable.
11. A method for manufacturing the chip matrix according to claim 1, the method comprising: performing surface modification on the wafer,
- wherein the surface modification comprises: treating a surface of the wafer with a transition metal oxide to form the transition metal oxide layer, wherein the transition metal oxide layer is formed on an upper surface of the first silicon oxide layer, the first silicon oxide layer is provided on the upper surface of the wafer, and the silicon oxide layer is made of silicon oxide, and the wafer has cutting lines evenly distributed on the wafer.
12. The method according to claim 11, wherein the first silicon oxide layer is formed in advance on the upper surface of the wafer by low-temperature plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, or atomic layer deposition.
13. The method according to claim 11, wherein the surface modification of the wafer is performed by thin film deposition, photolithography, or etching to form the transition metal oxide layer in form of a continuous layer or in form of arrayed spots.
14. The method according to claim 13, wherein, for the transition metal oxide layer in form of a continuous layer, the method further comprises forming, with silicon oxide, a second silicon oxide layer in form of continuous wells on an upper surface of the transition metal oxide layer;
- for the transition metal oxide layer in form of arrayed spots, the method further comprises depositing silicon oxide between the spots of the transition metal oxide layer to form a second silicon oxide layer.
15. The method according to claim 11, further comprising performing amination treatment on the transition metal oxide,
- wherein the amination treatment is performed by reacting transition metal oxide with an aminophosphonic acid-based compound.
16. The method according to claim 11, further comprising performing a surface modification on the first silicon oxide layer or the second silicon oxide layer to introduce polyethylene glycol on the first silicon oxide layer or the second silicon oxide layer; and
- the polyethylene glycol is provided by at least one of polyethyleneimine-polyethylene glycol or a silane coupling agent containing polyethylene glycol;
- optionally, when the polyethylene glycol is provided by polyethyleneimine-polyethylene glycol, the surface modification is performed by electrostatic adsorption of polyethyleneimine-polyethylene glycol on a surface of the first silicon oxide layer or a surface of the second silicon oxide layer;
- optionally, when the polyethylene glycol is provided by the silane coupling agent containing polyethylene glycol, the surface modification is performed by condensation reaction of the silane coupling agent containing polyethylene glycol with hydroxyl groups of the first silicon oxide layer or the second silicon oxide layer, wherein the hydroxyl groups are provided by Si—OH generated after the first silicon oxide layer or the second silicon oxide layer is ionized and adsorbs hydroxide ions in water.
17. A method for manufacturing a sequencing chip, comprising:
- assembling a chip unit, wherein the chip unit is obtained by cutting a chip matrix along cutting lines of a wafer layer of the chip matrix, the chip matrix is as defined in claim 1.
18. The method according to claim 17, wherein said assembling comprises placing the chip unit in a supporting frame including a liquid inlet and outlet, and bonding the chip unit to the supporting frame with a glue or adhesive, a fluid channel being formed between the frame and the chip unit.
19. The method according to claim 18, wherein, when the wafer is a silicon wafer, said assembling comprises: bonding the chip unit to the support frame with an upper surface of the chip unit facing upward, and placing a cover glass on the upper surface of the chip unit to obtain the sequencing chip.
20. The method according to claim 18, wherein, when the wafer is a quartz wafer or a glass wafer, said assembling comprises: bonding the chip unit to the support frame with a lower surface of the chip unit facing upward to obtain the sequencing chip.
21. A sequencing method, comprising performing sequencing using the sequencing chip according to claim 9.
Type: Application
Filed: Jul 15, 2021
Publication Date: Dec 9, 2021
Applicant: BGI SHENZHEN (Shenzhen)
Inventors: Shifeng Li (Shenzhen), Tengyue Li (Shenzhen), Yuan Li (Shenzhen), Zhaohui Wang (Shenzhen), Xueqin Jiang (Shenzhen), Jiacheng Chen (Shenzhen), Aoli Wang (Shenzhen), Fuxing Huang (Shenzhen), Xiaogang Song (Shenzhen), Lingling Peng (Shenzhen), Handong Li (Shenzhen), Wenwei Zhang (Shenzhen)
Application Number: 17/377,114