Charge-sharing digital to analog converter and successive approximation analog to digital converter
In one embodiment, an analog to digital converter includes a comparator having a first input, a second input and an output, the first input being coupled to an analog signal, a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal, and a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second input of the comparator.
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The present invention relates generally to electronics and more particularly to analog and digital signal converters.
BACKGROUND OF THE INVENTIONElectronic components have been developed that convert analog to digital signals and vice versa. These converters are used in applications that receive inputs from analog sensors and/or in cases where digital signals are used to interface with analog components. An analog to digital converter (hereinafter referred to “ADC”), converts an analog voltage to a digital number. A digital to analog converter (hereinafter referred to “DAC”), converts a digital number to an analog equivalent signal.
In certain applications the speed of the signal conversions is controlling. In some of these cases, the converter must be able to keep up with rapidly changing data. In other applications the ability to resolve between two close analog voltages is controlling. The number of bits that make up the digital number as well as the reference voltage used to implement the ADC/DAC determine the resolution of the ADC/DAC. For example, an eight-bit ADC/DAC ranges from 0 to 255, i.e., 256 values. If the highest number, i.e., 255, is scaled to 5 V, i.e., the reference voltage, the resolution of the ADC/DAC is 19.58 mV. That is, the ADC/DAC can only resolve to within 19.58 mV. If, for the same reference voltage, a ten-bit result is generated the resolution is thereby improved to 4.88 mV.
In some other applications the footprint of the converter is the most important factor. In these cases, the objective is to make the size of the ADC or DAC as small as possible within the geometrical constraints of the semiconductor technology being used. For example, the number of capacitors used in an ADC/DAC may result in a large footprint for the ADC/DAC.
Serial charge redistribution digital to analog converters were developed to address some of these shortcomings.
What is needed is an ADC/DAC converter that provides sufficiently fast conversions, with sufficiently fine resolution, a small footprint, and reduces the non-ideal behavior of switches.
SUMMARY OF THE INVENTIONIn one embodiment, an analog to digital converter includes a comparator having a first input, a second input and an output, the first input being coupled to an analog signal, a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal, and a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor mutually exclusively to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second input of the comparator.
In another embodiment, an analog to digital converter includes a first adder configured to generate a sum of a first analog signal and a second analog signal, a second adder configured to generate a sum of a third analog signal and a fourth analog signal, a comparator configured to compare the sum of the first and the second analog signals with the sum of the third and the fourth analog signals, a successive approximation register coupled to the comparator and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the first and the third analog signals in response to the comparison performed by the comparator, and a differential digital to analog converter coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, a third, and a fourth capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first and the third capacitors to the second capacitor, and to couple the first and the third capacitors to the fourth capacitor in a mutually exclusively manner to share charge on the first capacitor and charge on the third capacitor with charges on the second and fourth capacitors and to generate the second analog signal on the second capacitor and the fourth analog signal on the fourth capacitor.
In another embodiment, an analog to digital converter includes a first adder configured to generate a sum of a first analog signal and a second analog signal, a second adder configured to generate a sum of a third analog signal and a fourth analog signal, a comparator configured to compare the sum of the first and the second analog signals and the sum of the third and the fourth analog signals, a successive approximation register coupled to the comparator and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the first and the third analog signals in response to the comparison performed by the comparator, and a differential digital to analog converter coupled to the plurality of control signals, the differential digital to analog converter further comprising a first, a second, a third, and a fourth capacitor and a plurality of switches controlled by the plurality of control signals to toggle selectively between a first sequence and a second sequence, in the first sequence the plurality of switches couple the first and the third capacitors to the second capacitor and couple the first and the third capacitors to the fourth capacitor in a mutually exclusively manner to share charge on the first capacitor and charge on the third capacitor with charges on the second and fourth capacitors and to generate the second analog signal on the second capacitor and the fourth analog signal on the fourth capacitor, in the second sequence the plurality of switches couple the second and the fourth capacitors to the first capacitor and couple the second and the fourth capacitors to the third capacitor in a mutually exclusively manner to share charge on the second capacitor and charge on the fourth capacitor with charges on the first and the third capacitors and to generate the second analog signal on the first capacitor and the fourth analog signal on the third capacitor.
The above described features and advantages, as well as others, will become more readily apparent to those of ordinary skill in the art by reference to the following detailed description and accompanying drawings.
Referring to
Referring to
The circuit 50 is an improvement over the prior art shown in
where n is the number of bits) or discharged from about Vref (actually,
where n is the number of bits) to ground. Therefore, in circuit 50 as soon as charge between one pair of capacitors is shared during a charge sharing cycle, the third capacitor is ready to share its charge during the next charge sharing cycle.
There are four distinct states in the circuit 50. In the first state a first capacitor 64 is charged by coupling it to the high reference voltage 52 by placing the first switch 56 in the on state. In this state, a second switch 58 is in the off state to decouple a second capacitor 66 from the first capacitor 64. In the second state charge between the second capacitor 66 and either the first capacitor 64 or a third capacitor 68 is shared. If the first capacitor 64 is sharing charge with the second capacitor 66, the first switch 56 is in the off state, the second switch 58 is in the on state, and a third switch 60 is in the off state. If the second capacitor 66 is sharing charge with the third capacitor 68, the second switch 58 is in the off state, the third switch 60 is in the on state, and a fourth switch 62 is in the off state. In the third state, the third capacitor 68 is discharged by coupling it to ground 54 by placing the fourth switch 62 in the on state. In this state, the third switch 60 is in the off state to decouple the second capacitor 66 from the third capacitor 68. In the fourth state, the second capacitor 66 is discharged by placing the third switch 60 and the fourth switch 62 in the on state and by decoupling the first capacitor 64 by placing the second switch 58 in the off state. In addition, the fourth state can be implemented with an additional reset switch.
The high reference voltage 52 having an electrical potential with respect to ground 54 provides charge to the capacitor network 64, 66, and 68. The high reference voltage 52 is switched in and out of the capacitor network by the first switch 56. The high reference voltage 52 charges the first capacitor 64. While switch 56 connects the first capacitor 64 to the high reference voltage 52, the second switch 58 is in the open state, uncoupling a second capacitor 66 from the first capacitor 64. That is, the second switch 58 and the first switch 56 are on in a mutually exclusive manner. While the second switch 58 is in the on state, the charge between the first capacitor 64 and the second capacitor 66 is shared. In this state, the second capacitor 66 is decoupled from the third capacitor 68.
Charge sharing between the capacitor pairs, e.g., the first capacitor 64 and the second capacitor 66, is governed by equation (1).
where C1 and C2 are the capacitances of the first capacitor 64, the second capacitor 66, Vinit1 and Vinit2 are the voltages of the first and second capacitors immediately before charge sharing, and Q1,2 is the charge on the first and second capacitors C1 and C2. For C1=C2=C, the charge on the capacitors is shown by equation (2).
The final voltage on the first and second capacitors, is governed by equation (3).
Substituting for Q1,2 in equation 3, VFinal1,2 is calculated based on equation (4).
Therefore, for cases where C1=C2, every time the charge on the first and second capacitors are shared, the post-charge-sharing voltage on both capacitors is an average of Vinit1 and Vinit2. The same holds true for charge sharing between the second and third capacitors 66 and 68.
Referring to
The control sequence circuit 82 is configured to trigger the capture of the next bit available at the input 88 (which is connected to the comparator 12 and represents the output 20 of the comparator 12) after a certain amount of time has expired. In one embodiment, this delay can be accomplished by circuit 82 counting a predetermined number of clock cycles of the timing signal 90, which was generated by the timing circuit 80. In another embodiment, the timing circuit 80 may be a timer, i.e., an RC circuit, which provides a decaying signal to the control sequence circuit 82. In yet another embodiment, a data ready signal 36 can be provided by the comparator 12 to alert the timing circuit 80 that the output 20 of the comparator 12 has valid data. In any of these cases, the control sequence circuit 82 triggers the output register 84 to capture the data at the input 88 only when the data is valid.
The output register 84 provides data lines 95 to a shift register 86. The shift register 86 shifts data in a fashion that is described below and provides control lines 32 to the DAC (not shown). The shift register is also controlled by the control sequence circuit 82 via timing control signal 94.
As already discussed, the DAC 16 shown in
The capacitor and switching network in a SAR DAC, which is shown in
Referring to
However, the right child represents the voltage of its parent divided by two. The child-parent relationship according to
Referring to
The latter difference results in several children being in different locations. These are shown by arrows in
To resolve these differences, a bit mirror imaging method is implemented in the SAR 14, as described below. This method is exemplified in
Referring to
The DAC's second iteration has two phases. The second iteration begins at the reset state, state 0, as indicated by the dotted line in
The third iteration has three phases. It begins at state 0 and follows to state 8 by a pump-up operation, as indicated by the solid line in
The fourth iteration has four phases. It begins at state 0 and follows to state 8 by a pump-up operation, as indicated by the dashed-dotted line in
A fixed number of iterations is necessary to arrive at the closest digital conversion. The number of iterations is the same as the number of bits, i.e., N. In the four-bit example shown in
Given that there are a fixed number of iterations, for any analog input, the binary tree shown in
where, N is the number of ADC bits. In the above four-bit example, the number of cycles is 4+3+2+1+4 which equals 14 cycles. This can be seen in the bottom table of
In one embodiment, the first phase of the second iteration can be eliminated. This reduction is possible because the mirror image of the captured bit from the comparator's output after the first iteration is always equal to the same bit. In the example provided above, after the first iteration, the captured bit from the comparator's output was a zero. Since the mirror image of a single bit is the same as the bit, the second iteration can start from state 8, instead of starting from the reset state (0) and then traversing to state 8. The elimination of the first phase of the iteration saves latency required for one reset connectivity (see
In one implementation, the timing for traversing from one state to another is based on a clock cycle. The clock signal is formed, e.g., in the timing circuit 80 and provided to control sequence circuit 82 on timing signal 90. Alternatively, a timer, e.g. an RC circuit, can be used to trigger the control sequence circuit 82 when it is time to move to the next state. Whether a clock or a timer is used, the period between the timing signals 90 should be sufficient so that the charges on the capacitor network settle during pump-up/down operations.
In one embodiment, the SAR 14 can be implemented such that certain phases of a new iteration may be avoided. In this embodiment, if the mirror image of the appended bits places the DAC at the same state that the DAC already is at the end of a current iteration, phases of a new iteration that place the DAC in the current location can be eliminated. For example, if at the conclusion of iteration n, the mirror image of the appended bits would place the DAC at the same state that the DAC already is, then there is be no need to start the new iteration at the reset state. Instead the SAR 14 can continue to the next bit of the new iteration, skipping some of the pump-up/down operations. This was seen in the secondary example provided above where the analog input was 0.76 V. At the conclusion of the second iteration, the DAC was state 12 (0.75 V). The DAC could advantageously proceed to state 14 without traversing back up to the reset state and then to state 8, 12, and then to state 14. This elimination can result in a saving of 3 cycles (to reset, to state 8, and to state 12). This elimination occurs because the appended bits of the comparator output at the end of the second iteration were 11, which results in a mirror image of 11, which would place the DAC at the same location on the tree, i.e., state 12. This implementation can also reduce power required by the ADC.
In another embodiment, a differential scheme is provided to enhance the ADC's operation. Differential signals improve noise immunity of the DAC. In applications where the DAC's reference voltages are relatively low in amplitude, ground jitter can be disruptive. The noise immunity can be improved by implementing a differential DAC which uses a high and a low reference voltage. A differential DAC 100 is shown in
Referring to
In one embodiment, a dynamic element matching scheme is used to reduce the mismatch between the capacitors, and thereby improve the accuracy of the ADC/DAC. To achieve improved accuracy the capacitors need to be matched. The capacitors may be physically matched; however, physical matching requires larger footprints for the capacitors. In some applications increasing the size of the capacitors may be prohibitive. Alternatively, the capacitors can be dynamically matched in applications where the number of cycles required to arrive at a digital value for an analog input is not critical. Referring to
While the invention has been illustrated and described in detail in the drawings and foregoing description, the same should be considered as illustrative and not restrictive in character. It is understood that only the preferred embodiments have been presented and that all changes, modifications and further applications that come within the spirit of the invention are desired to be protected.
Claims
1. An analog to digital converter comprising:
- a comparator having a first input, a second input and an output, the first input being coupled to an analog signal;
- a successive approximation register having a serial input coupled to the output of the comparator, and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the analog signal; and
- a digital to analog converter having an input coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, and a third capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first capacitor to the second capacitor and the third capacitor to the second capacitor in a mutually exclusively manner to share charge on the first capacitor and charge on the third capacitor with charge on the second capacitor and to generate an analog signal on the second capacitor, the second capacitor being coupled to the second input of the comparator.
2. The analog to digital converter of claim 1, wherein the first capacitor is selectively coupled to a high reference voltage by one of the plurality of switches in response to one control signal of the plurality of control signals.
3. The analog to digital converter of claim 2, wherein the third capacitor is selectively coupled to an low reference voltage by one of the plurality of switches in response to one control signal of the plurality of control signals.
4. The analog to digital converter of claim 3, wherein the successive approximation register generates a combination of the plurality of control signals that operates the plurality of switches to place the digital to analog converter in a pump-up state, in the pump-up state the first capacitor is decoupled from the high reference voltage and afterwards coupled to the second capacitor and the third capacitor is decoupled from the second capacitor and coupled to the low reference voltage.
5. The analog to digital converter of claim 3, wherein the successive approximation register generates a combination of the plurality of control signals that operates the plurality of switches to place the digital to analog converter in a pump-down state, in the pump-down state the first capacitor is decoupled from the second capacitor and afterwards coupled to the high reference voltage and the third capacitor is decoupled from the low reference voltage and coupled to the second capacitor.
6. The analog to digital converter of claim 4, wherein the successive approximation register generates a combination of the plurality of control signals to place the digital to analog converter in a reset state, in the reset state the second capacitor is decoupled from the first and third capacitors, the second and third capacitors are coupled to the low reference voltage, and the first capacitor is coupled to the high reference voltage.
7. The analog to digital converter of claim 6, wherein the successive approximation register generates a combination of the plurality of control signals to place the digital to analog converter in the pump-up state after the reset state.
8. The analog to digital converter of claim 7, the successive approximation register further comprising an output register, the output register being coupled to the output of the comparator to append the output of the comparator N times serially to form the N-bit digital value, the register placing the digital to analog converter in the reset state after each time the output of the comparator is appended and after each reset state the register generates the plurality of control signals to form a pump sequence corresponding to a mirror image of the appended bits.
9. The analog to digital converter of claim 8, wherein for each bit of the pump sequence the digital to analog converter is placed in the pump-down state in response to the bit being zero, and the digital to analog converter is placed in the pump-up state in response to the bit being one.
10. The analog to digital converter of claim 9, wherein each bit of the pump sequence is presented to the digital to analog converter with reference to a predefined time interval.
11. The analog to digital converter of claim 10, wherein the register outputs the N-bit digital value at the first output of the register with a latency of N + ∑ n = 1 N n predefined time intervals.
12. The analog to digital converter of claim 11, wherein the register outputs the N-bit digital value at the first output of the register with a latency of ( N - 1 ) + ∑ n = 2 N n predefined time intervals.
13. The analog to digital converter of claim 10, the successive approximation register further comprising a clock signal generator that provides a clock period corresponding to the predefined time interval.
14. The analog to digital converter of claim 10, the successive approximation register further comprising a timer that provides a timeout period corresponding to the predefined time interval.
15. The analog to digital converter of claim 14, the comparator further comprising a third input coupled to the successive approximation register and configured to provide a trigger signal to the comparator the comparator comparing the first and the second inputs in reference to one state of the trigger signal and latching the output of the comparator in response to a predetermined amount of time after the one state of the trigger signal.
16. The analog to digital converter of claim 15, wherein the comparator further comprising a second output coupled to the successive approximation register and configured to provide a ready signal to the successive approximation register to indicate that the output of the comparator is valid.
17. An analog to digital converter comprising:
- a first adder configured to generate a sum of a first analog signal and a second analog signal;
- a second adder configured to generate a sum of a third analog signal and a fourth analog signal;
- a comparator configured to compare the sum of the first and the second analog signals with the sum of the third and the fourth analog signals;
- a successive approximation register coupled to the comparator and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the first and the third analog signals in response to the comparison performed by the comparator; and
- a differential digital to analog converter coupled to the plurality of control signals, the digital to analog converter further comprising a first, a second, a third, and a fourth capacitor and a plurality of switches controlled by the plurality of control signals and being configured to couple the first and the third capacitors to the second capacitor, and to couple the first and the third capacitors to the fourth capacitor in a mutually exclusively manner to share charge on the first capacitor and charge on the third capacitor with charges on the second and fourth capacitors and to generate the second analog signal on the second capacitor and the fourth analog signal on the fourth capacitor.
18. An analog to digital converter comprising:
- a first adder configured to generate a sum of a first analog signal and a second analog signal;
- a second adder configured to generate a sum of a third analog signal and a fourth analog signal;
- a comparator configured to compare the sum of the first and the second analog signals and the sum of the third and the fourth analog signals;
- a successive approximation register coupled to the comparator and being configured to generate a plurality of control signals and an N-bit digital value corresponding to the first and the third analog signals in response to the comparison performed by the comparator; and
- a differential digital to analog converter coupled to the plurality of control signals, the differential digital to analog converter further comprising a first, a second, a third, and a fourth capacitor and a plurality of switches controlled by the plurality of control signals to toggle selectively between a first sequence and a second sequence, in the first sequence the plurality of switches couple the first and the third capacitors to the second capacitor and couple the first and the third capacitors to the fourth capacitor in a mutually exclusively manner to share charge on the first capacitor and charge on the third capacitor with charges on the second and fourth capacitors and to generate the second analog signal on the second capacitor and the fourth analog signal on the fourth capacitor, in the second sequence the plurality of switches couple the second and the fourth capacitors to the first capacitor and couple the second and the fourth capacitors to the third capacitor in a mutually exclusively manner to share charge on the second capacitor and charge on the fourth capacitor with charges on the first and the third capacitors and to generate the second analog signal on the first capacitor and the fourth analog signal on the third capacitor.
19. The analog to digital converter of claim 18, further comprising:
- a memory device for storing the N-bit digital value as a first digital value corresponding to the first sequence and for storing the N-bit digital value as a second digital value corresponding to the second sequence.
20. The analog to digital converter of claim 19, further comprising:
- a processor configured to average the first digital value and the second digital value to produce an N-bit digital output corresponding to the first and the third analog inputs.
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Type: Grant
Filed: Sep 28, 2009
Date of Patent: Mar 29, 2011
Assignee: Robert Bosch GmbH (Stuttgart)
Inventors: Clemenz Portmann (Mountain View, CA), Christoph Lang (Cupertino, CA)
Primary Examiner: Peguy JeanPierre
Attorney: Maginot, Moore & Beck
Application Number: 12/568,172
International Classification: H03M 1/34 (20060101);