Semiconductor memory device including laminated gate having electric charge accumulating layer and control gate and method of manufacturing the same
A semiconductor memory device includes a first active region, a second active region, an element isolation region, memory cell transistors. Each of memory cell transistors includes a laminated gate and a first impurity diffusion layer functioning as a source and a drain. The laminated gate includes a first insulating film, a second insulating film, and a control gate electrode. The second insulating film is commonly connected between the plurality of memory cell transistors to step over the element isolation region and is in contact with an upper surface of the element isolation region. An upper surface of the element isolation region is higher than a bottom surface of the first insulating film and is located under the upper surface of the first insulating film.
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This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-141477, filed May 29, 2008, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. For example, the present invention relates to a structure of an element isolation region in a NAND flash memory having a MONOS structure.
2. Description of the Related Art
As a structure of a nonvolatile memory cell transistor in a semiconductor memory device, a conventional MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure is known. The MONOS structure has a structure which has an electric charge accumulating layer (for example, insulating film) formed on a semiconductor substrate through a gate insulating film, an insulating film (to be referred to as a block layer hereinafter) formed on the electric charge accumulating layer and having a dielectric constant higher than that of the electric charge accumulating layer, and a control gate electrode formed on the block layer. This is described on, for example, Pages 110 to 111 in “Self Aligned Trap-Shallow Trench Isolation Scheme For the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory”, by Jae Sung Sim, NVSMW, August 2007.
A semiconductor memory device has an element isolation region which electrically isolates an active region in which a nonvolatile memory cell transistor having a MONOS structure is arranged. An upper surface of the element isolation region is formed at a level higher than that of an upper surface of an electric charge accumulating layer formed on the active region to form a step on an upper surface of a block film formed on the active region and the element isolation region. For this reason, a distance from the upper surface of the control gate to the block layer on the active region is longer than a distance from the upper surface of the control gate on the element isolation region to the block layer. In this state, when a voltage is applied to the control gate, a voltage is not transmitted to the electric charge accumulating layer formed on the active region sufficiently. A higher voltage must be applied to control gate in the conventional structure, for example, to achieve 4 values (2 bits/cell) per cell.
BRIEF SUMMARY OF THE INVENTIONA semiconductor memory device according to an aspect of the present invention includes a first active region and a second active region formed in a semiconductor substrate, respectively;
an element isolation region which is formed in the semiconductor substrate and which isolates the first active region and the second active region from each other; and
memory cell transistors which are formed on the first active region and the second active region, respectively and each of which includes a laminated gate and a first impurity diffusion layer functioning as a source and a drain,
the laminated gate including a first insulating film which is formed on the semiconductor substrate and which accumulates electric charges, a second insulating film formed on the first insulating film by using a material having a dielectric constant higher than that of the first insulating film, and a control gate electrode formed on the second insulating film,
the second insulating film being commonly connected between said plurality of memory cell transistors to step over the element isolation region and being in contact with an upper surface of the element isolation region, and
an upper surface of the element isolation region being higher than a bottom surface of the first insulating film and being located under the upper surface of the first insulating film.
A semiconductor memory device manufacturing method according to an aspect of the present invention includes forming a first insulating film which accumulates electric charges on a semiconductor substrate through a gate insulating film;
forming a trench which penetrates partial regions of the gate insulating film and the first insulating film and which has a bottom portion which reaches an inside of the semiconductor substrate;
forming a second insulating film on the first insulating film and in the trench to bury the trench with the second insulating film;
etching the second insulating film such that a position of an upper surface of the second insulating film is lower than an upper surface of the first insulating film to leave the second insulating film in the trench;
forming block layers on the first and second insulating films; and
forming a control gate on the block layer.
Embodiments of the present invention will be described below with reference to the accompanying drawings. In this explanation, common reference numerals denote common parts over all the drawings.
First EmbodimentA semiconductor memory device according to a first embodiment of the present invention and a method of manufacturing the same will be described below with reference to
As shown in
As shown in
Control gate electrodes of the memory cell transistors MT on the same row are commonly connected to any one of word lines WL0 to WL15. Gate electrodes of the selection transistors ST1 and ST2 of the memory cells on the same row are commonly connected to select gate lines SGD and SGS, respectively. For descriptive convenience, when the word lines WL0 to WL15 are not discriminated from each other in the following description, the word lines WL0 to WL15 may be simply called word lines WL. Drains of the selection transistors ST1 on the same column in the memory cell array 1 are commonly connected to any one of bit lines BL0 to BLn (n is a natural number). When the bit lines BL0 to BLn are not discriminated from each other, the bit lines BL0 to BLn are referred to as bit lines BL. The sources of the selection transistors ST2 are commonly connected to a source line SL. Both the selection transistors ST1 and ST2 are not always required. Provided the NAND cell 5 can be selected, only one of the selection transistors ST1 and ST2 may be arranged.
The row decoder 3 selects a row direction of the memory cell array 1. More specifically, the row decoder 3 selects the word line WL and applies a voltage to the selected word line WL.
The column decoder 4 selects a column direction of the memory cell array 1. More specifically, the column decoder 4 selects the bit line BL.
The voltage generating circuit 2 generates a voltage and supplies the generated voltage to the row decoder 3.
Each of the voltage generating circuit 2, the row decoder 3, and the column decoder 4 include a low-voltage MOS transistor using, for example, a voltage VDD (for example, 1.5 V) as a power supply voltage and a high-voltage MOS transistor using, for example, a voltage VPP (for example, 20 V) higher than the power supply voltage of the low-voltage MOS transistor as a power supply voltage. For descriptive convenience, in the following description, only a p-channel MOS transistor is described as the low-voltage MOS transistor, and only an n-channel MOS transistor is described as the high-voltage MOS transistor. These transistors will be called peripheral transistors PT1 and PT2, respectively.
A plan view of the memory cell array 1 having the above configuration will be described below by using
As shown in
An impurity diffusion layer formed in the element region AA between the select gate lines SGD adjacent to each other in the first direction functions as a drain region of the selection transistor ST1. A contact plug CP1 is formed on the drain region. The contact plug CP1 is connected to the strip-like bit lines BL (not shown) arranged along the first direction. The impurity diffusion layer formed in the element region AA between the select gate lines SGS adjacent to each other in the first direction functions as a source region of the selection transistor ST2. On the source region, a contact plug CP2 is formed. The contact plug CP2 is connected to a source line SL (not shown).
A sectional configuration of the memory cell array 1 having the above configuration will be described below with reference to
As shown in
The gate electrode of the memory cell transistor MT has a laminated structure. More specifically, the gate electrode includes the insulating film 15 formed on the gate insulating film 14, an insulating film 16 formed on the insulating film 15, and a polycrystalline silicon layer 17 formed on the insulating film 16. The insulating film 15 functions as an electric charge accumulating layer which accumulates electric charges. The insulating film 16 functions as a block layer to confine electric charges in the insulating film 15 and is formed by using a material having a dielectric constant higher than that of the material used in the insulating film 15. The polycrystalline silicon layer 17 functions as a control gate (word line WL). In the following description, the insulating films 15 and 16 and the polycrystalline silicon layer 17 in the memory cell transistor MT may be called the electric charge accumulating layer 15, the block layer 16, and the control gate 17, respectively. An upper part or the whole of the polycrystalline silicon layer 17 may be silicified to make the resistance of the word line low. The electric charge accumulating layers 15 are separated in units of memory cell transistors MT, and the block layer 16 and the control gate 17 are commonly connected between the memory cell transistors MT adjacent in a word line direction. More specifically, the block layers 16 of the memory cell transistors MT are commonly connected between the adjacent active regions AA to step over the adjacent element isolation region 32 in a direction along the word lines.
The electric charge accumulating layer 15 is formed to have an upper surface which has a level equal to that of the upper surface of the element isolation region 32. A surface with which the bottom surface of the block layer 16 on the element isolation region 32 and the upper surface of the element isolation region 32 are in contact has a level which is equal to that of the upper surface of the electric charge accumulating layer 15 on the active region AA, i.e., the surface and the upper surface of the electric charge accumulating layer 15 are on the same plane.
The gate electrodes of the selection transistors ST1 and ST2 include the polycrystalline silicon layers 20. Hereinafter, the polycrystalline silicon layer 20 may be called a gate electrode 20. An upper part or the whole of the polycrystalline silicon layer 20 may be silicified to make the resistance of the gate electrode low. In the selection transistors ST1 and ST2, the gate electrodes 20 which are adjacent to each other in the second direction are commonly connected to each other. The gate electrodes 20 function as the select gate lines SGS and SGD.
An n+-type impurity diffusion layer 13 is formed in the surface of the p-type semiconductor substrate 10 located between the gate electrodes. The n+-type impurity diffusion layer 13 is shared by adjacent transistors, and functions as a source (S) or a drain (D). A region (immediately under the gate electrode) between the source and the drain which are adjacent to each other functions as a channel region serving as an electron moving region. The gate electrode, the n+-type impurity diffusion layer 13, and the channel region constitute the memory cell transistor MT and the selection transistors ST1 and ST2.
Furthermore, an interlayer insulating film 21 is formed on the p-type semiconductor substrate 10 to cover the memory cell transistor MT and the selection transistors ST1 and ST2. In the interlayer insulating film 21, the contact plug CP2 which reaches the impurity diffusion layer (source) 13 of the selection transistor ST2 on the source side is formed. On the surface of the interlayer insulating film 21, a metal wiring layer 22 connected to the contact plug CP2 is formed. The metal wiring layer 22 functions as a part of the source line SL. In the interlayer insulating film 21, a contact plug CP3 which reaches the impurity diffusion layer (drain) 13 of the selection transistor ST on the drain side is formed. On the surface of the interlayer insulating film 21, a metal wiring layer 23 connected to the contact plug CP3 is formed.
On the interlayer insulating film 21, an interlayer insulating film 24 is formed by using, for example SiO2 as a material. An insulating film 25 is formed on the interlayer insulating film 24. The insulating film 25 is formed by using a material, for example, SiN having a dielectric constant higher than that of the interlayer insulating film 24. A metal wiring layer 26 is formed on the insulating film 25. The metal wiring layer 26 functions as the bit line BL. In the insulating film 25 and the interlayer insulating film 24, a contact plug CP4 which is in contact with the metal wiring layer 26 on the upper surface and which is in contact with the metal wiring layer 23 on the bottom surface is formed. The upper surface of the contact plug CP4 is higher than the upper surface of the insulating film 25. More specifically, an upper part of the contact plug CP4 is formed to be buried in the metal wiring layer 26. The contact plug CP3, the metal wiring layer 23, and the contact plug CP4 function as contact plugs CP1 in
A structure of peripheral transistors PT1 and PT2 included in the voltage generating circuit 2, the row decoder 3, and the column decoder 4 will be described below with reference to
As shown in
The peripheral transistor PT1 will be described first. As shown in
The peripheral transistor PT2 will be described next. As shown in
On the p-type semiconductor substrate 10, the interlayer insulating films 21 and 24 are formed to cover the peripheral transistors PT1 and PT2. In the interlayer insulating films 21 and 24, a contact plug and a metal wiring layer (not shown) are formed. Voltages are applied to the peripheral transistors PT1 and PT2 through the contact plug and the metal wiring layer.
A method of manufacturing the memory cell transistor MT and the peripheral transistors PT1 and PT2 will be described below with reference to
As shown in
The photoresist film is removed, and another photoresist film (not shown) is formed in a region except for a prediction region for forming the memory cell transistor MT shown in
As shown in
On the p-type well region 12, the n-type well region 36, and the gate insulating film 44 shown in
When the gate insulating film 14 including the same material as that of the gate insulating film 44 is formed, a boundary between the gate insulating film 44 and the gate insulating film 14 shown in
Furthermore, on the gate insulating film 14, the insulating film 15 serving as an electric charge accumulating layer is formed to have a thickness of, for example, 3 [nm] to 10 [nm]. The insulating film 15 has, for example, an SiN single film, an HfAlO single film, or a laminated structure containing any one of SiN, HfAlO, and Al2O3. Furthermore, on the insulating film 15, a buffer silicon oxide film 45 having a thickness of about 10 [nm] is formed by a CVD (Chemical Vapor Deposition) method. Subsequently, an SiN film 46 having a film thickness of, for example, about 50 [nm] is formed on the buffer silicon oxide film 45. Furthermore, for example, a BSG film 47 which functions as a mask material in formation of the element isolation region 32 is formed on the SiN film 46.
Furthermore, on the BSG film 47, in a region except for a prediction region for forming the element isolation region 32, a photoresist film (not shown) is formed by the photolithography step. The BSG film 47 is etched by using anisotropic etching in a region in which the photoresist film is not formed, i.e., the photoresist film is open. Subsequently, the SiN film 46, the buffer silicon oxide film 45, the insulating film 15, and the gate insulating film 14 are etched by anisotropic etching. By the above steps, as shown in
As shown in
As shown in
Thereafter, as shown in
As shown in
A photoresist film (not shown) is formed by the photolithography step on the block layer 16 in a prediction region for forming the memory cell transistor MT shown in
As shown in
By the photolithography step and the dry etching step, the SiN film 53, the polycrystalline silicon layer 49, and the insulating film layers 15 and 16 are patterned into patterns of gate electrodes to obtain configurations shown in
In the prediction regions for forming the peripheral transistors PT1 and PT2, the gate electrode 43 formed by the polycrystalline silicon layer 49 is completed. The gate electrodes of the selection transistors ST1 and ST2 are formed to have the same configurations as those of the gate electrodes of the peripheral transistors PT1 and PT2. On the control gate 17 and the gate electrode 43, the mask material is left. The control gate 17 may have a laminated structure containing, for example, TaN, WN, and W. The control gates 43 of the peripheral transistors PT1 and PT2 may also have laminated structures containing, for example, polycrystalline silicon, TaN, WN, and W.
As shown in
Thereafter, by using the photolithography step and the ion injection step, an impurity is injected into the well regions 12, 36, and 37 to form the impurity diffusion layers 13, 39, and 41 functioning as the source and the drain. The ion injection step is performed by using an injection amount, ion species, and an acceleration voltage which are appropriate for the transistors. After the impurity is injected, annealing is performed at, for example, a temperature of 950° C. to activate the injected impurity. As a result of the ion injection and the annealing, the sources and drains 13, 39, and 41 of the memory cell transistor MT and the peripheral transistors PT1 and PT2 are completed.
Furthermore, the SiN film 53 on the gate electrode is removed by dry etching or like. Subsequently, the surfaces of the gate electrodes 17 and 43 are silicified. For example, an Ni layer is formed on the gate electrodes 17 and 43 and annealed to form NiSi on the upper surfaces of the gate electrodes 17 and 43.
On the p-type semiconductor substrate 10, the interlayer insulating film 21 is formed to cover the memory cell transistor MT and the peripheral transistors PT1 and PT2. On the interlayer insulating film 21, the contact plugs CP1 and CP2 having the same characteristics as those of a high-melting point metal such as tungsten or molybdenum or a metal wiring layer using, for example, aluminum are formed. In this state, the memory cell transistor MT and the peripheral transistors PT1 and PT2 shown in
Voltages are applied to the memory cell transistors MT and the peripheral transistors PT1 and PT2 through the contact plugs and the metal wiring layer.
As described above, according to a semiconductor memory device according to the first embodiment and a method of manufacturing the semiconductor memory device, operational reliability can be improved. This effect will be described below in detail in comparison with a conventional semiconductor memory device.
<Conventional Configuration>
<<Problem 1>>
More specifically, electrons captured in the electric charge accumulating layer 15 by a data programming operation move in the electric charge accumulating layer. That is, in the electric charge accumulating layer 15, electrons injected in a region on the active region AA moves to a region on the element isolation region 32. This is because an electric field is generated by the Frenkel Poll phenomenon. As a result, the number of electrons in the region on the active region AA decreases, and a threshold value of the memory cell transistor MT decreases. This may cause an erroneous operation of the memory cell transistor MT.
In particular, when the area of the electric charge accumulating layer 15 decreases with shrinking of the memory cell transistor MT, the above phenomenon becomes conspicuous. For this reason, this problem hinders miniaturization of a NAND flash memory and a reduction in cost.
COMPARATIVE EXAMPLEAs a countermeasure against this problem, a structure shown in
As shown in the drawing, a configuration in
<<Problem 2>>
However, even though the above configuration is used, the following new problem is also posed. This problem will be described below with reference to
As shown in the drawing, when a voltage is applied to the control gate 17, an electric flux line is concentrated on the electric charge accumulating layer 15. More specifically, the electric flux line generated from the control gate 17 is directed to the electric charge accumulating layer 15. When electrons are injected into the electric charge accumulating layer 15, the electric flux line generated from the well region 12 is also directed to the electric charge accumulating layer 15.
However, when shrinking is advanced (for example, a half pitch of the memory cell transistor MT (width of the active region AA in a direction along the word lines) is 40 [nm] or less), the electric flux line generated from the electric charge accumulating layer of the adjacent memory cell transistor MT is directed to a channel region in the semiconductor substrate 10 of an adjacent cell (indicated by an arrow A1 in
This is because the level difference between the upper surface of the electric charge accumulating layer 15 and the element isolation region 32 is a width S1 larger than a width S2 from the upper surface of the electric charge accumulating layer 15 and the upper surface of the block layer 16. Since a parasitic capacitance between the memory cell transistors MT is reduced, a relative dielectric constant of a material used in the silicon oxide film 31 is lower than that of the block layer 16. If the widths S1 and S2 are equal to each other, when the width S1 is converted into a dielectric constant of the block layer, the width S1 is four times the width S2. More specifically, an electric flux line from the block layer 16 is not easily transmitted to the electric charge accumulating layer 15 of the memory cell transistor MT. As a result, the electric charge accumulating layer 15 is easily influenced by the electric flux line from the electric charge accumulating layer of the adjacent memory cell transistor MT.
With the configuration shown in
As a result, an electrostatic potential of the channel region of the memory cell transistor MT fluctuates depending on the amount of electrons injected into the electric charge accumulating layer 15. This disadvantageously causes a fluctuation in threshold value of the memory cell transistor MT.
When the above problem is posed, the range of the threshold value distribution of the memory cell transistors MT is widened throughout the whole memory chip. For this reason, in order to reduce the threshold value distribution, a read operation and a rewrite operation must be repeated. As a result, a write operation requires a long period of time. Furthermore, when a fluctuation range in threshold value of the memory cell transistor MT is large, even the threshold value cannot be easily matched with a desired range.
This behavior is indicated by an arrow A2 in
When the electric field intensity fluctuates, a high voltage is disadvantageously required to program data. This is a conspicuous problem in a multi-valued NAND flash memory in which each of the memory cell transistors MT holds data of two or more bits.
This EmbodimentHowever, in a NAND flash memory according to the embodiment, the above problems can be solved, and the operational reliability of the NAND flash memory can be improved. This will be described below in detail.
<<Effect 1>>
As shown in
<<Effect 2>>
With the configuration according to the first embodiment, a fluctuation in electric field distribution of the electric charge accumulating layer 15 when a voltage is applied to the control gate can be suppressed. More specifically, the Problem 2 can be solved. More specifically, as shown in
This is because, in the configuration according to the first embodiment, the upper surface of the element isolation region 32 is located on the same plane as that of the upper surface of the electric charge accumulating layer 15.
With this configuration, since a dielectric constant of the block layer 16 is higher than that of the silicon oxide film 31, an electric flux line generated from the control gate 17 is easily concentrated on the electric charge accumulating layer 15. Consequently, for example, in a write operation, an electrostatic potential in a channel region of the memory cell transistor MT is not easily influenced by written data of an adjacent memory cell transistor MT, and a range of a threshold value distribution in the memory chip can be narrowed.
As a result, interference between adjacent memory cell transistors MT can be suppressed, a fluctuation in threshold value of the memory cell transistors MT in a whole memory chip can be suppressed. Furthermore, in a write operation and an erase operation, an electric field of the gate insulating film 14 located at a boundary between the element isolation region 32 and the active region AA can be suppressed from decreasing. For this reason, write and erase operations can be executed with a lower voltage.
A semiconductor memory device according to a second embodiment of the present invention and a method of manufacturing the semiconductor memory device will be described below. The semiconductor memory device according to the embodiment is obtained by lowering the upper surface of the element isolation region 32 in the first embodiment.
As shown in
The configuration except for the configuration described above is the same as that of the semiconductor memory device according to the first embodiment. Since the configuration of the peripheral transistor PT2 shown in
A method of manufacturing a semiconductor memory device according to the embodiment will be described below with reference to
At this time, in the peripheral transistor PT2 shown in
In
As described above, also in the semiconductor memory device according to the second embodiment and the method of manufacturing the semiconductor memory device, the same effect as that in the first embodiment is obtained.
More specifically, even though the upper surface of the element isolation region 32 is removed to a position which is lower than the upper surface of the electric charge accumulating layer 15 formed on the active region AA and higher than the lower surface of the electric charge accumulating layer 15, the same effect as described above is obtained. More specifically, a shift of a threshold value caused by an electric flux line generated from an adjacent memory cell transistor MT can be prevented. As a result, a high-reliable semiconductor memory device can be realized. This is because, when a voltage is applied to the control gate 17, an electric distance from the control gate 17 to the electric charge accumulating layer 15 in the selection memory cell transistor MT is shorter than a distance from the control gate 17 to the element isolation region 32. For this reason, the voltage applied to the control gate 17 is sufficiently transmitted to the memory cell transistor MT. As a result, as shown in
The position of the upper surface of the element isolation region 32 means the upper surface of the element isolation region 32 at a point at which the element isolation region 32 is in contact with a side surface of the electric charge accumulating layer 15. When the position of the upper surface of the element isolation region 32 at the contact point of the electric charge accumulating layer 15 is lower than the upper surface of the electric charge accumulating layer 15, an electric distance from the control gate 17 to the electric charge accumulating layer 15 in the selection memory cell transistor MT is shorter than a distance from the control gate 17 to the element isolation region 32. For this reason, the effect as described above is obtained.
Furthermore,
A semiconductor memory device according to a third embodiment of the present invention and a method of manufacturing the semiconductor memory device will be described below. The semiconductor memory device according to the embodiment is obtained by further lowering the upper surface of the element isolation region 32 in the second embodiment. Sectional views of the memory cell transistor MT and the peripheral transistor PT2 according to the embodiment in a direction of the word lines WL are shown in
As shown in
In a side wall of the active region AA exposed by setting down the upper surface of the element isolation region 32 and an upper surface of the element isolation region 32, for example, a silicon oxide film 52 is formed as an insulating film. The silicon oxide film 52 except for on the side wall of the active region AA, for example, the silicon oxide film 52 on the element isolation region 32 can also be removed. The other configuration is the same as that of the semiconductor memory devices according to the first and second embodiments. Since the configuration of the peripheral transistor PT2 shown in
As a result of the above configuration, the block layer 16, the gate insulating film 14, and the p-type semiconductor substrate 10 are isolated from each other by the silicon oxide film 52. More specifically, in a region in which the block layer 16 steps over the element isolation region 32, the silicon oxide films 52 are formed between the block layer 16 and the gate insulating film 14 and between the block layer 16 and the p-type semiconductor substrate 10.
The method of manufacturing a semiconductor memory device according to the embodiment will be described below with reference to
As a result of the above steps, trenches 51 shown in
At this time, in the peripheral transistor PT2 shown in
The silicon oxide film 52 may be formed on the upper portion of the element isolation region 35. In this case, a breakdown-voltage between the gate electrode 43 and the p-type semiconductor substrate 10 can be effectively improved.
In
As described above, even in the semiconductor memory device according to the third embodiment and the method of manufacturing the semiconductor memory device, the same effects as those in the first and second embodiments are obtained.
In the first to third embodiments, a NAND flash memory is exemplified. However, in the first to third embodiments, it may also be applied to a 3Tr-NAND flash memory obtained by making the number of memory cell transistors in a NAND flash memory one, or a NOR flash memory. It can also be applied to a 2Tr flash memory obtained by excluding the selection transistor ST1 on the drain side in the 3Tr-NAND flash memory, and may also be generally applied to nonvolatile semiconductor memories of a laminated gate structure.
The method of manufacturing a semiconductor memory device is not limited to the steps described above. More specifically, in
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
1. A semiconductor memory device comprising:
- a first active region and a second active region formed in a semiconductor substrate, respectively;
- an element isolation region which is formed in the semiconductor substrate and which isolates the first active region and the second active region from each other; and
- memory cell transistors which are formed on the first active region and the second active region, respectively and each of which includes a laminated gate and a first impurity diffusion layers functioning as a source and a drain,
- the laminated gate including a first insulating film which is formed on the semiconductor substrate and which accumulates electric charges, a second insulating film formed on the first insulating film by using a material having a dielectric constant higher than that of the first insulating film, and a control gate electrode formed on the second insulating film,
- the second insulating film being commonly connected between the memory cell transistors to step over the element isolation region and being in contact with an upper surface of the element isolation region, and
- an upper surface of the element isolation region being higher than a bottom surface of the first insulating film and, a center portion of the upper surface of the element isolation region being level with the upper surface of the first insulating film.
2. The device according to claim 1, wherein the first insulating film is a laminated film including a first gate insulating film formed on the semiconductor substrate and an electric charge accumulating layer formed on the first gate insulating film.
3. The device according to claim 2, wherein the first gate insulating film has any one of a configuration in which SiO2, NH3, and NO nitride films, a configuration in which an SiO2 film, an Si film, and SiO film are sequentially laminated, a configuration in which an SiO2 film, an Si film, and SiO2 film are sequentially laminated, a configuration in which an SiO2 film, an SiN film, and an SiO2 film are sequentially laminated, a configuration in which an SiO2 film, an Si fine-particle film, and an SiO2 film are sequentially laminated, and a configuration in which an SiO2 film, an Al2O3 film, and an SiO2 film are sequentially laminated.
4. The device according to claim 2, further comprising:
- a first MOS transistor including a first gate electrode formed on the semiconductor substrate through the second gate insulating film and a second impurity diffusion layers functioning as a source and a drain and has an impurity concentration profile different from that of the first impurity diffusion layer; and
- a second MOS transistor including a second gate electrode formed on the semiconductor substrate through a third gate insulating film and a third impurity diffusion layers functioning as a source and a drain and has an impurity concentration profile different from those of the first impurity diffusion layer and the second impurity diffusion layer,
- the first gate insulating film, the second gate insulating film, and the third gate insulating film having film thicknesses different from each other.
5. The device according to claim 4, wherein the apex is located to be higher than upper surfaces of the electric charge accumulating layers.
6. The device according to claim 2, wherein an upper surface of the element isolation region has an apex, one end of two sides which share the apex in a direction of the control gate are located to be higher than bottom surfaces of the electric charge accumulating layers formed on the first active region and the second active region and lower than an upper surface of the electric charge accumulating layer.
7. The device according to claim 1, wherein the second insulating film is formed by an Al2O3 single film or an LaAlO single film.
8. The device according to claim 1, wherein a dielectric constant of the element isolation region is lower than that of the first insulating film.
9. The device according to claim 1, wherein the upper surface of the element isolation region is flat.
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Type: Grant
Filed: May 28, 2009
Date of Patent: May 3, 2011
Patent Publication Number: 20090294835
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventor: Takayuki Okamura (Machida)
Primary Examiner: Bradley K Smith
Assistant Examiner: Mohammad T Karimy
Attorney: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
Application Number: 12/473,709
International Classification: H01L 29/792 (20060101);