With Charge Trapping Gate Insulator (e.g., Mnos-memory Transistors) (epo) Patents (Class 257/E29.309)
  • Patent number: 10340393
    Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 10121906
    Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 9806090
    Abstract: A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Thomas Jongwan Kwon, Senaka Kanakamedala, George Matamis
  • Patent number: 9524852
    Abstract: A method for monitoring ion implantation, comprising: a), providing a control piece and forming a mask layer; b), performing ion implantation process to implant a predetermined dose of impurity ions into the control piece, an area on the control piece uncovered by the mask layer being an impurity implantation area and an area on the control piece covered by the mask layer being an impurity non-implantation area; c), peeling off the mask layer from the control piece; d), performing oxidation treatment on the control piece; and e), respectively measuring thicknesses of the oxide layers on the impurity implantation area and the impurity non-implantation area of the control piece, and monitoring the impurity dose of the ion implantation on the basis of a ratio of the thickness of the oxide layer in the impurity implantation area to the thickness of the oxide layer in the impurity non-implantation area.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: December 20, 2016
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Hui Tian
  • Patent number: 9484357
    Abstract: A plurality of blocking dielectric portions can be formed between a memory stack structure and an alternating stack of first material layers and second material layers by selective deposition of a dielectric material layer. The plurality of blocking dielectric portions can be formed after removal of the second material layers selective to the first material layers by depositing a dielectric material on surfaces of the memory stack structure while avoiding deposition on surfaces of the first material layers. A deposition inhibitor material layer or a deposition promoter material layer can be optionally employed. Alternatively, the plurality of blocking dielectric portions can be formed on surfaces of the second material layers while avoiding deposition on surfaces of the first material layers after formation of the memory opening and prior to formation of the memory stack structure. The plurality of blocking dielectric portions are vertically spaced annular structures.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: November 1, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Rahul Sharangpani, Senaka Krishna Kanakamedala, Xiaofeng Liang, George Matamis, Sateesh Koka, Johann Alsmeier
  • Patent number: 9419619
    Abstract: A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Georg Tempel, Rolf-Peter Vollertsen
  • Patent number: 9041090
    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Akira Goda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 9035374
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Patent number: 9023702
    Abstract: A nonvolatile memory device may include a plurality of channel layers protruded substantially perpendicularly over a substrate having a well region, a structure configured to have a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked along each of the plurality of channel layers, a plurality of memory layers interposed respectively between each of the plurality of channel layers and each of the plurality of gate electrodes, a source line formed in the substrate between a plurality of the structures, a plurality of source contact plugs placed between the plurality of structures and connected with the source line, and a well pickup contact plug placed between the plurality of structures and connected with the well region.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: In-Hey Lee
  • Patent number: 9018693
    Abstract: Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. A gate stack overlies the channel, the gate stack comprising a tunneling layer, a trapping layer, a blocking layer, a gate layer; and a deuterated gate cap layer. The gate cap layer has a higher deuterium concentration at an interface with the gate layer than at surface of the gate cap layer distal from the gate layer. In certain embodiments, the channel comprises polysilicon or recrystallized polysilicon. Other embodiments are also described.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: April 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Fredrick Jenne, William Koutny
  • Patent number: 9012976
    Abstract: According to one embodiment, the stacked body includes a plurality of insulating layers and a plurality of conductive layers alternately stacked on the underlying film. The first insulating film is provided in a trench piercing the stacked body in a stacking direction of the stacked body and separating the stacked body into a plurality of resistance element blocks in a first direction on the underlying film. The resistance element blocks include a line portion formed of the conductive layer extending in a second direction crossing the first direction and the stacking direction and a hole formation portion provided to protrude in the first direction from the line portion and including a second insulating film provided in a hole piercing the stacked body in the stacking direction.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyasu Tanaka
  • Patent number: 9012978
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
  • Patent number: 9012333
    Abstract: A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: April 21, 2015
    Assignee: Spansion LLC
    Inventors: Yi Ma, Shenqing Fang, Robert Ogle
  • Patent number: 9012320
    Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Kil-Su Jeong, Hansoo Kim, Youngwoo Park
  • Patent number: 9006799
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 14, 2015
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 9000510
    Abstract: A nonvolatile memory device includes: a channel layer extending in a vertical direction from a substrate; a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines; and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Young-Ok Hong
  • Patent number: 9000509
    Abstract: A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalls of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: April 7, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Hong Lee, Kwon Hong, Dae-Gyu Shin
  • Patent number: 9000511
    Abstract: A non-volatile memory device includes a substrate having an active region defined by a device isolation region that has a trench and an air gap, a device isolation pattern positioned at a lower portion of the trench, a memory cell layer including a tunnel insulation layer, a trap insulation layer and a blocking insulation layer that are sequentially stacked on the active region and one of which extends from the active region toward the device isolation region encloses top of the air gap whose bottom is defined by a layer other than that of the top, and a control gate electrode positioned on the cell structure. The one of the insulation layer extending includes a recess at a region corresponding to the center of the air gap.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Chang, Young-Woo Park
  • Patent number: 8994087
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masumi Saitoh, Toshinori Numata, Kiwamu Sakuma, Haruka Kusai
  • Patent number: 8994006
    Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Robert H. Dennard, Hemanth Jagannathan, Ali Khakifirooz, Tak H. Ning, Ghavam G. Shahidi
  • Patent number: 8994035
    Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 8994094
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked body, first and second semiconductor pillars, a connecting portion, a first memory film, and a dividing portion. The stacked bodies include a plurality of electrode films stacked along a first axis and as interelectrode insulating film provided between the electrode films. The first and second semiconductor pillars penetrate through the first and second stacked bodies along the first axis, respectively. The connecting portion electrically connects the first and second semiconductor pillars. The first memory film is provided between the electrode film and the semiconductor pillar. The dividing portion electrically divides the first and second electrode films from each other between the first semiconductor pillar and the second semiconductor pillar, is in contact with the connecting portion, and includes a stacked film including a material used for the first memory film.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toru Matsuda
  • Patent number: 8994112
    Abstract: A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper portion (30) and the lower portion (32) acts as a diode; and the FinFET further comprises: at least one layer (26, 28) of high-k dielectric material (for example Si3N4) adjacent at least one side of the fin (12) for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion (30) is connected to a first potential and the lower portion (32) is connected to a second potential thereby providing the potential drop across the junction (34). Examples of the k value for the high-k dielectric material are k?5, k?7.5, and k?20.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gerben Doornbos, Robert Lander
  • Patent number: 8987087
    Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 24, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Henry Chien, Donovan Lee, Vinod R. Purayath, Yuan Zhang, James K. Kai, George Matamis
  • Patent number: 8987809
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
  • Patent number: 8987804
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Masayuki Tanaka, Kazuhiro Matsuo
  • Patent number: 8981458
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Patent number: 8981457
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 17, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Mark G. Johnson, Paul Michael Farmwald, Igor G. Kouznetzov
  • Patent number: 8981450
    Abstract: A semiconductor device includes conductive layers and interlayer insulating layers stacked alternately with each other, at least one first channel layer passing through the conductive layers and the interlayer insulating layers, at least one second channel layer coupled to the first channel layers and passing through the conductive layers and the interlayer insulating layers, a first insulating layer interposed between the at least one first channel layer and the conductive layers, and a second insulating layer interposed between the at least one second channel layer and the conductive layers and having a higher nitrogen concentration than the first insulating layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dae Gyu Shin
  • Patent number: 8975683
    Abstract: A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki-Hong Lee, Kwon Hong, Dae-Gyu Shin
  • Patent number: 8969943
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Hiraku Chakihara, Kota Funayama, Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Patent number: 8957471
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Fukuzumi
  • Patent number: 8958246
    Abstract: A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a Mth vertically foldable memory module in a Nth column and a source of a source selection transistor in a (M?1)th memory module in a (N+1)th column are connected to a same bit line, gates of the drain selection transistors and the source selection transistors in all the memory modules in the Nth column are connected to a same drain selection line and a same source selection line.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: February 17, 2015
    Assignee: Tsinghua University
    Inventors: Liyang Pan, Fang Yuan
  • Patent number: 8957472
    Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: February 17, 2015
    Assignee: Spansion LLC
    Inventors: Ashot Melik-Martirosian, Mark T. Ramsbey, Mark W. Randolph
  • Patent number: 8946670
    Abstract: A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The 3D semiconductor device includes a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the LDD region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam Kyun Park
  • Patent number: 8941171
    Abstract: Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A dielectric material is formed on the semiconductor between the pair of source/drain regions. A control gate is formed on the dielectric material. A charged species is introduced into the dielectric material. The charged species, e.g., mobile ions, has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 8937347
    Abstract: A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: January 20, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Guan-Wei Wu, I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
  • Patent number: 8928062
    Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Yasuda
  • Patent number: 8928063
    Abstract: A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Dong-Sun Sheen, Seung-Ho Pyi, Sung-Jin Whang
  • Patent number: 8921916
    Abstract: A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Chih-Jen Huang
  • Patent number: 8921924
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a cell transistor, an extraction section, a guard ring, a first transistor, and a second transistor. The semiconductor substrate includes first, second, third, and fourth regions. The fourth region includes first and second portions. The cell transistor is provided on the first region and includes a first insulating film, a charge storage film, and a first electrode. The extraction section is provided on the second region and includes a second insulating film, and an extension electrode. The guard ring is provided on the third region and includes a third insulating. The first transistor is provided on the first portion and includes a fourth insulating, and a second electrode. The second transistor is provided on the second portion and includes a fifth insulating film, and a third electrode.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiko Kato, Tatsuya Kato
  • Patent number: 8921823
    Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Jian Li
  • Patent number: 8921920
    Abstract: A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Kawanaka, Kosuke Tatsumura, Naoki Yasuda, Jun Fujiki, Atsushi Kawasumi
  • Patent number: 8921921
    Abstract: A nonvolatile memory device includes a stacked structure disposed over a substrate and having a plurality of interlayer dielectric layers and conductive layers that are alternately stacked, a plurality of holes formed to pass through the stacked structure to expose the substrate, a first memory layer and a second memory layer formed separately in a circumference of each hole, and a first channel layer and a second channel layer formed respectively on the first and second memory layers.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jung-Ryul Ahn
  • Patent number: 8916923
    Abstract: According to one embodiment, in a nonvolatile semiconductor memory in which a charge store layer is formed on a tunnel insulating film formed on a channel region of a semiconductor substrate, a first nanoparticle layer containing first conductive nanoparticles is formed on the channel side, and a second nanoparticle layer containing a plurality of second conductive nanoparticles having an average particle size larger than the first conductive nanoparticles is formed on the charge store layer side. An average energy value ?E1 required for charging one electron in the first conductive nanoparticle is smaller than an average energy value ?E required for charging one electron in the second conductive nanoparticle, and a difference between ?E1 and ?E is larger than a heat fluctuation energy (kBT).
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuji Ohba
  • Patent number: 8916432
    Abstract: Methods of forming memory cells including non-volatile memory (NVM) and MOS transistors are described. In one embodiment the method includes: depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a NVM transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain adjacent to the gate of the NVM transistor.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 23, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar
  • Patent number: 8916922
    Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Tae Jang, Myoung-Bum Lee, Ji-Youn Seo, Chang-Won Lee, Yong-Chae Jung, Woong-Hee Sohn
  • Patent number: 8916926
    Abstract: A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeong-In Choe, Sunil Shim, Sung-Hwan Jang, Woonkyung Lee, Jaehoon Jang
  • Patent number: 8912584
    Abstract: A semiconductor device includes a PFET transistor (a PMOS FET) having a poly(silicon) layer with a p-type doped portion and an n-type doped portion. The p-type doped portion is located above a channel region of the transistor and the n-type doped portion is located in an end portion of the poly layer outside the channel region. The poly layer may be formed by doping portions of an amorphous silicon layer with either the p-type dopant or the n-type dopant and then annealing the amorphous silicon layer to diffuse the dopants and crystallize the amorphous silicon to form polysilicon. The n-type doped portion of the poly layer may provide an electrical shunt in the end portion of the poly layer to reduce any effects of insufficient diffusion of the p-type dopant in the poly layer.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventor: Date Jan Willem Noorlag