Lead Frame Patents (Class 438/123)
  • Patent number: 11175162
    Abstract: An integrated circuit sensor package (1) with a package body (5) moulded at least in part around a substrate (2) and a plurality of lead frame members (6, 8). The substrate (2) has a first sensor element (3) on a first side surface (2a). The package body (5) comprises an aperture (5a) exposing a sensitive surface (4) of the first sensor element (3). Electrically conductive glue connections (7, 9) are provided between contact terminals of the first sensor element (3) and one or more of the plurality of lead frame members (6, 8).
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 16, 2021
    Assignee: Sencio B.V.
    Inventor: Ignatius Josephus van Dommelen
  • Patent number: 11127660
    Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 21, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
  • Patent number: 11101200
    Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 24, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
  • Patent number: 11088056
    Abstract: A leadframe includes a substrate and a surface layer covering the substrate. The surface layer includes an acicular oxide containing CuO at a higher concentration than any other component of the acicular oxide. A leadframe package includes the leadframe, a semiconductor chip mounted on the leadframe, and a resin that covers the semiconductor chip and at least a part of the leadframe.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 10, 2021
    Inventors: Ryota Furuno, Kimihiko Kubo
  • Patent number: 11055568
    Abstract: The current document is directed to methods and systems that employ image-recognition and machine learning to directly measure application-program response time from changes in a user interface displayed by the application program in much the same way that application-program users perceive response times when manually issuing commands through the user interface. The currently disclosed methods and systems involve building recognition models, training the recognition models to recognize application-program states from changes in the user interface displayed by the application program, and using the recognition models to monitor the user interface displayed by an application program to detect and assign timestamps to application-program state changes, from which the elapsed time for various different operations is computed.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: July 6, 2021
    Assignee: VMware, Inc.
    Inventors: Lan Vu, Uday Kurkure, Hari Sivaraman, Aravind Kumar Rao Bappanadu, Mohit Mangal
  • Patent number: 11004699
    Abstract: An electronic device comprises: an electronic component; a resin molded body in which the electronic component is embedded and fixed; and a bendable bend portion continuous with the resin molded body. For example, the bend portion is molded integrally with the resin molded body. Thus, electronic device can be reduced in size and thickness.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 11, 2021
    Assignee: OMRON Corporation
    Inventors: Wakahiro Kawai, Tetsuya Katsuragawa
  • Patent number: 10980106
    Abstract: Apparatus related to conformal coating implemented with surface mount devices. In some embodiments, a radio-frequency (RF) module includes a packaging substrate configured to receive a plurality of components. The RF also includes a surface mount device (SMD) mounted on the packaging substrate, the SMD including a metal layer that faces upward when mounted. The RF module further includes an overmold formed over the packaging substrate, the overmold dimensioned to cover the SMD. The RF module further includes an opening defined by the overmold at a region over the SMD, the opening having a depth sufficient to expose at least a portion of the metal layer. The RF module further includes a conformal conductive layer formed over the overmold, the conformal conductive layer configured to fill at least a portion of the opening to provide an electrical path between the conformal conductive layer and the metal layer of the SMD.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 13, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony James Lobianco, Howard E. Chen, Robert Francis Darveaux, Hoang Mong Nguyen, Matthew Sean Read, Lori Ann Deorio
  • Patent number: 10957666
    Abstract: In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Patent number: 10903148
    Abstract: Methods are provided for forming an IC power package including a power MOSFET device, a microprocessor/driver, and/or other discrete electronics. A lead frame may be etched to form a half-etch lead frame defining component attach structures at the top side of the lead frame. A power MOSFET may be mounted to a die attach pad defined in the half-etch lead frame, and the structure may be overmolded. The top of the overmolded structure may be grinded to reduce a thickness of the power MOSFET and expose a top surface of the MOSFET through the surrounding mold compound. A conductive contact may be formed on a top surface of the MOSFET. Selected portions of the half-etch lead frame may be etched from the bottom-up to separate the MOSFET from other package components, and to define a plurality of package posts for solder-mounting the package to a PCB.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 26, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Man Kit Lam
  • Patent number: 10896901
    Abstract: The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 19, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Patent number: 10825757
    Abstract: Various example embodiments concern an integrated circuit (IC) package having a clip with a protruding tough-shaped finger portion. The clip can be used in various IC packages including, for example, soft-soldered compact power packages such as rectifiers with specified surge current capability. Such embodiments can be implemented to allow for a visual inspection capability of the soldering area for connecting a lead frame, via the clip, to a surface of the IC package die, while still providing sufficient thermal mass to limit the temperature increase during forward surge current loads. This results in a simple to manufacture design without compromising too much on performance.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 3, 2020
    Assignee: NEXPERIA B.V.
    Inventors: Haibo Fan, Pompeo v Umali, Tim Boettcher, Wai Wong Chow
  • Patent number: 10811337
    Abstract: A semiconductor device includes a first electrode plate, a second electrode plate disposed to oppose the first electrode plate, and a semiconductor chip disposed between the first electrode plate and the second electrode plate. At least one of the first electrode plate and the second electrode plate has a space where a cooling medium circulates.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Shigeaki Hayase
  • Patent number: 10770576
    Abstract: A MOSFET device is integrated in a body of semiconductor material of a first conductivity type accommodating a body region, of a second conductivity type, and a source region, of the first conductivity type. A gate region extends over the top surface of the body; a source pad extends over the first top surface and is electrically coupled to the source region, a first gate pad extends over the first main surface, alongside the source pad, and is electrically coupled to the gate region; a drain pad extends over the rear surface and is electrically coupled to the body; a second gate pad extends over the rear surface, alongside the drain pad; and a conductive via extends through the body and electrically couples the gate region to the second gate pad.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Russo, Cristiano Gianluca Stella
  • Patent number: 10763237
    Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 1, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Min Lo, Chee-Key Chung, Chang-Fu Lin, Kuo-Hua Yu, Hsiang-Hua Huang
  • Patent number: 10643930
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadatoshi Danno, Atsushi Nishikizawa, Hiroyuki Nakamura
  • Patent number: 10619179
    Abstract: An electrochemical measuring method uses an electrochemical measuring device in which a measuring liquid is filled into a well. The electrochemical measuring method includes: a step of applying a measuring voltage to a working electrode and measuring a value of a first current flowing in the working electrode; a step of applying a non-measuring voltage to the working electrode; a step of introducing the biological sample into a container; and a step of applying the measuring voltage to the working electrode and measuring a value of a second current flowing in the working electrode.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 14, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kaoru Hiramoto, Masahiro Yasumi, Hiroshi Ushio, Atsushi Shunori
  • Patent number: 10529672
    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 7, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
  • Patent number: 10490488
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Roger M. Arbuthnot, Stephen St. Germain
  • Patent number: 10475977
    Abstract: A light emitting device includes an element container and a light emitting element. The element container has a first electrode lead, a second electrode lead, and a resin molded body integrated with the first electrode lead and the second electrode lead and includes an indentation at an outer surface, a wire covered with the resin molded body and extending from the first electrode lead to the indentation. The light emitting element is housed in the element container and electrically connected to the first electrode lead and the second electrode lead.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 12, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Motohisa Nogi, Saiki Yamamoto
  • Patent number: 10418353
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Eun Lee, Hyung-Dong Lee, Eun Ko
  • Patent number: 10411110
    Abstract: A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 10, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang
  • Patent number: 10332863
    Abstract: The invention relates to a 3D electronic module including, in a direction referred to as the vertical direction, a stack (4) of electronic dice (16), each die including at least one chip (1) provided with interconnect pads (10), this stack being attached to an interconnect circuit (2) for the module provided with connection bumps, the pads (10) of each chip being connected by electrical bonding wires (15) to vertical buses (41) that are themselves electrically linked to the interconnect circuit (2) for the module, a bonding wire and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnect circuit, characterized in that each electrical bonding wire (15) is linked to its vertical bus (41) by forming, in a vertical plane, an oblique angle (?2) and in that the length of the bonding wire between a pad of a chip of one die and the corresponding vertical bus is different than the length of the bonding wire between one and the same pad of a chip of another di
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 25, 2019
    Assignee: 3D PLUS
    Inventor: Christian Val
  • Patent number: 10325878
    Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 18, 2019
    Assignee: KULICKE AND SOFFA INDUSTRIES, INC.
    Inventors: Basil Milton, Wei Qin
  • Patent number: 10325835
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: June 18, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger M. Arbuthnot, Stephen St. Germain
  • Patent number: 10297556
    Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: May 21, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
  • Patent number: 10297566
    Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 21, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Yu-Ming Chen
  • Patent number: 10297535
    Abstract: A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Reyn Qin, Lucy Fan, Meifang Song, Xiaoli Wang
  • Patent number: 10252454
    Abstract: A manufacturing method of a semiconductor device includes the steps of: preparing a lead frame; mounting a plurality of semiconductor chips on the lead frame; and sealing one portion of the lead frame with a sealing resin. The resin-sealing step includes the step of: disposing the lead frame, molds having main surfaces on which cavity parts are formed, the lead frame being disposed on the main surface of the heated molds; injecting a resin in the main surfaces of the heated molds so as to seal the one portion of the lead frame with the sealing resin; and taking out the lead frame from the heated molds. In the taking-out step, while the lead frame is taken out, the main surfaces of the molds are inspected by using a sensor, and the sensor is cooled and formed integrally with an arm used for taking out the lead frame.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 9, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Itaru Matsuo
  • Patent number: 10157849
    Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fan Huang, Cheng-Tar Wu, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10157860
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a stiffener on a substrate, wherein a first section of the stiffener and a second section of the stiffener are on opposite sides of an opening. At least one component may be attached on the substrate within the opening, wherein the at least one component is disposed between the first section of the stiffener and the second section of the stiffener, and wherein the stiffener comprises a grounding structure disposed on the substrate.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Kedar Dhane, Yongki Min, William J. Lambert
  • Patent number: 10109562
    Abstract: A leadframe includes first and second parts separated from each other, and each comprises at least one anchoring hole. The first part comprises a mounting area, the second part comprises an edge line facing the first part which is curved, and the first part comprises first, second and third portions each having a maximum width, wherein the mounting area is arranged at the third portion, and the third portion follows the second portion and the second portion follows the first portion in a direction of a longitudinal extent of the first part such that the third portion faces the second part.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: October 23, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Sok Gek Beh, Mei See Boon, Wing Yew Wong, Hui Ying Pee
  • Patent number: 10096555
    Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 9, 2018
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert
  • Patent number: 10068837
    Abstract: A universal preformed lead frame device includes a plurality of spaced-apart longitudinal and transverse sections, and a plurality of preformed lead frame units each surrounded by two adjacent ones of the longitudinal and transverse sections and each includes a die pad, a plurality of spaced-apart leads, and a molding layer. The die pad includes a bottom portion, a die support portion and a plurality of spaced-apart pillar portions extending upwardly from the bottom portion. The leads extend from the two adjacent ones of the longitudinal and transverse sections toward the die pad. The molding layer is made of a polymeric material and fills gaps formed among the die support portion, the pillar portions, and the leads.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 4, 2018
    Assignee: Chang Wah Technology Co., LTD.
    Inventor: Chia-Neng Huang
  • Patent number: 9991246
    Abstract: A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 9911714
    Abstract: A lead frame includes adjacent die pads which lie adjacent to each other; grounding leads extended from the adjacent die pads; a connecting bar by which the grounding leads extended from the adjacent die pads are interconnected. The grounding leads and the connecting bar are formed to be thinner at one surface than a maximum thickness of leads of the lead frame, the grounding leads extended from the adjacent die pads are aligned on a common axis while providing the connecting bar between the grounding leads, and a support projection is provided at the one surface on the connecting bar in the common axis.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: March 6, 2018
    Assignee: MITSUI HIGH-TEC, INC.
    Inventor: Takahiro Ishibashi
  • Patent number: 9824960
    Abstract: Provided is a lead frame including: one or more solder bonding regions containing copper material or copper plating; and a molding resin adhesion region containing a copper oxide film. The solder bonding regions are exposed on a surface of the lead frame. Further, provided is a lead frame manufacturing method including: forming a resist film in a molding resin adhesion region that is included in a surface of a lead frame member made of copper, or that is included in a surface of a copper-plated lead frame member; forming a plating film by performing a metal plating process on one or more solder bonding regions included in the surface of the lead frame member; removing the resist film; and forming a copper oxide film by oxidizing the molding resin adhesion region.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: November 21, 2017
    Assignee: Mitsui High-tec, Inc.
    Inventors: Takahiro Ishibashi, Kimihiko Kubo, Ryota Furuno, Takaaki Katsuda
  • Patent number: 9799589
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 24, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9659892
    Abstract: A method of manufacturing a semiconductor device includes: arranging a solder material containing at least tin, between a semiconductor element and a joined member provided with a nickel layer and a copper layer, such that the solder material is in contact with the copper layer, the nickel layer being provided on a surface of the joined member, and the copper layer being provided on at least a portion of a surface of the nickel layer; and melting and solidifying the solder material to form Cu6Sn5 on the surface of the nickel layer using tin of the solder material and the copper layer.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: May 23, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Kadoguchi, Hiroshi Yanagimoto, Motoki Hiraoka
  • Patent number: 9607965
    Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 28, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
  • Patent number: 9599655
    Abstract: A semiconductor device capable of simplifying wiring work is provided. A semiconductor device includes a semiconductor element (insulated gate bipolar transistor IGBT) provided with an emitter main electrode and an emitter sense electrode, an integrated circuit having a detection terminal and a mold resin body that seals the semiconductor element and the integrated circuit, and a lead. The lead is provided with an inner lead part sealed in the mold resin body and electrically connected to the emitter sense electrode, an inner lead part sealed in the mold resin body and electrically connected to the emitter main electrode, and an outer lead part connected to the lead part on one side, connected to the inner lead part on the other side and exposed outside the mold resin body.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Nakamura
  • Patent number: 9543169
    Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: January 10, 2017
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Satoshi Shibasaki, Koji Tomita, Masaki Yazaki, Kazuyuki Miyano, Atsushi Kurahashi, Kazuhito Uchiumi, Masachika Masuda
  • Patent number: 9472482
    Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 18, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Takumi Ihara, Masami Mouri
  • Patent number: 9474153
    Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 18, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ai Kiar Ang, Michael Lauri
  • Patent number: 9412690
    Abstract: A package substrate includes a substrate body and a plurality of patterns disposed on the substrate body. The substrate body has a first region including a chip attachment region and a second region adjacent to the first region. The plurality of patterns are disposed on the substrate body in the second region. Each of the plurality of patterns extends in a first direction to have a stripe shape, and the plurality of patterns are spaced apart from each other in a second direction which is substantially perpendicular to the first direction. Related fabrication methods, electronic systems and memory cards are also provided.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: August 9, 2016
    Assignee: SK HYNIX INC.
    Inventors: Tae Ho Lee, Il Hwan Cho, In Chul Hwang, Ga Hyun No
  • Patent number: 9396982
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: July 19, 2016
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Hwee-Seng Jimmy Chew, Chee Kian Ong, Bin Chichik Abd. Razak
  • Patent number: 9392691
    Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Ai Kiar Ang, Michael Lauri
  • Patent number: 9379505
    Abstract: A method of manufacturing a lead frame includes, firstly, forming a metal plate which has a frame portion, a pad portion for mounting semiconductor elements, and lead portions. After that, the lead portions are etched to form a support end, a connecting terminal and a jointing end of each lead portion. Then a receiving portion for receiving the semiconductor elements is formed, wherein the receiving portion is collectively defined by the connecting terminals, the support ends and the pad portion. After that, step portions are formed on the lead portions and the pad portion by half-etching. A method of manufacturing a semiconductor package which includes the lead frame is also provided.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: June 28, 2016
    Assignee: SHUNSIN TECHNOLOGY (ZHONG SHAN) LIMITED
    Inventor: Wang-Lai Yang
  • Patent number: 9373585
    Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130), possibly dielectric, coated with a conductive material (144) which provides one or more conductive lines. In some embodiments, the conductive material covers a part, but not all, of the polymer member. In some embodiments, multiple conductive lines are formed on the polymer member. In some embodiments, the polymer member is conductive. Such interconnects replace metal bond wires in some embodiments. Other features are also provided.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: June 21, 2016
    Assignee: INVENSAS CORPORATION
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Charles G. Woychik, Guilian Gao, Arkalgud R. Sitaram
  • Patent number: 9373567
    Abstract: Disclosed herein are various chip lead frame and packaging structures, and methods of fabrication. In one embodiment, a lead frame can include: (i) a horizontal plate arranged at a bottom of the lead frame, where the horizontal plate is conductive; and (ii) a plurality of conductive bumps arranged on a surface of the horizontal plate, where the plurality of conductive bumps are configured to support and electrically connect to at least one chip. In one embodiment, a method of making the lead frame can include: (i) forming the horizontal plate by a mold; (ii) arranging a mask with a through-hole on the surface of the horizontal plate; (iii) electroplating conducting material on a portion of the horizontal plate that is exposed by the through-hole; and (iv) removing the mask after formation of the plurality of conductive bumps. Also, a package structure can be formed using the lead frame.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: June 21, 2016
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Xiaochun Tan
  • Patent number: 9324642
    Abstract: A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. A semiconductor die is attached to the die paddles. A molding compound covers the unit lead frames, including the semiconductor dies. Prior to testing or other processing of the lead frame strip, a gap is etched into a region of the leads which are shared by adjacent ones of the unit lead frames. The gap extends at least mostly through the shared leads. A partial cut is made in the molding compound around the periphery of the unit lead frames prior to the subsequent processing, including below the gap in the shared leads, to electrically isolate the leads of the unit lead frames.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: April 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Frank Püschner, Bernhard Schätzler, Teck Sim Lee, Franz Gabler, Pei Pei Kong, Boon Huat Lim