Abstract: A current sensor is configured by at least one magnetoelectric conversion element, a conductor, and a signal processing IC being encapsulated by an encapsulating portion. The current sensor includes a pair of first lead terminals that is partially exposed outside of the encapsulating portion, is electrically connected to the conductor, inputs the measurement current to the conductor, and outputs the measurement current from the conductor; a metal member that is partially exposed outside the encapsulating portion and is spaced apart from the conductor; and a supporting portion that supports the at least one magnetoelectric conversion element, the signal processing IC, and the metal member on a first surface, is separated from the conductor, and is separate from the metal member.

Abstract: A semiconductor device includes a silicon die having a metal material coating applied on one side, a lead frame having a mounting pad having an area smaller than an area of the silicon die, the silicon die being mounted on the lead frame via the mounting pad, and an etched area filled with a non-conductive mold compound on a side of the lead frame that comes into contact with an end of the silicon die along an edge of the silicon die. A volume of epoxy material is dispensed onto the lead frame along a length of the metal material coating to form a fillet weld on a side of the silicon die configured to adhere the silicon die to the lead frame and to prevent the metal material coating from coming into contact with the lead frame.

Abstract: An in-line power device, a semiconductor assembly, an in-wheel motor driver or a vehicle driver, and a new-energy vehicle are provided. The in-line power device includes: a body including a power chip and a wrapping layer wrapping an outer surface of the power chip; and a plurality of pins provided at a first side of the body at intervals. The plurality of pins includes a power pin, an auxiliary control pin and a control signal pin, and each pin includes a first segment provided inside the wrapping layer and a second segment provided outside the wrapping layer. The second segment of the auxiliary control pin and the second segment of the control signal pin are located in a first plane, the second segment of the power pin and the first side are located in a second plane, and the first plane is not parallel to the second plane.

Abstract: A semiconductor device includes a leadframe having a first level and a second level. The semiconductor device includes a semiconductor die and a conductive alloy. The conductive alloy is between the semiconductor die and the first level of the lead frame. The conductive alloy is configured to be a current sense element. The semiconductor device further includes a first conductive post coupling the semiconductor die to the conductive alloy, a second conductive post coupling the semiconductor die to the conductive alloy, and a third conductive post coupling the semiconductor die to the second level of the lead frame. The second conductive post is configured to be a first sense terminal. The third conductive post is configured to be a second sense terminal.

Abstract: This application provides a power semiconductor device, which includes: a semiconductor substrate, where the semiconductor substrate is doped with a first-type impurity; an epitaxial layer, that is doped with the first-type impurity, the epitaxial layer is disposed on a surface of the semiconductor substrate, a first doped region doped with a second-type impurity is disposed on a first surface that is of the epitaxial layer and that is away from the semiconductor substrate, and a circumferential edge of the first surface of the epitaxial layer has a scribing region; a first metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate, where the first metal layer is electrically connected to the epitaxial layer; a second metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate; and a passivation layer.

Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

Abstract: A package structure applied to power converters can include: a first die having a first power transistor and a first control and drive circuit; a second die having a second power transistor; a connection device configured to couple the first and second power transistors in series between a high-level pin and a low-level pin of a lead frame of the package structure; and where a common node of the first and second power transistors can be coupled to an output pin of the lead frame through a metal connection structure with a low interconnection resistance.

Abstract: An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die.

Abstract: A semiconductor device includes a pad formed on a surface of a substrate, a bonding wire for connecting the pad to an external circuit, and a resin layer covering at least a connection portion between the pad and the bonding wire and exposing at least a part of the substrate outside the pad.

Abstract: A support substrate has a mounting face with a metal heat transfer layer. Holes are provided to extend at least partially through the metal heat transfer layer. Metal heat transfer elements are disposed in the holes of the metal heat transfer layer of the support substrate. An electronic integrated circuit (IC) chip has a rear face that is fixed to the mounting face of the support substrate via a layer of adhesive material. The metal heat transfer elements disposed in the holes of the metal layer of the support substrate extend to protrude, relative to the mounting face of the support substrate, into the layer of adhesive material.

Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Abstract: A method of forming a lead frame can include: providing a frame base; providing a substrate to support the frame base; and selectively etching the frame base to form first and second type pins. The first type pins are distributed in the central area of the lead frame, and the second type of the pins are distributed in the edge area of the lead frame. The first type pins are separated from the second type of the pins, and the first and second type pins are not connected by connecting bars. A pattern of a first surface of the first and second type pins is different from that of a second surface of the first and second type pins. The metal of the first surface is different from the metal of the second surface, and the second surface is opposite to the first surface.

Abstract: A method for manufacturing a semiconductor module for an image-sensing device is disclosed. The method may comprise forming a first molding component on a first surface of a printed circuit board (PCB); mounting at least a photosensitive member to a second surface of the PCB; and forming a second molding component on the second surface of the PCB. The PCB may comprise at least an electric component on the first surface of the PCB. The first molding component may encapsulate the at least one electric component with the PCB. The second molding component may secure the photosensitive member on the PCB.

Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.

Abstract: A semiconductor device according to an embodiment is attached to a radiator and includes a heat-generating electronic component, a sealing part sealing the electronic component, a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part, and a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part. The inner lead part has a heat-dissipating end part that releases heat propagating from the outer lead part to the radiator and an electrical connecting part that is positioned between the heat-dissipating end part and the outer lead part and is electrically connected to the main electrode of the electronic component.

Abstract: An integrated circuit package, a die carrier, and a die are provided. The die carrier includes at least one die pad and a plurality of leads. The at least one die pad is suitable for carrying the die. The leads surround the at least one die pad. The leads are disposed on four sides of the die carrier. A length of a long side among the four sides is twice or more a length of a short side among the four sides. The die carrier is suitable for a QFN package or a QFP package.

Abstract: An electronic device includes a substrate having top side contact pads including metal pillars thereon or a laminate substrate having land pads with the pillars thereon. A solder including layer stack is on the pillars, the solder including layer stack having a bottom solder material layer including in physical contact with a top surface of the pillars, a metal material layer, and a capping solder material layer on the metal material layer. The metal material layer is primarily a copper layer or an intermetallic compound (IMC) layer including copper.

Abstract: A resin molded product is a terminal body 10 in which plate-like terminals 20 and a housing 40 made of synthetic resin are integrally fixed and includes bent portions 22 provided substantially at a right angle by press-working the terminals 20, molded portions 62 provided in the housing 40 to embed and cover inner curved surfaces 30 of the bent portions 22 obliquely from a lower-rear side, flat surface portions 32 provided in the form of flat surfaces on inner peripheral edge parts of side parts 22A of the bent portion 22 and disposed adjacent to the molded portions to be exposed from the molded portions, and thinned portions 34 made thinner than the flat surface portions 32 on the side parts 22A.

Abstract: An integrated circuit sensor package (1) with a package body (5) moulded at least in part around a substrate (2) and a plurality of lead frame members (6, 8). The substrate (2) has a first sensor element (3) on a first side surface (2a). The package body (5) comprises an aperture (5a) exposing a sensitive surface (4) of the first sensor element (3). Electrically conductive glue connections (7, 9) are provided between contact terminals of the first sensor element (3) and one or more of the plurality of lead frame members (6, 8).

Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

Abstract: A leadframe includes a substrate and a surface layer covering the substrate. The surface layer includes an acicular oxide containing CuO at a higher concentration than any other component of the acicular oxide. A leadframe package includes the leadframe, a semiconductor chip mounted on the leadframe, and a resin that covers the semiconductor chip and at least a part of the leadframe.

Abstract: The current document is directed to methods and systems that employ image-recognition and machine learning to directly measure application-program response time from changes in a user interface displayed by the application program in much the same way that application-program users perceive response times when manually issuing commands through the user interface. The currently disclosed methods and systems involve building recognition models, training the recognition models to recognize application-program states from changes in the user interface displayed by the application program, and using the recognition models to monitor the user interface displayed by an application program to detect and assign timestamps to application-program state changes, from which the elapsed time for various different operations is computed.

Abstract: An electronic device comprises: an electronic component; a resin molded body in which the electronic component is embedded and fixed; and a bendable bend portion continuous with the resin molded body. For example, the bend portion is molded integrally with the resin molded body. Thus, electronic device can be reduced in size and thickness.

Abstract: Apparatus related to conformal coating implemented with surface mount devices. In some embodiments, a radio-frequency (RF) module includes a packaging substrate configured to receive a plurality of components. The RF also includes a surface mount device (SMD) mounted on the packaging substrate, the SMD including a metal layer that faces upward when mounted. The RF module further includes an overmold formed over the packaging substrate, the overmold dimensioned to cover the SMD. The RF module further includes an opening defined by the overmold at a region over the SMD, the opening having a depth sufficient to expose at least a portion of the metal layer. The RF module further includes a conformal conductive layer formed over the overmold, the conformal conductive layer configured to fill at least a portion of the opening to provide an electrical path between the conformal conductive layer and the metal layer of the SMD.

Abstract: In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

Abstract: Methods are provided for forming an IC power package including a power MOSFET device, a microprocessor/driver, and/or other discrete electronics. A lead frame may be etched to form a half-etch lead frame defining component attach structures at the top side of the lead frame. A power MOSFET may be mounted to a die attach pad defined in the half-etch lead frame, and the structure may be overmolded. The top of the overmolded structure may be grinded to reduce a thickness of the power MOSFET and expose a top surface of the MOSFET through the surrounding mold compound. A conductive contact may be formed on a top surface of the MOSFET. Selected portions of the half-etch lead frame may be etched from the bottom-up to separate the MOSFET from other package components, and to define a plurality of package posts for solder-mounting the package to a PCB.

Abstract: The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.

Abstract: Various example embodiments concern an integrated circuit (IC) package having a clip with a protruding tough-shaped finger portion. The clip can be used in various IC packages including, for example, soft-soldered compact power packages such as rectifiers with specified surge current capability. Such embodiments can be implemented to allow for a visual inspection capability of the soldering area for connecting a lead frame, via the clip, to a surface of the IC package die, while still providing sufficient thermal mass to limit the temperature increase during forward surge current loads. This results in a simple to manufacture design without compromising too much on performance.

Abstract: A semiconductor device includes a first electrode plate, a second electrode plate disposed to oppose the first electrode plate, and a semiconductor chip disposed between the first electrode plate and the second electrode plate. At least one of the first electrode plate and the second electrode plate has a space where a cooling medium circulates.

Abstract: A MOSFET device is integrated in a body of semiconductor material of a first conductivity type accommodating a body region, of a second conductivity type, and a source region, of the first conductivity type. A gate region extends over the top surface of the body; a source pad extends over the first top surface and is electrically coupled to the source region, a first gate pad extends over the first main surface, alongside the source pad, and is electrically coupled to the gate region; a drain pad extends over the rear surface and is electrically coupled to the body; a second gate pad extends over the rear surface, alongside the drain pad; and a conductive via extends through the body and electrically couples the gate region to the second gate pad.

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.

Abstract: An electrochemical measuring method uses an electrochemical measuring device in which a measuring liquid is filled into a well. The electrochemical measuring method includes: a step of applying a measuring voltage to a working electrode and measuring a value of a first current flowing in the working electrode; a step of applying a non-measuring voltage to the working electrode; a step of introducing the biological sample into a container; and a step of applying the measuring voltage to the working electrode and measuring a value of a second current flowing in the working electrode.

Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: A light emitting device includes an element container and a light emitting element. The element container has a first electrode lead, a second electrode lead, and a resin molded body integrated with the first electrode lead and the second electrode lead and includes an indentation at an outer surface, a wire covered with the resin molded body and extending from the first electrode lead to the indentation. The light emitting element is housed in the element container and electrically connected to the first electrode lead and the second electrode lead.

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

Abstract: A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.

Abstract: The invention relates to a 3D electronic module including, in a direction referred to as the vertical direction, a stack (4) of electronic dice (16), each die including at least one chip (1) provided with interconnect pads (10), this stack being attached to an interconnect circuit (2) for the module provided with connection bumps, the pads (10) of each chip being connected by electrical bonding wires (15) to vertical buses (41) that are themselves electrically linked to the interconnect circuit (2) for the module, a bonding wire and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnect circuit, characterized in that each electrical bonding wire (15) is linked to its vertical bus (41) by forming, in a vertical plane, an oblique angle (?2) and in that the length of the bonding wire between a pad of a chip of one die and the corresponding vertical bus is different than the length of the bonding wire between one and the same pad of a chip of another di

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

Abstract: A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.

Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

Abstract: A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.

Abstract: A manufacturing method of a semiconductor device includes the steps of: preparing a lead frame; mounting a plurality of semiconductor chips on the lead frame; and sealing one portion of the lead frame with a sealing resin. The resin-sealing step includes the step of: disposing the lead frame, molds having main surfaces on which cavity parts are formed, the lead frame being disposed on the main surface of the heated molds; injecting a resin in the main surfaces of the heated molds so as to seal the one portion of the lead frame with the sealing resin; and taking out the lead frame from the heated molds. In the taking-out step, while the lead frame is taken out, the main surfaces of the molds are inspected by using a sensor, and the sensor is cooled and formed integrally with an arm used for taking out the lead frame.

Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.