Showerhead for semiconductor processing

- Lam Research Corporation
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Description

FIG. 1 is an isometric view of a first embodiment of a showerhead for semiconductor processing.

FIG. 2 is a front view thereof.

FIG. 3 is a back view thereof.

FIG. 4 is a right-side view thereof.

FIG. 5 is a left-side view thereof.

FIG. 6 is a top view thereof.

FIG. 7 is a bottom view thereof.

FIG. 8 is a perspective view thereof.

FIG. 9 is another perspective view thereof.

FIG. 10 is the top view thereof.

FIG. 11 is an enlarged partial view of the area shown in FIG. 10.

FIG. 12 is a cross-sectional view along line 12-12 shown in FIG. 10.

FIG. 13 is an enlarged partial view of the area shown in FIG. 12.

FIG. 14 is the bottom view thereof.

FIG. 15 is an enlarged view of the area shown in FIG. 14.

FIG. 16 is an isometric view of a second embodiment of a showerhead for semiconductor processing.

FIG. 17 is a front view thereof.

FIG. 18 is a back view thereof.

FIG. 19 is a right-side view thereof.

FIG. 20 is a left-side view thereof.

FIG. 21 is a top view thereof.

FIG. 22 is a bottom view thereof.

FIG. 23 is a perspective view thereof.

FIG. 24 is another perspective view thereof.

FIG. 25 is the top view thereof.

FIG. 26 is an enlarged partial view of the area shown in FIG. 25.

FIG. 27 is a cross-sectional view along line 27-27 shown in FIG. 25.

FIG. 28 is an enlarged partial view of the area shown in FIG. 27.

FIG. 29 is the bottom view thereof; and,

FIG. 30 is an enlarged view of the area shown in FIG. 29.

The showerheads for semiconductor processing shown in FIGS. 1-30 are for use in semiconductor processing equipment in order to flow fluids, liquids, and/or gases onto a semiconductor substrate.

The dashed broken line portions in the drawings are included to show portions of the depicted articles that form no part of the claimed design. The dash-dot-dash broken line portions in the drawings are included to show boundaries of partial or sectional views.

Claims

I claim the ornamental design for a showerhead for semiconductor processing, as shown and described.

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Patent History
Patent number: D1038900
Type: Grant
Filed: Sep 30, 2021
Date of Patent: Aug 13, 2024
Assignee: Lam Research Corporation (Fremont, CA)
Inventor: Aaron Blake Miller (West Linn, OR)
Primary Examiner: Shawn T Gingrich
Assistant Examiner: Caleb M Baker
Application Number: 29/789,575