Connector for printed circuit boards

- Sony Corporation
Description

FIG. 1 is a front view of a connector for printed circuit boards showing our new design in a first embodiment, while the rear view corresponds to the front view;

FIG. 2 is a top view of the connector for printed circuit boards;

FIG. 3 is a bottom view of the connector for printed circuit boards;

FIG. 4 is a left side view of the connector for printed circuit boards, while the right side view corresponds to the left side view;

FIG. 5 is a sectional view along the line V--V in FIG. 1;

FIG. 6 is a sectional view along the line V--V in FIG. 1 in a connecting condition of printed circuit boards;

FIG. 7 is a front view of a connector for printed circuit boards showing our new design in a second embodiment, while the rear view corresponds to the front view;

FIG. 8 is a top view of the connector for printed circuit boards of the second embodiment;

FIG. 9 is a bottom view of the connector for printed circuit boards of the second embodiment;

FIG. 10 is a left side view of the conector for printed circuit boards of the second embodiment, while the right side view corresponds to the left side view;

FIG. 11 is a sectional view along the line XI--XI in FIG. 7; and,

FIG. 12 is a sectional view along the line XI--XI in FIG. 7 in a connecting condition of printed circuit boards.

The broken-line disclosure of a portion of a circuit board in the views is for illustrative purposes only and forms no part of the claimed design.

Referenced Cited
U.S. Patent Documents
D317592 June 18, 1991 Yoshizawa
D357901 May 2, 1995 Horman
D359028 June 6, 1995 Siegel et al.
5089929 February 18, 1992 Hilland
Foreign Patent Documents
898318 May 1994 JPX
898319 May 1994 JPX
908880 October 1994 JPX
908881 October 1994 JPX
Other references
  • "Electronic Parts Catalog", Electronic Industries Association of Japan, No. 58 p. 88-13, published Oct. 4, 1994 (1995 edition).
Patent History
Patent number: D402273
Type: Grant
Filed: Jun 3, 1997
Date of Patent: Dec 8, 1998
Assignees: Sony Corporation (Tokyo), Japan Solderless Terminal Mfg. Co., Ltd. (Osaka)
Inventors: Yasuhiro Kataoka (Yokohama), Terumi Nakashima (Takatsuki), Narihiko Hashimoto (Nagoya)
Primary Examiner: Brian N. Vinson
Attorneys: W. F. Fasse, W. G. Fasse
Application Number: 0/71,611
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;