Semiconductor device

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Description

FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a right side elevational view thereof, the left side elevational view is omitted as that is symmetrical to the right side elevational view thereof;

FIG. 7 is an enlarged cross-sectional view thereof, taken along line 7—7 of FIG. 2, with the internal system omitted; and,

FIG. 8 is an enlarged cross-sectional view thereof, taken along line 8—8 of FIG. 2, with the internal system omitted.

Claims

The ornamental design for a semiconductor device, as shown and described.

Referenced Cited
U.S. Patent Documents
D401912 December 1, 1998 Majumdar et al.
D421969 March 28, 2000 Kawafuji et al.
D428859 August 1, 2000 Kawafuji et al.
5089929 February 18, 1992 Hilland
5221859 June 22, 1993 Kobayashi et al.
Other references
  • Catalogue of Toshiba Corp., Toshiba APRES series, “Intelligent power module”, 1999.
Patent History
Patent number: D448739
Type: Grant
Filed: Mar 8, 2001
Date of Patent: Oct 2, 2001
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo)
Inventors: Mitsutaka Iwasaki (Tokyo), Hitoshi Toda (Tokyo), Hisashi Kawafuji (Fukuoka)
Primary Examiner: Brian N. Vinson
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/138,165
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;