Semiconductor package
Description
FIG. 1 is a front, plan and right side perspective view of a semiconductor package showing our new design;
FIG. 2 is a front, bottom and right side perspective view thereof;
FIG. 3 is a rear, plan and left side perspective view thereof;
FIG. 4 is a rear, bottom and left side perspective view thereof;
FIG. 5 is a front elevational view thereof;
FIG. 6 is a rear elevational view thereof;
FIG. 7 is a top plan view thereof;
FIG. 8 is a bottom plan view thereof;
FIG. 9 is a left side elevational view thereof; and,
FIG. 10 is a right side elevational view thereof.
Claims
The ornamental design for a semiconductor package, as shown and described.
Referenced Cited
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Patent History
Patent number: D466485
Type: Grant
Filed: May 23, 2001
Date of Patent: Dec 3, 2002
Assignee: Shindengen Electric Manufactuturing Co., Ltd. (Tokyo)
Inventors: Kenichi Maehara (Kawagoe), Koji Igarashi (Hanno)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Antonelli, Terry, Stout & Kraus, LLP
Application Number: 29/142,263
Type: Grant
Filed: May 23, 2001
Date of Patent: Dec 3, 2002
Assignee: Shindengen Electric Manufactuturing Co., Ltd. (Tokyo)
Inventors: Kenichi Maehara (Kawagoe), Koji Igarashi (Hanno)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Antonelli, Terry, Stout & Kraus, LLP
Application Number: 29/142,263
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;