Semiconductor carrier
Latest Yamaichi Electronics Co., Ltd. Patents:
Description
FIG. 1 is a top plan view of a semiconductor carrier of our new design in its entirety;
FIG. 2 is a bottom plan view of our new design;
FIG. 3 is a right end view of our new design;
FIG. 4 is a left end view of our new design;
FIG. 5 is a front view of our new design;
FIG. 6 is a rear view our new design; and,
FIG. 7 is a left, front perspective view of our new design.
Claims
The ornamental design for a semiconductor carrier, as shown and described.
Referenced Cited
U.S. Patent Documents
D359028 | June 6, 1995 | Siegel et al. |
5451165 | September 19, 1995 | Cearley-Cabbiness et al. |
5519332 | May 21, 1996 | Wood et al. |
5541525 | July 30, 1996 | Wood et al. |
D401567 | November 24, 1998 | Farnworth et al. |
20010043074 | November 22, 2001 | Hembree et al. |
20040016993 | January 29, 2004 | Ham et al. |
Patent History
Patent number: D507248
Type: Grant
Filed: Jul 27, 2004
Date of Patent: Jul 12, 2005
Assignee: Yamaichi Electronics Co., Ltd. (Tokyo)
Inventors: Minoru Hisaishi (Tokyo), Noriyuki Matsuoka (Tokyo), Takeyuki Suzuki (Tokyo)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
Application Number: 29/210,045
Type: Grant
Filed: Jul 27, 2004
Date of Patent: Jul 12, 2005
Assignee: Yamaichi Electronics Co., Ltd. (Tokyo)
Inventors: Minoru Hisaishi (Tokyo), Noriyuki Matsuoka (Tokyo), Takeyuki Suzuki (Tokyo)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
Application Number: 29/210,045
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)