Optoelectronic IC package
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Description
FIG. 1 is a top perspective view of an optoelectronic IC package of the present invention;
FIG. 2 is a first side view thereof;
FIG. 3 is a second side view thereof;
FIG. 4 is a third side view thereof;
FIG. 5 is a top view thereof; and,
FIG. 6 is a fourth side view thereof.
The ornamental design which is claimed is shown in solid lines in the drawings. Any broken lines in the drawings are for illustrative purposes only and form no part of the claimed design.
Claims
We claim the ornamental design for an optoelectronic IC package, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
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6328483 | December 11, 2001 | Havasi et al. |
6355946 | March 12, 2002 | Ishinaga |
6570190 | May 27, 2003 | Krames et al. |
D476961 | July 8, 2003 | Horiuchi et al. |
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6707069 | March 16, 2004 | Song et al. |
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20040201987 | October 14, 2004 | Omata |
D1144892 | June 2002 | JP |
D1144893 | June 2002 | JP |
D1145109 | June 2002 | JP |
Patent History
Patent number: D511331
Type: Grant
Filed: Oct 10, 2003
Date of Patent: Nov 8, 2005
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka)
Inventors: Shogo Horinouchi (Fukuoka), Hideki Ohyama (Fukuoka)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Brinks Hofer Gilson & Lione
Application Number: 29/191,635
Type: Grant
Filed: Oct 10, 2003
Date of Patent: Nov 8, 2005
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka)
Inventors: Shogo Horinouchi (Fukuoka), Hideki Ohyama (Fukuoka)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Brinks Hofer Gilson & Lione
Application Number: 29/191,635
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)