Load-lock chamber

- Tokyo Electron Limited
Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description

The present article relates to a load-lock chamber for a multi-chamber type semiconductor substrate processing apparatus for a film forming process and other processes for semiconductor substrates, and others to be processed. The load-lock chamber is, as shown in a reference drawing illustrating a state of usage of the load-lock chamber, connected to a transfer-chamber wherein load-in and load-out of substrates to be processed are carried out without exposing the transfer-chamber to air.

FIG. 1 is a top view of the load-lock chamber,

FIG. 2 is a front elevational view thereof;

FIG. 3 is a back elevational view thereof;

FIG. 4 is a bottom view thereof;

FIG. 5 is a right side view thereof;

FIG. 6 is a left side view thereof;

FIG. 7 is a sectional view taken along line 7-7 in FIG. 1;

FIG. 8 is a perspective view thereof; and,

FIG. 9 is a reference figure showing a bottom perspective view thereof.

The broken line showing of the environment is for illustrative purpose only and forms no part of the claimed design.

Claims

The ornamental design for a load-lock chamber, as shown and described.

Referenced Cited
U.S. Patent Documents
6045620 April 4, 2000 Tepman et al.
6270582 August 7, 2001 Rivkin et al.
6382902 May 7, 2002 Sugimura
20050005847 January 13, 2005 Hiroki
20050095088 May 5, 2005 Kurita et al.
20050193948 September 8, 2005 Oohirabaru et al.
20050205012 September 22, 2005 Jang
20050247265 November 10, 2005 Devine et al.
20060021575 February 2, 2006 Ishizawa et al.
Patent History
Patent number: D556157
Type: Grant
Filed: Nov 22, 2004
Date of Patent: Nov 27, 2007
Assignee: Tokyo Electron Limited (Tokyo)
Inventors: Keisuke Kondoh (Yamanashi), Hiroki Oka (Yamanashi), Makoto Tashiro (Yamanashi)
Primary Examiner: Selina Sikder
Attorney: Smith, Gambrell & Russell, LLP
Application Number: 29/217,730