Shadow frame
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Description
The broken line portion of
Claims
The ornamental design for a shadow frame, as shown and described.
Referenced Cited
U.S. Patent Documents
5352294 | October 4, 1994 | White et al. |
6106631 | August 22, 2000 | Inoue et al. |
6355108 | March 12, 2002 | Won et al. |
6744562 | June 1, 2004 | Okada et al. |
6746198 | June 8, 2004 | White et al. |
6773562 | August 10, 2004 | Inagawa et al. |
D568839 | May 13, 2008 | Mitsui et al. |
D608742 | January 26, 2010 | Tiner |
D608743 | January 26, 2010 | Tiner |
20040123799 | July 1, 2004 | Clark |
20060011137 | January 19, 2006 | Keller |
20060103289 | May 18, 2006 | Kim et al. |
20060148368 | July 6, 2006 | Kang et al. |
20080213679 | September 4, 2008 | Miyakawa et al. |
20090283036 | November 19, 2009 | Duong et al. |
Patent History
Patent number: D631858
Type: Grant
Filed: Nov 17, 2008
Date of Patent: Feb 1, 2011
Assignee: Applied Materials, Inc. (Santa Clara, CA)
Inventor: Kyung-Tae Kim (Suwon)
Primary Examiner: Thomas J Johannes
Attorney: Patterson & Sheridan, LLP
Application Number: 29/327,995
Type: Grant
Filed: Nov 17, 2008
Date of Patent: Feb 1, 2011
Assignee: Applied Materials, Inc. (Santa Clara, CA)
Inventor: Kyung-Tae Kim (Suwon)
Primary Examiner: Thomas J Johannes
Attorney: Patterson & Sheridan, LLP
Application Number: 29/327,995
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)