Transistors Patents (Class 365/104)
  • Patent number: 10284072
    Abstract: A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 7, 2019
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Patent number: 10269439
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 23, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Patent number: 10229874
    Abstract: An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: March 12, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10229025
    Abstract: An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 12, 2019
    Assignee: NXP USA, INC.
    Inventors: Xuewen He, Xiaoxiang Geng, Lei Zhang
  • Patent number: 10199118
    Abstract: A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Seok Lee, Hyun-Taek Jung
  • Patent number: 10170197
    Abstract: A semiconductor device includes: first to Nth non-volatile memory areas, each including a plurality of cells positioned at cross points between row lines and column lines; a storage circuit including a plurality of unit latches suitable for storing data transferred from the first to Nth non-volatile memory areas; and an operation control circuit suitable for controlling setup information of first to Nth operation modes to be programmed in the first to Nth non-volatile memory areas, respectively, during a rupture mode, and controlling a data transferred from the first non-volatile memory area to be written in the unit latches and controlling a data transferred from one of the second to Nth non-volatile memory areas to be over-written in the unit latches in response to an operation mode change request, during a boot-up mode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: January 1, 2019
    Assignee: SK Hynix Inc.
    Inventors: Hyeong-Soo Jeong, Jong-Ho Son
  • Patent number: 10090063
    Abstract: A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 10056141
    Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: August 21, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Brent Buchanan
  • Patent number: 10026494
    Abstract: A method of generating a high differential read current through a non-volatile memory, includes receiving a voltage read input from a word line voltage generator, outputting a first current to a bit line true (BLT), outputting a second current to a bit line complement (BLC), and generating the high differential read current through a difference between the first current and the second current.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric D. Hunt-Schroeder
  • Patent number: 10020038
    Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Mamoru Nishizaki
  • Patent number: 9945329
    Abstract: An internal combustion engine includes a cylinder block defining first and second cylinders, and a cylinder head coupled to the block. The engine also includes a passage having a first outlet and a second outlet for exhausting post-combustion gasses from the cylinder head. The engine additionally includes a mechanism for selectively activating and deactivating the first cylinder and a turbocharging system having a low-flow turbocharger and a high-flow turbocharger. The low-flow turbocharger is driven by gasses from the first outlet and the high-flow turbocharger is driven by gasses from the second outlet. The turbocharging system also includes a first flow-control device that directs the gasses via the first and second outlets to the turbochargers when the first and second cylinders are activated. The first flow-control device also directs the gasses via the first outlet only to the low-flow turbocharger and blocks the second outlet when the first cylinder is deactivated.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: April 17, 2018
    Assignee: GM Global Technology Operations LLC
    Inventor: Ko-Jen Wu
  • Patent number: 9941011
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 10, 2018
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 9935105
    Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: April 3, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 9910607
    Abstract: In one embodiment, the method includes determining whether a selection transistor of a currently programmed memory string in the memory has deteriorated, and copying data in the currently programmed memory string to a different memory string of the memory if the determining determines the selection transistor has deteriorated.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangyong Yoon, Jinman Han
  • Patent number: 9898568
    Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 20, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Naveen Chandra Srivastava, Janardhan Achanta, Pankaj Kumar, Shreekanth Karandoor Sampigethaya
  • Patent number: 9900008
    Abstract: A pre-driver includes a first inverter, a second inverter, an amplifier, a first capacitor, and a second capacitor. The first inverter has an input terminal for receiving an input signal at an input node, and an output terminal coupled to an inner node. The second inverter has an input terminal coupled to the inner node, and an output terminal for outputting an output signal at an output node. The amplifier is configured to amplify the input signal by a gain factor so as to generate an amplified signal and an inverted amplified signal. The first capacitor has a first terminal coupled to the output node, and a second terminal for receiving the amplified signal. The second capacitor has a first terminal coupled to the inner node, and a second terminal for receiving the inverted amplified signal.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: February 20, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: Yeong-Sheng Lee
  • Patent number: 9847133
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 19, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
  • Patent number: 9799409
    Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: October 24, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Dechang Sun, Wei Zhang, Mai T. MacLennan, Sudeep Ashok Pomar, Roy M. Carlson
  • Patent number: 9734881
    Abstract: A memory device and a method for forming a memory device are disclosed. The memory device includes a memory cell having a storage unit coupled to a cell selector unit. The storage unit includes first and second storage elements. Each of the first and second storage elements includes first and second terminals. The second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL). The cell selector unit includes first and second selectors. The first selector includes a write select transistor (TW) and the second selector includes a first read transistor (TR1) and a second read transistor (TR2). The first selector is coupled to a word line (WL) for selectively coupling a write path to the storage unit and the second selector is coupled to a read line (RL) for selectively coupling a read path to the storage unit.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 15, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Vinayak Bharat Naik, Eng Huat Toh, Kiok Boone Elgin Quek
  • Patent number: 9704918
    Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tadashi Miyakawa, Katsuhiko Hoya, Mariko Iizuka, Takashi Nakazawa, Hiroyuki Takenaka
  • Patent number: 9697908
    Abstract: Various implementations described herein may refer to and may be directed to non-discharging read-only memory cells. For instance, in one implementation, an integrated circuit may include a read-only memory (ROM) array including a plurality of ROM cells arranged into a column, where the column is disposed proximate to a bit line and to a reference voltage line. The plurality of ROM cells arranged into the column may include a plurality of non-discharging ROM cells positioned adjacently to one another, where each non-discharging ROM cell has a source terminal, a drain terminal, or both coupled to at least one adjacent non-discharging ROM cell. In addition, the plurality of non-discharging ROM cells may be coupled to the bit line using two or fewer connections.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 4, 2017
    Assignee: ARM Limited
    Inventors: Kapil Rathi, Abhishek Kumar Shrivastava, Vikash
  • Patent number: 9691853
    Abstract: According to example embodiments, an electronic device includes channel layer including a graphene layer electrically contacting a quantum dot layer including a plurality of quantum dots, a first electrode and a second electrode electrically connected to the channel layer, respectively, and a gate electrode configured to control an electric current between the first electrode and the second electrode via the channel layer. A gate insulating layer may be between the gate electrode and the channel layer.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: June 27, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Taeho Kim, Kiyoung Lee, Seongjun Park
  • Patent number: 9653174
    Abstract: According to one embodiment, a semiconductor storage device includes memory cell array including a memory cell, a bit line coupled to the memory cell, a sense circuit coupled to the bit line and being capable of charging the bit line, and a charging circuit, the memory cell array being disposed between the sense circuit and the charging circuit and being capable of charging the bit line.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroki Date
  • Patent number: 9640263
    Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: May 2, 2017
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sakhawat M. Khan
  • Patent number: 9620176
    Abstract: A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 11, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Meng-Yi Wu, Wei-Zhe Wong, Hsin-Ming Chen
  • Patent number: 9589627
    Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: March 7, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thomas Evan Wilson, Eric Harris Naviasky
  • Patent number: 9552859
    Abstract: An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each including, connected to a source line (SL), a series connection (in any order) of a selection element (e.g., transistor gated by word line WL), a resistive storage element (e.g., MTJ), and a permanent connection to one of the bit lines (e.g., BL0, BL1). The apparatus may also include a ROM sense amplifier which is configured to precharge two output nodes connected to respective ones of the bit lines, so that the jumper in a selected memory cell pulls one of the output nodes to a first reference potential (e.g., GND) and the ROM sense amplifier pulls the other of the output nodes to a second reference potential (e.g., Vdd).
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: January 24, 2017
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventors: Kaushik Roy, Dongsoo Lee, Xuanyao Fong
  • Patent number: 9543036
    Abstract: A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: January 10, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Xia Li, Seung Hyuk Kang, Xiaochun Zhu
  • Patent number: 9529533
    Abstract: An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: December 27, 2016
    Assignee: Apple Inc.
    Inventors: Michael A. Dreesen, Naveen Javarappa, Ajay Kumar Bhatia, Greg M. Hess
  • Patent number: 9524777
    Abstract: A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: December 20, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: Deepak Kamalanathan, Ming Kwan, Venkatesh Gopinath, John Jameson
  • Patent number: 9508856
    Abstract: Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: November 29, 2016
    Assignees: Kobe Steel, Ltd., Samsung Display Co., Ltd.
    Inventors: Hiroaki Tao, Takeaki Maeda, Aya Miki, Toshihiro Kugimiya, Byung Du Ahn, So Young Koo, Gun Hee Kim
  • Patent number: 9496048
    Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: November 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaonan Chen, Zhongze Wang, Xia Li
  • Patent number: 9484114
    Abstract: A data storage device includes a memory including a plurality of storage elements configured to store data. The plurality of storage elements includes a first group of storage elements and a second group of storage elements. The data storage device further includes a selection module configured to retrieve first bit line defect information affecting the first group of storage elements and to retrieve second bit line defect information affecting the second group of storage elements.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 1, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Refael Ben-Rubi, Mark Shlick, Moshe Cohen
  • Patent number: 9484109
    Abstract: The memory cell of a memory device comprises a MOS capacitor having a n-type gate and a n-type well, a first switch to temporarily apply a breakthrough voltage across the n-type gate and the n-type well to generate a permanent conductive breakthrough structure between the n-type gate and the n-type well.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: November 1, 2016
    Assignee: The Swatch Group Research and Development Ltd.
    Inventor: Arnaud Casagrande
  • Patent number: 9484110
    Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word lines. Each memory cell includes a high Vt transistor and a low Vt transistor.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Chulmin Jung, Esin Terzioglu, Steven Mark Millendorf
  • Patent number: 9449967
    Abstract: A semiconductor circuit can include a plurality of arrays of transistors having differing characteristics and operating at low voltages and currents. A drain line drive signal may provide a potential to a drain line to which a selected transistor is connected. A row of drain mux circuits can provide reduced leakage current on the drain line drive signal so that more accurate current measurements may be made. A gate line drive signal may provide a potential to a gate line to which the selected transistor is connected. A column of gate line mux circuits can provide a gate line low drive signal to unselected transistors to reduce leakage current in unselected transistors so that more accurate drain current measurements may be made to the selected transistor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 20, 2016
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Richard S. Roy, Samuel Leshner
  • Patent number: 9400707
    Abstract: The present disclosure includes methods, devices, and systems for error detection or correction of stored signals in memory devices. An example method includes determining whether to perform error correction operations on contents of a non-volatile memory array. Determining whether to correct can include determining whether a level of errors in pre-programmed signals in the non-volatile memory array exceeds a bit error rate threshold, where the pre-programmed signals are different from the contents of the non-volatile memory array, and performing error correction on the contents of the non-volatile memory array if the level of errors exceeds the bit error rate threshold.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: July 26, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 9367475
    Abstract: The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: June 14, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ravindraraj Ramaraju, David R. Bearden, Andrew C. Russell
  • Patent number: 9362001
    Abstract: A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: June 7, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Meng-Yi Wu, Chih-Hao Huang, Hsin-Ming Chen
  • Patent number: 9350591
    Abstract: Methods for down converting a modulated carrier signal to a demodulated baseband signal are described herein. The method requires that a first portion of energy is transferred from the modulated carrier signal, and stored at a first storage device when a first switch is on. At least some of the energy stored in the first storage device is discharged when the first switch is off. The method further comprises transferring a second portion of energy from the modulated carrier signal, storing at a second storage device the second portion of transferred energy when a second switch is on, and discharging at least some of the energy stored in the second storage device when the second switch is off.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: May 24, 2016
    Assignee: ParkerVision, Inc.
    Inventors: David F. Sorrells, Michael J. Bultman, Robert W. Cook, Richard C. Looke, Charley D. Moses, Gregory S. Rawlins, Michael W. Rawlins
  • Patent number: 9324430
    Abstract: A method of generating a default state in an embedded Multi-Time-Programmable-Read-Only-Memory for a high-performance logic technology consisting of a plurality of memory cells featuring a charge trap, each having a first and a second NMOS transistor. The first and second NMOS transistors use a different mask having different threshold voltages. The second NMOS threshold voltage is adjusted to a middle point of the threshold voltage of the first NMOS with or without trapping the charge. When the charge is not trapped by the first NMOS, the NMOS threshold is lowered to the second NMOS, thereby generating a default state. When the charge is trapped to the first NMOS, the NMOS threshold is higher than the second NMOS, generating a second state. Moreover, a reference voltage generation can use two arrays, each consisting of memory cells and reference memory cells such that a default state can be generated for a single transistor per memory cell.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sheikh Sabiq Chishti, Toshiaki Kirihata, Krishnan S. Rengarajan, Deepal Wehella-Gamage
  • Patent number: 9318477
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-myoung Lee, Young-soo Song, Bo-young Lee, Jun-min Lee
  • Patent number: 9318476
    Abstract: A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: April 19, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Ohsang Kwon, Foua Vang, Animesh Datta, Seid Hadi Rasouli
  • Patent number: 9299422
    Abstract: A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first access transistor has a gate terminal coupled to a first word line. The first access transistor has a source terminal coupled to the first node. The second access transistor has a gate terminal coupled to a second word line, and the second access transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first access transistor, and the second high supply voltage provides a first differential voltage simultaneously.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: March 29, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chien-Fu Chen, Meng-Fan Chang, Hiroyuki Yamauchi, Yen-Yao Wang
  • Patent number: 9281017
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: March 8, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 9281195
    Abstract: A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: March 8, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Guan Wei Wu, Yao Wen Chang, I Chen Yang, Tao Cheng Lu
  • Patent number: 9269405
    Abstract: A semiconductor memory includes: a first switching transistor, wherein the first switching transistor has a first terminal, a second terminal, and a third terminal, and the second terminal is coupled to a first word-line; a first differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the first terminal of the first switching transistor for storing first information; and a second differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the third terminal of the first switching transistor for storing second information.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 23, 2016
    Assignee: MEDIATEK INC.
    Inventor: Chia-Wei Wang
  • Patent number: 9251862
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Patent number: 9236140
    Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: January 12, 2016
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Jitendra Dasani
  • Patent number: 9214236
    Abstract: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: December 15, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Chun Hsiung Hung