Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A memory device includes a memory cell array, a current detector and a controller. The memory cell array has a plurality of memory cell strings coupled to a common source line. The current detector detects a circulating current on the common source line or a power end of a page buffer. The controller is configured to: during a program operation, perform a first program operation on a plurality of first memory cells corresponding to logic 0 according to a first program verify voltage, and perform a second program operation on a plurality of second memory cells corresponding to logic 1 according to a second program verify voltage, where the first program verify voltage is different from the second program verify voltage; and provide a read voltage to the memory cell strings during a read operation, and sense the circulating current based on a read current reference value.

Abstract: There is provided a differential signal transmission circuit that includes a first output terminal, a second output terminal connected to the first output terminal via a load resistor, a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal, a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal, a high-side pre-driver configured to drive the high-side transistor, a low-side pre-driver configured to drive the low-side transistor, a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor, and a second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor.

Abstract: A memory controller controls a memory device including a plurality of memory blocks and a plurality of power modules respectively providing voltages to a plurality of word line groups, the memory controller comprising: a fail block detector detecting fail blocks on which an erase operation has failed among the plurality of memory blocks, and detecting fail word line groups among a plurality of word line groups included in each of the fail blocks; a fail block manager detecting, among the plurality of power modules, a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among the fail blocks; and a power defect controller controlling the memory device such that the defective power module is changed to another power module among the plurality of power modules.

Abstract: A chip aka integrated circuit, the chip comprising configuration register/s, typically volatile, and/or at least one on-chip non-volatile memory m typically including at least one reserved memory location, which may be reserved for storing contents of at least one typically volatile configuration register r, from among the configuration registers; and/or apparatus configured for, at least once, storing values which may be indicative of content of at least one typically volatile configuration register r from among the registers, e.g. in the on-chip non-volatile memory m, e.g. at the at least one reserved memory location.

Abstract: A method includes setting an output of each memory cell in an array of memory cells to a same first value, decreasing power to the array of memory cells and then increasing power to the array of memory cells. Memory cells in the array of memory cells with outputs that switched to a second value different from the first value are then identified in response to decreasing and then increasing the power. A set of memory cells is then selected from the identified memory cells to use in hardware security.

Abstract: An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.

Abstract: The present invention provides a method and a system based on a multi-gate field effect transistor for sensing molecules in a gas or liquid sample. The said FET transistor comprises dual gate lateral electrodes (and optionally a back gate electrode) located on the two sides of an active region, and a sensing surface on top of the said active region. Appling voltages to the lateral gate electrodes, creates a conductive channel in the active region, wherein the width and the lateral position of the said channel can be controlled. Enhanced sensing sensitivity is achieved by measuring the channels conductivity at a plurality of positions in the lateral direction. The use of an array of the said FTE for electronic nose is also disclosed.

Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: A time-based sensing circuit to convert resistance of a one-time programmable (OTP) element into logic states is disclosed. A one-time programmable (OTP) memory has a plurality of OTP devices. At least one of the OTP devices can have at least one OTP element that is selectively accessible via a wordline and a bitline. The bitline can be coupled a capacitor and the capacitor can be precharged and discharged. By comparing the discharge rate of the capacitor to discharge rate of a reference capacitor in a reference unit (e.g., reference cell, reference resistance, reference selector, etc.), the PRE resistance can be determined larger or smaller than a reference resistance and then converting the OTP element resistance into a logic state.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: A DRAM memory having a storage cell array is described. The storage cell array has rows and columns. The storage cell array has reserved storage cells coupled to each of the rows. The reserved storage cells to store count values that individually count activations of each of the rows.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read operation used to determine a stored logic state of the cell. The capacitance may be increased by leveraging intrinsic capacitance of digit lines of the array—e.g., by shorting one digit line to another digit line. Increasing the capacitance of the digit line may increase the signal on the digit line that is sensed during the read operation.

Abstract: A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. By allowing the sense amplifier to bias a memory cell being sensed to a selected one of multiple bias levels during a sensing operation, multiple target data states can be concurrently program verified, leading to higher performance when writing data.

Abstract: A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.

Abstract: A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory cell of a first memory cell array or a second memory cell of a second memory cell array, where a first digit line coupled to the first memory cell is coupled to a paging buffer register including a sense amplifier. The method further includes operating a transfer gate based at least in part on determining to read the second memory cell of the second memory cell array, where the transfer gate is configured to selectively couple a second digit line coupled to the second memory cell to the paging buffer register through the first digit line.

Abstract: A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive shield lines. In a second level above the first level there are rows of transistor wordlines. In a third level above the second level there are rows and columns of capacitors. In a fourth level above the third level there are rows of transistor wordlines. In a fifth level above the fourth level there are alternating columns of digitlines and conductive shield lines. Other embodiments and aspects are disclosed, including method.

Abstract: An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.

Abstract: A one-time programmable (OTP) memory device includes an OTP cell array, a latch controller, a column selection circuit, and a latch circuit. The OTP cell array includes a plurality of OTP memory cells respectively connected to a plurality of bitlines. The latch controller generates a latch address signal indicating an address that is changed sequentially in an enable mode to initialize the OTP memory device. The column selection circuit electrically connects a plurality of bitline groups of the bitlines to a plurality of input-output lines sequentially based on the latch address signal in the enable mode. The latch circuit receives and stores fuse bits provided sequentially through the bitline groups and the input-output lines in the enable mode.

Abstract: A semiconductor device includes: first to Nth non-volatile memory areas, each including a plurality of cells positioned at cross points between row lines and column lines; a storage circuit including a plurality of unit latches suitable for storing data transferred from the first to Nth non-volatile memory areas; and an operation control circuit suitable for controlling setup information of first to Nth operation modes to be programmed in the first to Nth non-volatile memory areas, respectively, during a rupture mode, and controlling a data transferred from the first non-volatile memory area to be written in the unit latches and controlling a data transferred from one of the second to Nth non-volatile memory areas to be over-written in the unit latches in response to an operation mode change request, during a boot-up mode.

Abstract: A circuit for testing a memory includes a complementary charge trap memory cell, which includes a first transistor and a second transistor. A logical value of the cell corresponds to respective states of the first transistor and the second transistor. The circuit further includes a first bitline coupled to the first transistor, where the first transistor is configured to apply a first voltage to the first bitline. The circuit includes a second bitline coupled to the second transistor, where the second transistor is configured to apply a second voltage to the second bitline. The circuit also includes a sense circuit configured to output, prior to programming of the complementary charge trap memory cell, a logical high signal or a logical low signal in response to the first voltage on the first bitline and the second voltage on the second bitline.

Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.

Abstract: A method of generating a high differential read current through a non-volatile memory, includes receiving a voltage read input from a word line voltage generator, outputting a first current to a bit line true (BLT), outputting a second current to a bit line complement (BLC), and generating the high differential read current through a difference between the first current and the second current.

Abstract: Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of bit lines, a plurality of word lines and a plurality of memory cells, each memory cell is coupled to an associated bit line and an associated word line; a second region including a plurality of sense amplifiers, each sense amplifier includes a sense node and a column selection switch coupled to the sense node; a third region including a plurality of bleeder circuits, and disposed between the first and second regions; and a plurality of column selection lines. Each bit line from the first region to the second region is coupled to the sense node of an associated one of the plurality of sense amplifiers, and each column selection line from the column selection switch is coupled to an associated bleeder circuit.

Abstract: An internal combustion engine includes a cylinder block defining first and second cylinders, and a cylinder head coupled to the block. The engine also includes a passage having a first outlet and a second outlet for exhausting post-combustion gasses from the cylinder head. The engine additionally includes a mechanism for selectively activating and deactivating the first cylinder and a turbocharging system having a low-flow turbocharger and a high-flow turbocharger. The low-flow turbocharger is driven by gasses from the first outlet and the high-flow turbocharger is driven by gasses from the second outlet. The turbocharging system also includes a first flow-control device that directs the gasses via the first and second outlets to the turbochargers when the first and second cylinders are activated. The first flow-control device also directs the gasses via the first outlet only to the low-flow turbocharger and blocks the second outlet when the first cylinder is deactivated.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

Abstract: In one embodiment, the method includes determining whether a selection transistor of a currently programmed memory string in the memory has deteriorated, and copying data in the currently programmed memory string to a different memory string of the memory if the determining determines the selection transistor has deteriorated.

Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.

Abstract: A pre-driver includes a first inverter, a second inverter, an amplifier, a first capacitor, and a second capacitor. The first inverter has an input terminal for receiving an input signal at an input node, and an output terminal coupled to an inner node. The second inverter has an input terminal coupled to the inner node, and an output terminal for outputting an output signal at an output node. The amplifier is configured to amplify the input signal by a gain factor so as to generate an amplified signal and an inverted amplified signal. The first capacitor has a first terminal coupled to the output node, and a second terminal for receiving the amplified signal. The second capacitor has a first terminal coupled to the inner node, and a second terminal for receiving the inverted amplified signal.

Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: A memory device and a method for forming a memory device are disclosed. The memory device includes a memory cell having a storage unit coupled to a cell selector unit. The storage unit includes first and second storage elements. Each of the first and second storage elements includes first and second terminals. The second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL). The cell selector unit includes first and second selectors. The first selector includes a write select transistor (TW) and the second selector includes a first read transistor (TR1) and a second read transistor (TR2). The first selector is coupled to a word line (WL) for selectively coupling a write path to the storage unit and the second selector is coupled to a read line (RL) for selectively coupling a read path to the storage unit.

Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

Abstract: Various implementations described herein may refer to and may be directed to non-discharging read-only memory cells. For instance, in one implementation, an integrated circuit may include a read-only memory (ROM) array including a plurality of ROM cells arranged into a column, where the column is disposed proximate to a bit line and to a reference voltage line. The plurality of ROM cells arranged into the column may include a plurality of non-discharging ROM cells positioned adjacently to one another, where each non-discharging ROM cell has a source terminal, a drain terminal, or both coupled to at least one adjacent non-discharging ROM cell. In addition, the plurality of non-discharging ROM cells may be coupled to the bit line using two or fewer connections.

Abstract: According to example embodiments, an electronic device includes channel layer including a graphene layer electrically contacting a quantum dot layer including a plurality of quantum dots, a first electrode and a second electrode electrically connected to the channel layer, respectively, and a gate electrode configured to control an electric current between the first electrode and the second electrode via the channel layer. A gate insulating layer may be between the gate electrode and the channel layer.

Abstract: According to one embodiment, a semiconductor storage device includes memory cell array including a memory cell, a bit line coupled to the memory cell, a sense circuit coupled to the bit line and being capable of charging the bit line, and a charging circuit, the memory cell array being disposed between the sense circuit and the charging circuit and being capable of charging the bit line.

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

Abstract: A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. The first following gate transistor has a first terminal coupled to the second terminal of the first select transistor, a second terminal, and a gate terminal coupled to a following control line. The antifuse transistor has a first terminal coupled to the second terminal of the first following gate, and a gate terminal coupled to an antifuse control line. The second following gate transistor and the second select transistor are disposed symmetrically to the first following gate transistor and the second select transistor with respect to the antifuse transistor.

Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of memory driver circuitry using a voltage translation capacitor. One embodiment is high speed level translation memory driver apparatus comprising a plurality of field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) logic gates to drive the FETs, and a voltage translation capacitor with a first terminal of the voltage translation capacitor connected to an output of a second CMOS logic gate and a second terminal of the voltage translation capacitor connected to a gate terminal of a first P-type FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Abstract: An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each including, connected to a source line (SL), a series connection (in any order) of a selection element (e.g., transistor gated by word line WL), a resistive storage element (e.g., MTJ), and a permanent connection to one of the bit lines (e.g., BL0, BL1). The apparatus may also include a ROM sense amplifier which is configured to precharge two output nodes connected to respective ones of the bit lines, so that the jumper in a selected memory cell pulls one of the output nodes to a first reference potential (e.g., GND) and the ROM sense amplifier pulls the other of the output nodes to a second reference potential (e.g., Vdd).

Abstract: A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.

Abstract: An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.

Abstract: A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.