Circuit for the generation of a scanning clock in an operational analysis device of the serial type for an integrated circuit

The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

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Claims

1. A circuit for the generation of a scanning clock in a serial operational analysis device for an integrated circuit, comprising a first switching means which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with said system clock, means for clamping said first switching means responsive to a firing signal of said serial operational analysis device which determines the clamping of the state of the machine clock and second switching means which receives at its input said system clock and is responsive to said firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

2. A circuit according to claim 1, wherein said first switching means comprises a first and a second amplifier stage with inputs coupled to receive the system clock, each followed by a respective inverter stage, and said clamping means is comprised of a switching stage, operated by the trailing edge of said firing signal of the serial operational analysis device which sets said switching stage in a closed position for allowing the passage through it to the system clock for the generation of the machine clock and is further responsive to the leading edge of said firing signal of the serial operational analysis device which sets said switching stage in an open position in which clamping of the state of the machine clock takes place.

3. A circuit according to claim 2, further comprising a feedback stage coupled between the output of said switching stage and the input of said second amplifier stage wherein said feedback stage prevents the production of spurious signals during the switching operation of said switching stage to the open position.

4. A circuit according to claim 2, further comprising a latch circuit coupled between the output of said second amplifier stage and the input of said switching stage which during the switching operation of said switching stage to the open position prevents the second amplifier stage from going into oscillation which would give rise to energy losses..Iadd.

5. A circuit for generating a scanning clock, comprising:

a first switch circuit operable to receive a system clock and a firing signal, said first switch circuit operable to generate a machine clock when said firing signal is in a first firing state and to clamp said machine clock in a first or second machine state when said firing signal is in a second firing state; and
a second switch circuit operable to receive said system clock, said firing signal, and said machine clock, said second switch circuit operable to generate said scanning clock when said firing signal is in said second firing state, said scanning clock substantially noninverted with respect to said system clock when said machine clock is in said first machine state and substantially inverted with respect to said system clock when said machine clock is in said second machine state..Iaddend..Iadd.6. The circuit of claim 5 wherein said first switch circuit comprises a switching stage operable to receive said system clock and said firing signal, and to close and open when said firing signal is in said first and second firing states respectively..Iaddend..Iadd.7. The circuit of claim 5 wherein said first switch circuit comprises a switching stage operable to receive said system clock, to receive said firing signal, and to close when said firing signal is in said first firing state and to open when said firing signal

is in said second firing state..Iaddend..Iadd.8. The circuit of claim 7 wherein said first switch circuit further comprises an amplifier operable to receive an output clock from said switching stage and to generate said machine clock from said output clock..Iaddend..Iadd.9. The circuit of claim 7 wherein said first switch circuit further comprises one or more serially coupled amplifiers interposed between said system clock and said switching stage..Iaddend..Iadd.10. The circuit of claim 5 wherein said second switch circuit comprises:

a first path operable to receive and invert said system clock to generate said scanning clock when said firing signal is in said second firing state and said machine clock is in said second machine state; and
a second path operable to receive and pass through said system clock to generate said scanning clock when said firing signal is in said second firing state and said machine clock is in said first machine state..Iaddend..Iadd.11. The circuit of claim 10 wherein said second switch circuit comprises:
a first switch serially coupled to said first path;
a second switch serially coupled to said second path;
a first enable circuit operable to close said first switch when said firing signal is in a second firing state and said machine clock is clamped in said second machine state; and
a second enable circuit operable to close said second switch when said firing signal is in a second firing state and said machine clock is clamped in said first machine state..Iaddend..Iadd.12. The circuit of claim 5 wherein said first switch circuit further comprises a feed back circuit operable to uncouple said system clock from said first switch circuit when said firing signal is in said second firing state.

.Iaddend..Iadd.13. A circuit, comprising:

a first circuit for generating a machine clock from a system clock, said first circuit including,
an input terminal coupled to receive said system clock,
an output terminal that provides said machine clock,
a switching stage having input and output terminals, and having a control terminal coupled to receive a firing signal that closes and opens said stage when in a first and a second state respectively,
one or more amplifier stages each having input and output terminals and serially coupled between said input terminals of said first circuit and said switching stage, and
a latching stage coupled between said output terminals of said switching stage and said first circuit; and
a second circuit for generating a scanning clock from said system clock, said second circuit including,
an input terminal coupled to receive said system clock,
an output terminal that provides said scanning clock,
a first path coupled between said input and output terminals of said second circuit, said first path including a first switch having a control terminal,
a second path coupled between said input and output terminals of said second circuit, said second path including a second switch having a control terminal,
a first enable circuit having a first input terminal coupled to said output terminal of said first circuit, a second input terminal coupled to receive said firing signal, and an output terminal coupled to said control terminal of said first switch, and
a second enable circuit having a first input terminal coupled to said output terminal of said first circuit, a second input terminal coupled to receive said firing signal, and an output terminal coupled to said control terminal of said second switch..Iaddend..Iadd.14. The circuit of claim 13 wherein one or more of said amplifier stages comprise inverters.

.Iaddend..Iadd.15. The circuit of claim 13 further comprising:

a test terminal that receives a test signal; and
a third enable circuit interposed between said system clock and said input terminal of said second circuit, said third enable circuit including a first input terminal coupled to said test terminal, a second input terminal coupled to receive said system clock, and an output terminal coupled to said input terminal of said second circuit..Iaddend..Iadd.16. The circuit of claim 13 wherein said third enable circuit comprises a NAND gate..Iaddend..Iadd.17. The circuit of claim 13 wherein said second path includes an odd number of inverters serially coupled to said second switch..Iaddend..Iadd.18. The circuit of claim 13 wherein said first and second enable circuits each comprise a NOR gate..Iaddend..Iadd.19. The circuit of claim 18 wherein said first enable circuit comprises an inverter coupled between said first input terminal of said first enable circuit gate and a corresponding input terminal of said NOR gate..Iaddend..Iadd.20. The circuit of claim 13 wherein said input terminal of said second circuit is coupled to an output of one of said amplifier stages..Iaddend..Iadd.21. The circuit of claim 13 wherein said first circuit further comprises a feed-back circuit coupled between said output terminal of said first circuit and a disable terminal of one of said amplifier stages..Iaddend..Iadd.22. A method for generating a scanning clock, comprising:
generating a machine clock from a system clock when a firing signal is in a first firing state;
clamping said machine clock in a first or second machine-clock state when said firing signal is in a second firing state;
generating said scanning clock substantially coincident with said system clock when said machine clock is clamped in said first machine-clock state; and
generating said scanning clock substantially inverted with respect to said system clock when said machine clock is clamped in said second

machine-clock state..Iaddend..Iadd.23. The method of claim 22 wherein:

said generating a machine clock includes closing a switch that receives said system clock when said firing signal is in said first firing state; and
said clamping includes opening said switch when said firing signal is in said second firing state..Iaddend..Iadd.24. The method of claim 23 further comprising uncoupling said system clock from said switch when said firing signal is in said second firing state..Iaddend..Iadd.25. The method of claim 22 wherein:
said generating a machine clock includes closing a switch that receives said system clock when said firing signal is in said first firing state; and
said clamping includes opening said switch and latching said machine clock in its present state when said firing signal is in said second firing state..Iaddend..Iadd.26. The method of claim 22 wherein:
said generating a machine clock includes, when said firing signal is in said first firing state, coupling said system clock to an amplifier stage that generates said machine clock; and
said clamping includes uncoupling said system clock from said amplifier stage when said firing signal is in said second firing state.

.Iaddend..Iadd.27. The method of claim 22 wherein:

said generating a machine clock includes coupling said system clock to an amplifier stage when said firing signal is in said first firing state; and
said clamping includes, when said firing signal is in said second firing state, uncoupling said system clock from said amplifier stage and holding in said amplifier stage the state of said machine clock when said firing signal transitioned from said first to said second firing state..Iaddend..Iadd.28. An integrated circuit, comprising:
one or more functional blocks;
one or more serially coupled input chains operable to propagate an input scanning signal from an input of a first cell to an output of a last cell, each of said input chains coupled to an associated one of said blocks and a scanning clock;
one or more serially coupled output chains operable to propagate an output scanning signal from an input of a first cell to an output of a last cell, each of said output chains coupled to an associated one of said blocks and said scanning clock; and
a scanning-clock generator, including,
a first switch circuit having an input terminal operable to receive a system clock, an output terminal, and a control terminal operable to receive a firing signal, said first switch circuit operable to generate a machine clock on said output terminal when said firing signal is in a first firing state and to clamp said machine clock in a first or second machine state when said firing signal is in a second firing state; and
a second switch circuit having an input terminal operable to receive said system clock, a first control terminal operable to receive said firing signal, a second control terminal coupled to said output terminal of said first switch circuit, and an output terminal, said second switch circuit operable to generate said scanning clock on said output terminal when said firing signal is in said second firing state, said scanning clock substantially noninverted with respect to said system clock when said machine clock is in said first machine state and substantially inverted with respect to said system clock when said machine clock is in said

second machine state..Iaddend..Iadd.29. The circuit of claim 28 wherein said first switch circuit further comprises a switching stage having control, input, and output terminals respectively coupled to said control, input, and output terminals of said first switch circuit, said switching stage operable to close and open when said firing signal is in said first and second firing states respectively..Iaddend..Iadd.30. The circuit of claim 29 wherein said first switch circuit further comprises one or more inverters interposed between said input terminals of said first switch circuit and said switching stage..Iaddend..Iadd.31. The circuit of claim 29 wherein said first switch circuit further comprises one or more amplifier stages interposed between said input terminals of said first switch circuit and said switching stage..Iaddend..Iadd.32. The circuit of claim 31 wherein said first switch circuit further comprises a feedback circuit coupled between said output terminal of said first switch circuit and a disable input of one of said amplifier stages..Iaddend..Iadd.33. The circuit of claim 30 wherein said first switch circuit further comprises a latch interposed between said output terminals of said switching stage and said first switch circuit..Iaddend..Iadd.34. The circuit of claim 28 wherein said second switch circuit further comprises:

a first path coupled between said input and output terminals of said second switch circuit and including a first switching stage having a control terminal;
a second path coupled between said input and output terminals of said second switch circuit and including a second switching stage having a control terminal;
a first enable circuit having input terminals coupled to said output terminal of said first switch circuit and to said firing signal respectively and having an output terminal coupled to said control terminal of said first switching stage; and
a second enable circuit having input terminals coupled to said output terminal of said first switch circuit and to said firing signal respectively, and having an output terminal coupled to said control

terminal of said second switching stage..Iaddend..Iadd.35. The circuit of claim 34 wherein said second path includes an odd number of inverters in series with said second switching stage..Iaddend..Iadd.36. The circuit of claim 34 wherein said first and second enable circuits each comprise a NOR gate..Iaddend..Iadd.37. The circuit of claim 36 wherein said first enable circuit comprises an inverter coupled between an input terminal of said NOR gate and said input terminal of said first enable circuit that is coupled to said output terminal of said first switch circuit..Iaddend.

Referenced Cited
U.S. Patent Documents
4245349 January 13, 1981 Kumaoka et al.
4308472 December 29, 1981 McLaughlin
4441182 April 3, 1984 Best et al.
4493077 January 8, 1985 Agrawal et al.
4613773 September 23, 1986 Koike
4627085 December 2, 1986 Yuen
4649539 March 10, 1987 Crain et al.
4701920 October 20, 1987 Resnick et al.
4710933 December 1, 1987 Powell et al.
4922138 May 1, 1990 Hashimoto et al.
5045776 September 3, 1991 Claridge
5225724 July 6, 1993 Scarra et al.
Foreign Patent Documents
3 106 183 September 1982 DEX
2 188 504 September 1987 GBX
2 192 106 December 1987 GBX
Other references
  • "LSSD Compatible Non-Overlapping Clock Splitter," IBM Technical Bulletin, vol. 31, No. 4: Sep. 1988.
Patent History
Patent number: RE36123
Type: Grant
Filed: Jun 15, 1995
Date of Patent: Mar 2, 1999
Assignee: SGS-Thomson Microelectronics S.r.L. (Agrate Brianza)
Inventors: Flavio Scarra (San Diego, CA), Maurizio Gaibotti (Cesano Madero), Giampiero Trupia (Carnate)
Primary Examiner: Edward P. Westin
Assistant Examiner: Richard Roseen
Attorneys: David V. Carlson, Bryan A. Seed and Berry LLP Santarelli
Application Number: 8/492,462
Classifications
Current U.S. Class: Plural Outputs (327/295); Clocking Or Synchronizing Of Logic Stages Or Gates (326/93)
International Classification: H03K 19096;