Isolation region fabrication for replacement gate processing
A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
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This is an application for reissue of U.S. Pat. No. 8,643,109, and is a continuation of application Ser. No. 15/015,546, which is also an application for reissue of U.S. Pat. No. 8,643,109, which application is a divisional of U.S. application Ser. No. 13/213,713, filed on Aug. 19, 2011, which is herein incorporated by reference in its entirety.
BACKGROUNDThis disclosure relates generally to the field of integrated circuit (IC) manufacturing, and more specifically to isolation region fabrication for electrical isolation between semiconductor devices on an IC.
ICs are formed by connecting isolated active devices, which may include semiconductor devices such as field effect transistors (FETs), through specific electrical connection paths to form logic or memory circuits. Therefore, electrical isolation between active devices is important in IC fabrication. Isolation of FETs from one another is usually provided by shallow trench isolation (STI) regions located between active silicon islands. An STI region may be formed by forming a trench in the substrate between the active devices by etching, and then filling the trench with an insulating material, such as an oxide. After the STI trench is filled with the insulating material, the surface profile of the STI region may be planarized by, for example, chemical mechanical polishing (CMP).
However, use of raised (or regrown) source/drain structures, which may be employed to achieve lower series resistances of the IC or to strain FET channels, may exhibit significant growth non-uniformities at the boundary between a gate and an STI region, or when the opening in which the source/drain structure is formed is of variable dimensions. This results in increased variability in FET threshold voltage (Vt), delay, and leakage, which in turn degrades over-all product performance and power. One solution to such boundary non-uniformity is to require all STI regions to be bounded by isolation regions. However, inclusion of such isolation region structures may limit space available for wiring, device density, and increase the load capacitance, thereby increasing switching power of the IC.
BRIEF SUMMARYIn one aspect, a semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.
Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.
Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:
Embodiments of a method for isolation region fabrication for replacement gate processing, and an IC including isolation regions, are provided, with exemplary embodiments being discussed below in detail. Instead of placing isolation regions at STI region boundaries, isolation regions may replace STI regions, as is described in U.S. patent application Ser. No. 12/951,575 (Anderson et al.), filed Nov. 22, 2010, which is herein incorporated by reference in its entirety. A relatively dense, low-capacitance IC may be formed by replacement gate (i.e., gate-last) processing through use of a block mask that selectively allows removal of active silicon in a gate opening to form an isolation region. The active silicon is removed in a manner that is self-aligned to the dummy gate, such that there is no overlap of gate to active area and hence minimal capacitance penalty.
Returning to method 100, in block 102, a block mask is applied to the top surface of the dummy gates and the ILD, and the block mask is patterned to selectively expose the dummy gates that are to become isolation regions. The block mask may comprise, for example, photoresist.
Next, in method 100 of
Lastly, in block 106 of method 100 of
The technical effects and benefits of exemplary embodiments include formation of an IC having relatively high device density and low capacitance through replacement gate processing.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims
1. A semiconductor structure, comprising:
- a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer;
- a plurality of active devices formed on the top silicon layer; and
- an isolation region located between two of the plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends through the top silicon layer to the BOX layer, wherein the isolation region further extends between a pair of spacers that are located on the top silicon layer on either side of the isolation region, and wherein the isolation region further extends through an interlevel dielectric (ILD) layer that is located over the pair of spacers.
2. The semiconductor structure of claim 1, further comprising a hardmask layer located over the isolation region.
3. The semiconductor structure of claim 2, wherein the hardmask layer comprises silicon nitride.
4. A semiconductor device comprising:
- a substrate including a top silicon layer that includes a fin;
- a first gate structure disposed on the fin;
- a second gate structure disposed on the fin;
- an isolation region disposed between the first gate structure and the second gate structure;
- a first spacer disposed on a first side of the isolation region and disposed on the top silicon layer;
- a second spacer disposed on a second side of the isolation region and disposed on the top silicon layer; and
- an interlevel dielectric (ILD) layer disposed on the first spacer and the second spacer,
- wherein the isolation region extends between the first spacer and the second spacer, and
- wherein the isolation region extends through the ILD layer that is disposed on the first spacer and the second spacer.
5. The semiconductor device of claim 4, wherein the isolation region includes silicon nitride.
6. The semiconductor device of claim 4, wherein the isolation region is disposed below a silicon nitride layer.
7. The semiconductor device of claim 4, wherein the isolation region electrically isolates the first gate structure from the second gate structure.
8. The semiconductor device of claim 4, further comprising source/drain regions disposed on the substrate, disposed on sides of the first and second gate structures, and disposed below the first and second spacers.
9. The semiconductor device of claim 4, wherein the substrate is a silicon-on-insulator substrate.
10. The semiconductor device of claim 4, wherein a top surface of the isolation region is planarized.
11. The semiconductor device of claim 4, further comprising channels disposed below the first gate structure and the second gate structure.
12. The semiconductor device of claim 4, wherein the isolation region extends through the ILD layer in a direction that is substantially parallel with respect to a top surface of the substrate.
13. The semiconductor device of claim 4, wherein the isolation region extends through the ILD layer in a direction that is substantially perpendicular with respect to a top surface of the substrate.
14. The semiconductor device of claim 4, wherein the ILD layer is disposed on a sidewall of the first spacer and on a sidewall of the second spacer.
15. The semiconductor device of claim 4, wherein the ILD layer is disposed on a top surface of the first spacer and on a top surface of the second spacer.
16. The semiconductor device of claim 4, wherein the isolation region contacts the ILD layer.
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Type: Grant
Filed: Jun 19, 2017
Date of Patent: Jun 29, 2021
Assignee: SAMSUNG ELECTRONICS CO., LTD. (Suwon-si)
Inventors: Brent A. Anderson (Jericho, VT), Edward J. Nowak (Shelburne, VT)
Primary Examiner: Tuan H Nguyen
Application Number: 15/626,876
International Classification: H01L 27/12 (20060101); H01L 29/66 (20060101); H01L 21/28 (20060101); H01L 21/84 (20060101); H01L 21/762 (20060101);