Abstract: Disclosed is an inventive diode which can reduce a stray capacity to improve various characteristics thereof, in which a dielectric layer, a conductive layer and a second dielectric layer are respectively formed by deposition in this order on an upper face of a semiconductor substrate excluding a central portion of an exposed surface of a P-type region. Then, an anode side electrode is formed extending from the exposed surface of the P-type region to the upper face of the second dielectric layer, and is electrically connected with the P-type region. Herein, the conductive layer is formed such that it is isolated from the electrode by the second dielectric layer, is connected with the semiconductor substrate upper face in a location where the dielectric layer has not been formed, and partially resides in a location sandwiched between the electrode and the semiconductor substrate.

Abstract: A semiconductor light emitting device has a blue LED and a green LED which each have a protection circuit connected in parallel thereto. The protection circuit has two Zener diodes that are connected in series in opposite directions to each other. When an AC voltage below a breakdown voltage of the protection circuit is applied to the semiconductor light emitting device and when the voltage is in forward direction, a current passes through the blue and green LEDs to emit lights. A current is intercepted by the protection circuit when the voltage is in reverse direction. When an high AC voltage above a breakdown voltage of the protection circuit is applied, a current passes through the protection circuit whether the current in forward direction or in reverse direction, so that the green and blue LEDs are protected. Even when the semiconductor light emitting devices are connected to one another in a matrix form and subject to dynamic driving, a leakage current is intercepted by the protection circuits.

Abstract: Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines and function as a filter. As a result, noise generated by operation of internal circuit is absorbed in propagating to stabilize circuit through first internal power supply line, pad, and second internal power supply line. Therefore, effects of noise given to stabilize circuit is small.

Abstract: A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at least the polysilicon film, and by nitriding at least the surface portion of the oxide film, a nitride oxide film is formed on each side face of the gate electrodes. An interlayer insulating film is then deposited, and contact holes are formed through the interlayer insulating film. The existence of the nitride oxide film suppresses variation and reduction in size due to oxidation and etching of the gate side faces during resist removal and washing.

Abstract: An embedded LSI includes a FeRAM macro block and an associated logic circuit section. A hydrogen barrier layer covers the FeRAM macro block as a whole and exposes the logic circuit section. The edge of the hydrogen barrier layer overlies the peripheral circuit of the FeRAM macro block and the boundary separating the FeRAM macro block from the logic circuit section. The ferroelectric capacitor is protected by the hydrogen barrier layer against hydrogen during a hydrogen-annealing process.

Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.

Abstract: A memory cell has a cylindrical electrode having a porous cylindrical portion, and insulating layers for making less steep the height of cylindrical electrode are provided in the peripheral circuit region. Thus a semiconductor memory device and manufacturing method thereof can be provided in which the step between the memory cell array region and the peripheral circuit region can be made less steep by a smaller number of manufacturing steps.

Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.

Abstract: At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.

Abstract: The present invention relates to a pressure sensor comprising a capacitor with a first capacitor pole element (1) and at least one additional capacitor pole element (3) arranged at a distance from one another. In accordance with the invention, at least one capacitor pole element (1, 3) has at least one textured region (31, 31′ and/or 32, 32′) on the surface of its conductive components facing toward the other capacitor pole element (3, 1), and the distance between the two capacitor pole elements (1,3) is different in the textured region (31,31′ and/or 32; 32′) than in an adjacent region (32, 32′ and/or 31, 31′) to the textured region (31; 31′ and/or 32,32′). The difference between these two different distances can be changed—more particularly, reduced—by deformation of at least one capacitor pole element (1,3) when the capacitor is subjected to pressure.

Abstract: A semiconductor device includes an interlevel insulating film, a contact plug, a barrier film, a first electrode, a capacitor insulating file, and a second electrode. The interlevel insulating film is formed on a semiconductor substrate. The contact plug extends through the interlevel insulating film and is formed from a conductive material. The barrier film is formed from a tungsten-based material on the upper surface of the contact plug. The first electrode is connected to the contact plug via the barrier film and formed from a metal material on the interlevel insulating film. The capacitor insulating film is formed from an insulating metal oxide on the first electrode. The second electrode is insulated by the capacitor insulating film and formed on the surface of the first electrode.

Abstract: A memory cell assembly includes a substrate, a first electrode, and a second electrode layer. The first electrode is disposed over the substrate and the second electrode layer is disposed over the first electrode. The second electrode layer includes two or more second electrodes. Dielectric material separates the first electrode form the second electrodes and also separates the second electrodes. Each second electrode forms an individual memory cell associated with the first electrode. The memory cell assembly can be made by, first, forming a first electrode over a substrate. A second electrode layer is formed over the first electrode. The second electrode layer includes two or more second electrodes. A dielectric material is formed between the first electrode and the second electrodes and between the second electrodes.

Abstract: A new capacitor structure of a Flash memory (Flash) cells on a supporting substrate's existing topography, including existing topography provided by adjacent word lines is provided. The gate of the Flash memory cell is constructed as an integral part of the new capacitor cell structure. An increased capacitive coupling ratio is achieved whereby reduced programming voltage is required while yielding more a more compact memory cell structure. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.

Abstract: A gate electrode of a field-effect transistor used as a peripheral circuit is constituted by the same gate electrode structure as a double-level gate electrode structure of nonvolatile memory cells, and a contact hole for connecting those conductive films constituting the gate electrode is provided at a location which two-dimensionally overlaps an active area within a plane of the gate electrode.

Abstract: An insulated gate bipolar transistor (IGBT) and a method for manufacturing the same is provided. This method is capable of preventing a latch-up and improving a short current characteristic. In the IGBT, a second conductive type semiconductor layer is formed over a semiconductor substrate. A first conductive type well is then formed beneath the surface of the semiconductor layer, and a second conductive type source region doped with a high concentration is formed in the well. Also, a gate electrode is formed over the semiconductor layer, but so as not to contact the source region in a region in which a contact between the source region and a cathode electrode is formed. Also, the IGBT further includes an impurity region for controlling latch-up, the impurity region being extended to a part of the semiconductor layer via the well.

Abstract: A field-effect semiconductor device, for example a MOSFET of the trench-gate type, comprises side-by-side device cells at a surface (10a) of a semiconductor body (10), and at least one drain connection (41) that extends in a drain trench (40) from the body surface (10a) to an underlying drain region (14a). A channel-accommodating region (15) of the device extends laterally to the drain trench (40). The drain trench (40) extends through the thickness of the channel-accommodating region (15) to the underlying drain region (14a), and the drain connection (41) is separated from the channel-accommodating region (15) by an intermediate insulating layer (24) on side-walls of the drain trench (40). A compact cellular layout can be achieved, with a significant proportion of the total cellular layout area accommodating conduction channels (12). The configuration in a discrete device avoids a need to use a substrate conduction path and so advantageously reduces the ON resistance of the device.

Abstract: Provides a semiconductor device that can separate components easily. Gate electrode 42 is formed only within component forming region 32, and gate electrode 42 and aluminum wiring 48 are connected in component forming region 32. Therefore, there is almost no inversion of the surface of the semiconductor substrate 36 that is under field oxide film 38 due to the voltage of the concerned connection area and gate electrode 42. Also, there is interlayer film 44 between aluminum wiring 48 and field oxide film 38, so there is almost no inversion of the surface of the semiconductor substrate 36 that is under field oxide film 38 due to the voltage of aluminum wiring 48. Therefore, it is possible to separate components without increasing overall length L1 of field oxide film 38, increasing the film thickness of field oxide film 38, or increasing the concentration of channel stop ions implanted into the surface of the semiconductor substrate 36 that is under field oxide film 38.

Abstract: A step-like silicon on isolation (SOI) structure has a substrate, wherein isolation structures are located within the substrate and an active region is located between the isolation structures; a pair of source/drain regions formed within the active region; a channel region located between the source/drain regions and within the substrate; a gate structure located on the channel region and above the substrate; and a buried insulator layer located below the source/drain regions and the channel region, wherein the buried insulator layer is substantially conformal to the source/drain regions and the channel region and has a step-like profile.

Abstract: An integrated circuit and process for making the same is provided in which a transistor including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, the gate dielectric is formed from a transition metal oxide. Preferably, the transition metal oxide is formed by oxidation of a transition metal spacer. The transition metal spacer may be reduced, prior to oxidation such that a later extent of the spacer is substantially less than a lateral extent of the gate conductor.

Abstract: The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: In one aspect, the invention provides semiconductor sensor which includes a first single crystal silicon wafer layer. A single crystal silicon structure is formed in the first wafer layer. The structure includes two oppositely disposed substantially vertical major surfaces and two oppositely disposed generally horizontal minor surfaces. The aspect ratio of major surface to minor surface is at least 5:1. A carrier which includes a recessed region is secured to the first wafer layer such that said structure is suspended opposite the recessed region.

Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle &thgr; on the active region. The boundary between the element-isolating region and the active region intersects the gate electrode so that the line segments of the boundary at which said intersection takes place, are approximately parallel to the bisector of the bent-angle &thgr; of the bent portion of the gate electrode. In this semiconductor device, the variation in width of gate electrode is small and accordingly the variation in properties is small, even when the relative position of gate electrode and active region of MOSFET has shifted slightly.

Abstract: An integrated circuit configuration includes a structure, a p-n junction, and a defect plane disposed such that each of a plurality of straight lines, that intersect or touch the structure and the p-n junction, intersect the defect plane. This prevents unwanted leakage currents through the p-n junction and increases a retention time in a DRAM cell configuration. A wafer configuration and a method of producing an integrated circuit configuration are also provided.

Abstract: Certain embodiments relate to a microwave monolithic integrated circuit using a silicon substrate in which parasitic capacitances between inductors and a silicon substrate are sufficiently reduced. A semiconductor device may include a silicon substrate 1, a CMOSFET 200 formed on the silicon substrate 1, and an inductor 100 formed over the silicon substrate 1 through an insulation layer 50. A through hole 300 is formed in the silicon substrate 1 in a portion below the inductor 100.

Abstract: A vertical semiconductor component having a semiconductor body of a first conductivity type is described. In a surface region of the semiconductor body, at least one zone of a second conductivity type, opposite to the first conductivity type, is embedded. Regions of the second conductivity type are provided in the semiconductor body in a plane running substantially parallel to the surface of the surface region. The regions are in this case sufficiently highly doped that they cannot be depleted of charge carriers when a voltage is applied.

Abstract: An electron emitting apparatus that can realize a convergence of electron trajectories and an improved electron emission efficiency. The apparatus comprises a substrate having a first primary surface that is substantially planar, an electron emitting device comprising first and second electroconductive members disposed on the primary surface and at an interval from one another, and an anode electrode having a substantially planar surface opposite to the first primary surface. A voltage applying means of the apparatus applies a potential higher than a potential applied to the first electroconductive member to the second electroconductive member to irradiate electrons emitted from the electron emitting device onto the anode electrode.

Abstract: In a semiconductor device, a bus bar (4a) is provided with a projection (9a). Based on a positional relationship between the projection and a metal wire (13a) subjected to the lateral deflection upon resin filling, the metal wire lateral deflection amount is managed. The projection may be provided on a suspension pin or at another portion of a lead frame. A cutout may be provided instead of the projection.

Abstract: A re-wiring layer is provided on a circuit-formed surface of an IC chip, in an area other than where external lead electrodes. In the process for forming a circuit of the IC chip, the re-wiring layer is formed in a step following to a circuit forming step, and the re-wiring layer formation is executed as a part of the IC chip fabrication process. The re-wiring layer is provided with first electrode pads on a chip periphery, second electrode pads at positions closer to the IC chip than the positions of the first electrode pads are, and wires for connecting the first electrode pads with the second electrode pads according to the 1:1 correspondence therebetween. By so doing, it is possible to provide a semiconductor device that allows the number of possible combinations of sizes of the laminated semiconductor chips to increase, while ensuring that an increase in the package cost, an increase in the thickness of the package, and deterioration of the package production efficiency should be suppressed.

Abstract: In order to suppress the warp of a semiconductor package of an over-coat structure, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are &agr;s, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are &agr;r, Er and Hr, respectively, the value R of (&agr;r·Er·Hr)/(&agr;s·Es·Hs) is set to be approximately 0.6 or more. With adoption of such a configuration, stress exerting on a semiconductor package can be effectively alleviated, and coplanarity of the semiconductor package can be improved.

Abstract: A method for manufacturing a chip scale package includes: providing a redistribution substrate; attaching a semiconductor wafer to the redistribution substrate; forming external terminals on the redistribution substrate; and separating the semiconductor wafer and the redistribution substrate into individual integrated circuits. The method can further include forming a buffer layer by filling a gap between the semiconductor wafer and the redistribution substrate with a dielectric material. Another method is the same as the method described above except that instead of the semiconductor wafer, individual integrated circuit chips attach to the redistribution substrate.

Abstract: A solid-state image pickup apparatus having hermetic seal portion capable of packaged in a smaller size by a simple construction and fabricated with high precision at wafer level is constructed such that an epoxy-type resin sheet having opening portion only at light-receiving portion is adhered to solid-state image pickup device chip by an adhesive and a transparent member capable of becoming a flat-plate portion is adhered onto the epoxy-type resin sheet by means of an adhesive.

Abstract: A multilayer wiring structure is formed on a flat metal plate and then an entire surface of the metal plate is etched away to thereby leave only a multilayer wiring layer. An insulating substrate having through hole sections is bonded to the multilayer wiring layer, a conductive bonding agent is embedded into the through hole section, a semiconductor chip is mounted and a solder ball is coupled.

Abstract: A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract: A semiconductor device comprises a first wiring board and a second wiring board, wherein the first wiring board includes a first semiconductor element arranged on the underside of the first wiring board, and a second connecting section formed on the underside of the first wiring board, the second wiring board includes a second semiconductor element, and a third connecting section formed on the surface of the second wiring board, the second connecting section has a first external connecting land, the third connecting section is arranged opposite to the first external connecting land and has a second external connecting land which is smaller than the first external connecting land, and the second and third connecting sections are formed such that a combined thickness thereof provides a given space between the first semiconductor element and the second wiring board.

Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.

Abstract: A method of forming a solder film on a metallic surface such as a pad of a metallic circuit of a printed circuit board and a lead frame of electronic parts, which is capable of forming a precise and fine pattern and which comprises selectively imparting tackiness to only a predetermined part of the metallic surface by means of a tacky layer-forming solution containing at least one compound selected from benzotriazole derivatives, naphthotriazole derivatives, imidazole derivatives, benzoimidazole derivatives, mercaptobenzothiazole derivatives, benzothiazole thiofatty acid derivatives, and triazine derivatives, adhering a powdered solder to the resulting tacky part, and then melting the solder by heating to thereby form a solder film.

Abstract: A multi-layered metal bond pad for a semiconductor die having a conductive metal layer and an overlying ruthenium electrode layer. The ruthenium electrode layer protects the conductive metal from oxidation due to ambient environmental conditions. An interconnect structure such as a wire bond or solder ball may be attached to the ruthenium layer to connect the semiconductor die to a lead frame or circuit support structure. Also disclosed are processes for forming the ruthenium layer.

Abstract: Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device.

Abstract: One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads.

Abstract: A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

Abstract: A bond pad structure for use in wire bonding applications during the packaging of semiconductor devices which minimizes the bond pad lift-off problem to provide improved stability. The bond pad structure contains: (1) a dielectric layer 4 formed on a first conductive layer 5; (2) a base conductive layer (whose outer boundary as viewed from the top is indicated as line 11) formed in the dielectric layer on top of the first conductive layer, the base conductive being extended to form an overhang layer (whose outer boundary is shown as line 13) which is disposed above the dielectric layer; and (3) at least one recessed portion 20 formed in the overhang layer. In a preferred embodiment, the bond pad is rectangular in shape and the recessed portion has the shape of an elongated rim that covers two corners of the base conductive layer.

Abstract: A semiconductor wafer having dot mark groups which are excellent in optical visibility and which have a peculiar configuration indicating the orientation of a crystallographic axis and a method of specifying the orientation of a crystallographic axis by the dot mark groups are provided. After a plurality of marks in a dot shape a part of which rising from the wafer surface within the predetermined region of a semiconductor wafer are formed, a group of epitaxial growth dot marks in which s single crystal is formed on the entire surface of the foregoing semiconductor wafer by the epitaxial growth, and a group of non-epitaxial growth dot marks in which no or little epitaxial growth is formed are made. By extracting the dot mark which is most excellent in visibility in the foregoing group of non-epitaxial growth dot marks, the orientation of a crystallographic axis is spsecified from this dot mark and the wafer center.

Abstract: An elongated apparatus is provided for aerating water, and includes a tubular support body and a sleeve of elastomeric material that surrounds the support body and is provided with slits that open to allow fine bubbles to pass into the water. To achieve a uniform supply of the sleeve with little loss for long apparatus, the inner side of the sleeve is provided with one or more groove-like channels that extend lengthwise relative to the sleeve.

Abstract: The present invention relates to a method for producing a shell for a Luneberg lens in which an amount of a dielectric material composition containing particles of an expandable plastic material coated with an amount of a titanium-oxygen compound, is introduced into a mould and heated to an appropriate temperature for moulding. As a plastic material use is made of an expandable plastic material which is non-expanded or partly pre-expanded. The moulding temperature is selected such that expansion of the particles takes place. As an expandable plastic material preferably use is made of polystyrene. The dielectric moulding composition preferably comprises 5-65 wt. % of the titanium-oxygen compound with respect to the total weight of the composition.

Abstract: A nozzle internal resin pressure feedback control system has a mold internal pressure sensor for measuring a mold internal resin pressure as a measured mold internal pressure value. The measured mold internal pressure value is fed to the nozzle internal resin pressure feedback control system, and a nozzle internal pressure preset value in the nozzle internal resin pressure feedback control system is changed in accordance with a difference between the measured mold internal pressure value and the mold internal pressure preset value.

Abstract: In a method for manufacturing electronic parts by laminating metal thin films and insulating thin films on a support, a mold releasing agent is applied to the support before the start of lamination. Alternatively, the mold releasing agent is applied to the surface of the laminate during the lamination step, and then lamination is resumed. Therefore, the laminate can be prevented from cracking when the laminate is separated from the support or divided into plural pieces in the lamination direction. Thus, the reliability and productivity of electronic parts improve.