Abstract: Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel effect. The impurity regions 104 allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.

Abstract: A method for fabricating a high voltage transistor includes the steps of: forming a plurality of drift regions on a semiconductor substrate of a first conductive type; implanting drift ions of a second conductive type into surfaces of the drift regions of the semiconductor substrate at a first depth; implanting drift ions of the second conductive type into the surfaces of the drift regions of the semiconductor substrate at a second depth deeper than the first depth; implanting first conductive channel stop ions into the semiconductor substrate thereby forming a space between the semiconductor substrate and the drift regions; forming a device isolation film on a surface of the semiconductor substrate into which the channel stop ions are implanted; forming a gate electrode by inserting a gate insulating film on the semiconductor substrate between the drift regions; and forming a source/drain impurity diffusion region of a second conductive type in the surface of the semiconductor substrate at both sides of the

Abstract: Alternative methods are provided for fabricating a hybrid isolation structure on a semiconductor substrate, wherein, the hybrid isolation structure includes a shallow trench isolation (STI) and a field oxide isolation formed by local oxidation of silicon (LOCOS). In detail, the STI is formed within a device region that is operated at a low working voltage, a logic device region, to efficiently enhance the device density. On the other hand, the LOCOS isolation is formed within a device region that is operated at a high working voltage, a memory device region, to ensure the reliability and performance of the devices.

Abstract: A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate.

Abstract: When fabricating an MIM capacitive circuit in which a lower electrode and an upper electrode confront each other through a capacitive film, the lower electrode composed of titanium nitride (TiN), which is a metal that is resistant to oxidation by sulfuric acid, is formed on a substrate, following which the surface of this lower electrode is cleaned with a solution containing sulfuric acid, preferably, dilute sulfuric acid. A capacitive film composed of the dielectric material tantalum oxide (Ta2O5) is then formed on the surface of the cleaned lower electrode, following which an upper electrode composed of the metal titanium nitride (TiN) is formed on the surface of the capacitive film. Cleaning with dilute sulfuric acid eliminates the presence of organic material or oxide material on the surface of the lower electrode, thereby preventing leakage current that is caused by these materials.

Abstract: This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.

Abstract: The invention relates to an improved substrate (100) using a layer (112) or region (130) of porous silicon that is created in the bulk silicon substrate material (110) to increase the resistivity of the substrate (100) thus making it suitable for passive component integration directly on the motherboard (200) or chip (230) and useful for high frequency applications due to its low loss, low dielectric properties. One or more passive components such as inductors (214), resistors (212) and capacitors (216) can be integrated on the device (140) over the porous silicon region (130). The high resistivity of the device makes it ideal for integration on a single platform using conventional wafer fab processes since loss at radio frequencies is comparably less when compared to a pure silicon substrate.

Abstract: A process for fabricating a tapered trench on a silicon substrate. The process comprises the steps of forming an initial trench in the substrate and implanting nitrogen ions on the initial trench side walls. More nitrogen ions are implanted adjacent the exposed surface of the substrate than adjacent the trench bottom. Finally, the initial trench side walls are oxidized to create the tapered shape.

Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

Abstract: A method of manufacturing a semiconductor device comprising semiconductor elements having semiconductor zones (17, 18, 24, 44, 45) formed in a top layer (4) of a silicon wafer (1) situated on a buried insulating layer (2). In this method, a first series of process steps are carried out, commonly referred to as front-end processing, wherein, inter alia, the silicon wafer is heated to temperatures above 700° C. Subsequently, trenches (25) are formed in the top layer, which extend as far as the buried insulating layer and do not intersect pn-junctions. After said trenches have been filled with insulating material (26, 29), the semiconductor device is completed in a second series of process steps, commonly referred to as back-end processing, wherein the temperature of the wafer does not exceed 400° C. The trenches are filled in a deposition process wherein the wafer is heated to a temperature which does not exceed 500° C.

Abstract: A method for forming a thermal silicon nitride on a semiconductor substrate is disclosed. This method allows formation of thermal silicon nitride that is thick enough for a FET gate dielectric, but has a low thermal budget.

Abstract: A method for setting the threshold voltage of a MOS transistor having a gate composed of polysilicon includes the step of implanting germanium ions into the gate composed of polysilicon in order to change the work function of the gate.

Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.

Abstract: An unprogrammed die is attached to a die package, and bond wires are attached between the die and lead fingers on the die package. A cavity in the die package allows the die to be configured, such as with a laser. The die is then tested and, if needed, etched to ensure the desired configuration. The die package is sealed, such as with a filler material or a lid to protect the configured die and bond wires. In one embodiment, the die and bond wires are fully exposed through the cavity. In another embodiment, only a minority portion of the bona wires are exposed through the cavity. The cavity can be formed either prior to or after attaching the die and bond wires to the die package.

Abstract: An electrical and thermal contact which includes an intermediate conductive layer, an insulator component, and a contact layer. The insulator component is fabricated from a thermally insulative material and may be sandwiched between the intermediate conductive layer and the contact layer. The electrical and thermal contact may be fabricated by forming a first thin layer on a surface of the semiconductor device, depositing a dielectric layer adjacent the first thin layer, patterning the dielectric layer to define the insulator component, forming a second thin layer adjacent the insulator component and in partial contact with the first thin layer. The first and second thin layers are respectively patterned to define the intermediate conductive layer and the contact layer. The electrical and thermal contact effectively contains heat within and prevents heat from dissipating from a contacted structure, such as a phase change component that may be switched between two or more electrical states.

Abstract: Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

Abstract: The invention relates to a semiconductor device comprising a substrate (1) comprising for instance silicon with thereon a layer (2, 4) comprising at least organic material which contains a passage (6, 8) to the substrate (1). The passage (6,8) has walls (7, 9) transverse to the layer (2, 4). A metal layer (11) is applied on the substrate (1) in at least that portion which adjoins the passage (8). The organic material forming the walls (7, 9) of the passage (6, 8) is covered with an oxide liner (12), and the passage (6, 8) is filled with a metal (14). According to the invention, a metal liner (13) comprising Ti or Ta is provided between the oxide liner (12) and the metal (14) filling the passage (6, 8). It is achieved by this that the device has a better barrier between the organic material (2, 4) and the interconnection metal (14) and that the organic material (2, 4) has a better protection during the various steps of the process.

Abstract: It is possible to obtain a semiconductor device in which a contact and a wiring provided on the contact can be electrically connected well even if a shift of superposition is caused. Sidewalls 5a, 5b, 5c and 5d formed of a conductive material are bonded to side faces of wirings 4a and 4b to lee provided on contacts 3a and 3b. Consequently, the wirings 4a and 4b and the contacts 3a and 3b can be electrically connected well through the sidewalls 5a, 5b, 5c and 5d.

Abstract: Disclosed is a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method. A method for forming a semiconductor according to the present invention comprises the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers. Accordingly, the present invention using the air gap as a gap filling materials reduces the parasite capacitance loaded on a bit line and omits an additional gap filling process.

Abstract: The disclosed semiconductor device comprises an ohmic contact between a semiconductor region made of n-conducting silicon carbide and a largely homogeneous ohmic contact layer (110), which adjoins the semiconductor region and is made of a material having a first and a second material component. A silicide formed from the first material component and the silicon of the silicon carbide and a carbide formed from the second material component and the carbon of the silicon carbide are contained in a junction region between the semiconductor region and the ohmic contact layer. The silicide and carbide formation take place at maximum 1000° C.

Abstract: There is disclosed a method of forming stress-adjusted insulating films which are interposed between respective interconnection layers upon laminating metal interconnection layers in excess of three-layer. Multiple layers whose total stress is adjusted are formed by laminating insulating films 22a to 22e, 23a to 23d on a substrate 21.

Abstract: A method for manufacturing an interlayer dielectric layer begins with a preparation of an active matrix provided with a substrate and interconnections formed on the substrate and then the prepared active matrix is set on a chamber. Thereafter, a silicon source material, e.g., a tetra-ethyl-ortho-silicate (TEOS) or modified TEOS and a hydrogen peroxide (H2O2) in a gaseous state are sprayed on the active matrix. And finally, the interlayer dielectric layer is formed on the active matrix by a condensation reaction of the silicon source material and the H2O2.

Abstract: Methods for making an aluminum-containing metallization structure, methods and solutions for cleaning a polished aluminum-containing layer, and the structures formed by these methods. The methods for making the aluminum-containing metallization structure are practiced by providing a substrate, forming a metal layer with an upper surface containing aluminum over the substrate, polishing the metal layer, and contacting the polished surface of the metal layer with a solution comprising water and at least one corrosion-inhibiting agent. The method for cleaning the polished aluminum-containing layer is practiced by contacting a polished aluminum-containing layer with a solution comprising water and a corrosion-inhibiting agent. In these methods and solutions, the water may be deionized water, the corrosion-inhibiting agent may be citric acid or one of its salts, and the solution may contain additional additives, such as chelating agents, buffers, oxidants, anti-oxidants, and surfactants.

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: An underlying conductive film made of iridium and having a thickness of about 0.1 &mgr;m is formed in a contact hole formed in an insulating film covering a transistor formed in a substrate, except in the top portion of the contact hole. The underlying conductive film covers the sidewall portions of the contact hole and the top surface of the drain region but does not completely fill in the contact hole. A plug made of platinum is filled in the contact hole up to the top portion thereof. Over the contact hole of the insulating film, there is formed a capacitor composed of a lower electrode made of platinum, a capacitor insulating film made of SrBi2Ta2O9, and an upper electrode made of platinum in contact relation with the respective upper ends of the underlying conductive film and the plug.

Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.

Abstract: The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers.

Abstract: A method for controlling the critical dimension of a contact opening in a dielectric layer. A substrate has a dielectric layer formed thereon. A hard mask layer is formed over the dielectric layer. A photosensitive layer is formed over the hard mask layer. The photosensitive layer is patterned to expose a portion of the hard mask layer inside a desired contact opening region. A first etching operation is carried out to remove the hard mask layer within the contact opening region so that a portion of the dielectric layer is exposed. A second etching operation is carried out to remove the dielectric layer within the contact opening region, thereby forming the contact opening.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1-xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1-xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1-yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: A trench is formed. A first TEOS film is deposited in the trench. Thereafter, the first TEOS film is etched back by a wet etching method up to a planarized surface of a substrate. In this way, seams and a void generated during the first TEOS film deposition step are exposed. This is attained by performing the etching under the conditions that an etching rate for the TEOS film of the upper portion of the trench is larger than that for the TEOS film of the bottom portion of the trench. Thereafter, a second TEOS film is deposited in the trench.

Abstract: At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step followed by an etch step may be used to remove contamination and damage from a substrate. A method including a first etch step followed by an oxidation step and a second etch step may likewise be used to remove contamination and damage, and a final oxidation step may optionally be included to grow an oxide film. A method including an etch step followed by an oxidation step may also be used to grow an oxide film. Repeated alternate in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is accomplished.

Abstract: A method for forming a gate oxide film includes the steps of: activating either one of deutrium and oxygen through remote plasma process; introducing deutrium and oxygen into a reactive chamber through a sufficiently isolated gas injection units; pyro-reacting deutrium and oxygen to form deuterium vapor; and heating a silicon wafer at an atmosphere of the deutrium vapor and forming a gate silicon oxide film of which silicon dangling bond on the silicon wafer surface makes a Si—D bonding. The silicon dangling bond existing at the interface between the silicon and the SiO2 gate oxide film makes the Si—D bonding, stronger than Si—H bonding, to form the SiO2 film. Therefore, a gate oxide film having an excellent film quality can be formed. In addition, the oxidation is performed at a comparatively low temperature, so that the problem of difficulty in controlling a threshold voltage as the dopant doped at the lower portion of the gate oxide film is diffused outwardly is solved.

Abstract: In one aspect, the invention includes a method of improving uniformity of liquid deposition when a liquid is spin-coated over a noncircular substrate. The substrate is retained on a platform and spun. The circular platform includes a plurality of shaping members pivotally connected to the platform. The plurality of shaping members are biased by spinning the platform to form a platform surface with a circular periphery. In another aspect, the invention includes a substrate coating apparatus. Such apparatus comprises a non-circular substrate support configured to support a substrate with a planar surface and non-circular periphery. The apparatus further comprises a motor configured to spin the substrate support. A plurality of shaping members are pivotally connected with the substrate support and each shaping member has a curved outer side surface.

Abstract: An IC socket adapted to establish an electrical connection between an IC package and a printed board includes a socket body having a mount portion on which the IC package is mounted, a number of contact pins disposed on the socket body in substantially equally adjacent arrangement, each of the contact pins having one end to be connected to a terminal of the IC package and another end to be connected to the printed board, and an interval widening member provided for the socket body for widening a pitch interval between the other ends of adjacent contact pins so as to provide a predetermined distance therebetween.

Abstract: A center bond flip chip device carrier and a method for making and using it are described. The carrier includes a flexible substrate supporting a plurality of conductive traces. A cut out portion is formed in each trace at a position within a gap of a layer of elastomeric material provided over the traces. Each cut out portion is sized and configured to receive a solder ball for electrically connecting the carrier with a semiconductor die.

Abstract: In an IC socket for an electrical part, a contact pin electrically connecting a terminal of an electrical part and a printed circuit board is provided for a socket body of an IC socket. The contact pin comprises a sleeve having a space with one end opening, a plunger inserted into the sleeve through the end opening thereof to be vertically movable and an elastic member for urging downward the plunger. The sleeve is arranged to be vertically movable with respect to the socket body and is provided with a contact portion formed to an upper end thereof contacts a terminal of the electrical part to be electrically connected thereto and the plunger has a lower end contacting the printed circuit board to establish an electrical connection therebetween.

Abstract: An external relay box device for computer peripheries comprises a relay box, a signal cable assembly. The relay box at the front panel thereof provides signal connectors, a circuit board. A box connector is disposed on the circuit board and the circuit board connects with the signal connectors and the box connector for interlinking a signal circuit between the signal connectors and the box connector. The signal cable assembly at an end thereof provides a cable connector to join the box connector and the other end thereof has a plurality of signal wires being formed as a bundle shape and a free end of the bundle at least has a strand of signal wires with a plurality of extended plugs. The extended plugs are inserted into a respective corresponding connector disposed at a rear plate of the computer main unit to allow the signals passing through the box connector so as to extend to each of the signal connector.

Abstract: A printed circuit board connector 10 has a plurality of terminals 3 which connect the connector 10 to a printer circuit board and protrude outside from a rear wall surface 12a of a connector housing 12. Tip end portions of the terminals are bent into an L shape in parallel to the rear wall surface 12a and thereby aligned. A terminal cover 20 is detachably attached to the connector housing 12 so as to cover the terminals 3 and a tip end of an insulating wall 22 provided on the terminal cover 20 is fitted into a groove 15 formed in the rear wall surface 12a, whereby distances among adjacent terminals 3 can be widened and the insulation performance among the terminals 3 can be enhanced.

Abstract: A low profile connector assembly for use with a first printed circuit board having a plurality of first traces extending to an array of interconnect holes and a second printed circuit board having a plurality of second traces extending to an array of interconnect holes. The connector assembly comprises an elongate male connector housing extending along a longitudinal axis and having a first side extending parallel to the longitudinal axis adapted for mounting to the first printed circuit board in a position overlying the array of interconnect holes of the first printed circuit board. The male connector housing has a second side and a cavity communicating with an opening in the second side. A plurality of male electrical contacts of an electrically conductive material are carried by the male connector housing.

Abstract: An electrical interface arrangement includes a buss bar having a longitudinal edge that is substantially smooth and free of conductive tabs. A conductive member, such as an elongated coil spring, is arranged adjacent to the longitudinal edge of the buss bar, and contacts the buss bar with at least 40 A-spots (electrical connection locations) per inch, along an entire length of the buss bar. A circuit board having a plurality of internal planes is provided, with at least one of the internal planes being an internal power plane, and with at least another one of the internal planes being an internal wiring plane having a plurality of conductive wirings. The circuit board further has an arrangement for electrically connecting the conductive member to the internal power plane without interfering with a placement of the conductive wirings, so that the circuit board and the buss bar are in electrical communication.

Abstract: A connector for a battery charger is configured so that a latching member protrude from a connector body, a connector portion is disposed in the lower portion of a latching member, and a keep plate is fixed at the bottom face 12A. When the connector portion is connected to a battery connector located in a recess of a battery pack, hooks of the latching member fit in grooves of the recess, thereby the keep plate 14 comes in contact with a bottom face of the battery pack and the battery connector is pinched between the keep plate and the latching member. The connector is thus locked in the connection state.

Abstract: A cable connector comprises a housing of insulating material, the housing having a plurality of contact terminals, and a metal cover having a first end for accommodating the housing and a second end with a cable exit. The metal cover comprises a location for receiving a strain relief means of the cable near the second end. The cover is provided with at least two cable exits and two locations for receiving a strain relief means. The receiving locations are staggered with respect to each other in the direction from the first to the second end, and/or the receiving locations are placed at an offset with respect to a center plane of the connector in mutually opposite directions.

Abstract: A connector (21) includes at least one terminal (23) and a connector housing (22) having a terminal receiving chamber into which the at least one terminal (23) is insertable. The connector housing (22) has at least one connection port (33) through which a mating terminal is insertable, a detection-pin inserting port (34) through which a lance-displacement detecting pin of a connector conduction-test tool is insertable, and a contact-pin inserting port (35) through which a conduction contact pin (24) of the connector conduction-test tool is insertable. The contact-pin inserting port 35 is formed in such a manner as to cut away an edge portion of the connection port (33).

Abstract: A method for assembling an impedance controlled connector using conventional connector shells and inserts and corresponding connector pins and sockets. Controlled impedance cables are prepared and physically arranged for termination in a conventional connector shell in a configuration which enhances the impedance control characteristic of the assembled connector. Assembly of the connector is effected using conventional materials and tools.

Abstract: A housing is provided with an abutment face formed inside thereof so as to define an insertion opening, to which a electric wire terminal is inserted, and a chamber for accommodating the inserted terminal. The terminal penetrates a gel member before being inserted to the chamber. A holder is provided with an insertion passage through which the terminal passes before penetrating the gel member. The holder is engaged with the housing while being movable between a provisional engagement position and a plenary engagement position. The gel member is compressed against the abutment face of the housing when the holder is placed in the plenary engagement position. The gel member is held by the holder without compressing against the abutment face, when the holder is placed in the provisional engagement position.

Abstract: A connector comprises a terminal (3) and a connector housing (2) having a terminal accommodation chamber (4). The terminal (3) has elastic curled portions (25) that are substantially crest shaped in cross section. A lance (5) for engaging the terminal (3) is formed in the terminal accommodation chamber (4), and tapered portions (22) along which the elastic curled portions (25) slide are formed on the lance (5).

Abstract: At least one positioning projection (12, 13, 14, 15, 16 or 17) is formed at least on at least one deformed wall (e.g., 2) of a synthetic resinmade connector housing (1). The projecting height of the at least one positioning projection (12, 13, 14, 15, 16 or 17) is defined so as to correct an amount of deformation of the at least one wall (2, 3, 4 or 5), and positioning is effected by using the at least one positioning projection (12, 13, 14, 15, 16 or 17) as a reference. In case of a plurality of the positioning projections (12 to 17), the plurality of the positioning projections (12 to 17) are juxtaposed at least on the at least one wall (2, 3, 4 or 5), and projecting height of the plurality of positioning projections (12 to 17) are varied in correspondence with a shape of deformation of the at least one wall (2, 3, 4 or 5).

Abstract: A tab (10A) is comprised of a flat base (12), a substantially U-shaped turning portion (13), a flat overlapping portion (14) which is connected to a side end of the base (12) via the turning portion (13) and faces the base (12) substantially in parallel, and a raising portion (15) extending substantially at right angles from an end of the overlapping portion (14) and held in contact with the base (12). Thickness ta of the tab (10A) can be set at a desired value regardless of thickness tb of a terminal material by changing a curvature of the turning portion (13) and a projecting distance tc of the raising portion (15).

Abstract: In order to make a process available for the production of a position sensor comprising a housing, in the housing interior of which an electrical circuit arranged on a carrier is seated, which can be carried out with less time expended and inexpensively it is suggested that the carrier be connected to an electrical connection element to form a carrier-connection element combination, the carrier-connection element combination be introduced into the housing closed at a measuring end from the rear end located opposite the measuring end, the space around the carrier-connection element combination in the interior of the housing be filled with a molding compound up to a specific level and a cap be connected to the rear end of the housing, connections of the connection element being guided through this cap.

Abstract: In a connector fitting structure, one connector includes an inner housing, having lock arms, and an outer housing having a slider slidably mounted therein. The other connector includes a housing, and engagement projections for abutment against the slider and for respectively elastically deforming the lock arms are formed on this housing. Second retaining portions, which are engageable respectively with first retaining portions formed on the one connector, are formed respectively on engagement arms 16 provided at a second slide member of the slider. Stoppers, which prevent the cancellation of the engagement of the first retaining portions with the second retaining portions before starting the connector fitting operation, are formed on a first slide member of the slider.