Abstract: The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

Abstract: In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer.

Abstract: Nonvolatile memory and method for fabricating the same, which can prevent damages to a diffusion region between a selection transistor and a memory cell transistor and reduce a cell size, the nonvolatile memory including a semiconductor substrate having a selection transistor and a cell transistor defined thereon, a line form of a first selection gate line formed on the selection transistor region in one direction and a floating gate formed on the cell transistor region in a fixed pattern, an insulating film and a second gate line formed on the first selection gate line at fixed intervals, and an insulating film and a control gate line over the insulating film including the floating gate in a direction the same with the first gate line, impurity regions formed in one region in the semiconductor substrate on both sides of the control gate line and the first selection gate line, a first planar protection film having first contact holes one each to the first selection gate line and to the impurity region, a cont

Abstract: In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A trench-gate semiconductor device, for example a MOSFET or an IGBT, has a network of connected trenches (20) containing gate material (21) in a semiconductor body (10) in an active transistor cell area 100 with an n-type source region (13A) and an underlying channel accommodating p-type region (15A) in each cell. A source electrode (51) contacts the source regions (13A). Trenches (20) containing gate material (21) extend from the network of connected trenches in the area 100 to an inactive area (200) having a gate electrode contact area (201) where a gate electrode (53) contacts the gate material (21) on the whole area of the trenches (20) adjacent the semiconductor body surface (10a) and where the gate electrode (53) also contacts the semiconductor body surface (10a) adjacent the trenches (20).

Abstract: A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm, or preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.

Abstract: There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p- epitaxial growth layer along a trench, and an electron current flows from an n+drain layer to the p- epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved.

Abstract: In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, isotropic etching is performed to round a corner of a bottom portion of the trench without removing the reaction product. The isotropic etching can round the corner of the trench without etching the side wall of the trench that is covered by the reaction product.

Abstract: A trench DMOS transistor cell is provided, which is formed on a substrate of a first conductivity type. A body region, which has a second conductivity type, is located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. The insulating layer includes first and second portions that contact one another at an interface. The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary of the body region. A conductive electrode is formed in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench.

Abstract: A semiconductor chip is ESD protected, in part, by utilizing floating lateral clamp diodes. Unlike conventional clamp diodes, which are based upon parasitic bipolar devices associated with large MOS transistors, the floating lateral clamp diodes utilize a well formed in the substrate as the cathode, and a plurality of regions of the opposite conductivity type which are formed in the well as the anode.

Abstract: A semiconductor device constructed as a reverse conducting static induction thyristor including a thyristor section 114 formed by an n− silicon substrate 101, p+ gate regions 102, 104 formed in one surface of the substrate, a p+ anode region 111 formed in the other surface of the substrate, a main diode section 134 having a cathode region formed by the silicon substrate and an anode region 131 formed in the one surface of the substrate, and a series arrangement 145 of diodes including plural p+ anode regions 142, plural n+ cathode contact regions 143 formed in the first surface of the substrate, and plural conductive layers 144 connecting these anode regions and cathode contact legions successively. An anode and a cathode of the series arrangement of diodes are connected to a cathode electrode 110 and an anode electrode 113 of the thyristor section. Each of diodes in the series arrangement has a breakdown voltage lower than that of the thyristor section.

Abstract: New Group III nitride based field effect transistors and high electron mobility transistors are disclosed that provide enhanced high frequency response characteristics. The preferred transistors are made from GaN/AlGaN and have a dielectric layer on the surface of their conductive channels. The dielectric layer has a high percentage of donor electrons that neutralize traps in the conductive channel such that the traps cannot slow the high frequency response of the transistors. A new method of manufacturing the transistors is also disclosed, with the new method using sputtering to deposit the dielectric layer.

Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

Abstract: A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.

Abstract: A power semiconductor device of the present invention comprises a voltage drive type power MOS transistor, a series connection of a first resistor and Zener diode, a second resistor, and a series connection of a third resistor and MOS transistor. The power MOS transistor has a gate, source and drain. A drain-to-source voltage of the power MOS transistor is applied across the series connection of the first resistor and Zener diode. A gate-to-source voltage of the power MOS transistor is applied across the second resistor. The gate-to-source voltage of the power MOS transistor is applied across a series connection of a third resistor and the MOS transistor. The MOS transistor has a gate, source and drain. The gate of the MOS transistor is connected to a node between the first resistor and the Zener diode.

Abstract: Described is an electronic device having a compliant fibrous interface. The interface comprises a free fiber tip structure having flocked thermally conductive fibers embedded in an adhesive in substantially vertical orientation with portions of the fibers extending out of the adhesive and an encapsulant between the portions of the fibers that extend out of the adhesive and the fiber's free tips.

Abstract: An integrated circuit arrangement having two NMOS transistors with different cut off voltages and two PMOS transistors with different cut off voltages. Channel regions of the NMOS transistors exhibit the same dopant concentration. The analogous case applies to the PMOS transistors. The different cut off voltages are achieved by different chemical compositions of the gate electrodes of the transistors. Preferably, the chemical compositions of the gate electrodes of respectively one of the NMOS transistors and one of the PMOS transistors thereby coincide. Si1−xGex with 0≦x≦1 is suitable as a material for the gate electrodes. The transistors preferably form pairs with transistors complementary to one another that exhibit the same cut off voltages. Given a dopant concentration of the channel regions of the NMOS transistors that is approximately 1.5 times greater than a dopant concentration of the channel regions of the PMOS transistors, the value of x amounts, for example, to 0.

Abstract: A semiconductor device package, has

Abstract: A film, typically a silicon-based film, is formed on a substrate by means of a plasma CVD process using a high frequency wave in a condition where a resistance element made of a different material than that of the substrate is provided on the electric path between the substrate and the earth. The resultant film shows a high quality and an improved adhesion strength while it can be formed at a practically high rate.

Abstract: Polymer blobs that are development related defects are substantially eliminated in the patterned photoresist masks by a heat treatment of the wafer performed at the development step in two different manners according to the present invention. In the first method, after the development has been performed as standard, the wafer is heated at 140° C. and before cooling takes place, it is rinsed with deionized water (DIW) at room temperature. In the second method, the wafer is either developed as standard but rinsed with 60° C. DIW instead of 22° C. DIW or, after standard development, it is submitted to an extra rinse step with 60° C. DIW.

Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

Abstract: Walkout in high voltage trench isolated semiconductor devices is inhibited by applying a voltage bias signal directly to epitaxial silicon surrounding the device. Voltage applied to the surrounding epitaxial silicon elevates the initial breakdown voltage of the device and eliminates walkout. This is because voltage applied to the surrounding epitaxial silicon reduces the strength of the electric field between the silicon of the device and the surrounding silicon. Specifically, application of a positive voltage bias signal to surrounding epitaxial silicon equal to or more positive than the most positive potential occurring at the collector during normal operation of the device ensures that no walkout will occur.

Abstract: Adjacent ones of a plurality of fuse electrodes extending parallel to each other are cut off by a laser beam. Cutting positions on the adjacent fuse electrodes are set to positions which are different from each other in a direction in which the fuse electrodes extend. Since the cutting positions on the adjacent fuse electrodes are different from each other, the adjacent fuse electrodes are prevented from being short-circuited by fragments of components thereof that are scattered when the laser beam is applied to cut off the fuse electrodes.

Abstract: In a semiconductor device comprising first and second layer wirings formed with a space left therebetween and a capacitor formed in the space and electrically connected to the first and the second layer wirings, the capacitor comprises a via electrically connected to one of the first and the second layer wirings, an electrode made of a conductive material and electrically connected to the one of the first and the second layer wirings through the via, and a dielectric film formed between the electrode and the other of the first and the second layer wirings.

Abstract: A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.

Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.

Abstract: A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

Abstract: A stacked semiconductor device includes a plurality of stacked wiring substrates each having connection electrodes and wires connected to the connection electrodes and each mounted with a semiconductor device, a plurality of conductive via boards each interposed between adjacent two wiring substrates and having an opening for enclosing the semiconductor device, an uppermost wiring substrate formed on the top of the stacked wiring substrates and having wires connected to the connection electrodes, and a lowermost wiring substrate formed under the stacked wiring substrates and having wires connected to the connection electrodes, wherein heat radiation/shield conductive layers are formed on the uppermost and lowermost wiring substrates.

Abstract: A semiconductor device is provided, which device includes a semiconductor substrate including a plurality of signal pads and ground pads, an insulating film formed on the semiconductor substrate, a conductive metal film formed on the insulating film and electrically connected to the ground pads and a plurality of first interconnection lines electrically connected to the signal pads and insulated from the conductive metal film. The conductive metal film is formed over a region including the first interconnection lines in a plan view of the semiconductor device.

Abstract: A small package is provided for a flash EEPROM memory. The small package uses terminals which are part of a bottom conductive layer of a circuit board. In this manner, the final package can be quite thin. The circuit board can be connected to the integrated circuits and passive devices and can be encapsulated in plastic or glued to a plastic cover. In this manner, a thin and relatively inexpensive package can be formed. Additionally, the circuit board can have testing connections which can be removed before forming the final package.

Abstract: Supply of a semiconductor device capable of preventing the likely occurrence of cracking of a ceramic substrate, and the consequential disconnection of internal layer wiring, due to the thermal changes suffered when the semiconductor device is mounted on external wiring boards different in thermal expansion coefficient.

Abstract: A semiconductor package includes a substrate panel, a chip, an upper package encapsulant, and a lower package encapsulant. The chip is mounted to the substrate panel and below a hole in the substrate panel. A number of wires interconnect the leads on the chip with the leads on the substrate panel. The upper package encapsulant is formed on the upper side of the substrate panel by filling molten liquid plastic material into an upper mold placed on the upper side of the substrate panel. The lower package encapsulant is formed on the underside of the substrate panel by filling molten liquid plastic material into a lower mold placed on the underside of the substrate panel.

Abstract: A method of making a microelectronic assembly includes providing a first microelectronic element having one or more conductive bumps, the conductive bumps including a first fusible material that transforms from a solid to a liquid at a first melting temperature, and providing a second microelectronic element having one or more conductive elements. The conductive bumps of the first microelectronic element are electrically interconnected with the conductive elements of the second microelectronic element using a second fusible material, the second fusible material having a second melting temperature that is lower than the first melting temperature of the first fusible material. During the electrically interconnecting step, the second fusible material is maintained at a temperature that is greater than or equal to the second melting temperature and less than the first melting temperature of the first fusible material.

Abstract: Carbon nanotube devices and methods for fabricating these devices, wherein in one embodiment, the fabrication process consists of the following process steps: (1) generation of a template, (2) catalyst deposition, and (3) nanotube synthesis within the template. In another embodiment, a carbon nanotube transistor comprises a carbon nanotube having two or more defects, wherein the defects divide the carbon nanotube into three regions having differing conductivities. The defects may be introduced by varying the diameter of a template in which the carbon nanotube is fabricated and thereby causing pentagon-heptagon pairs which form the defects.

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

Abstract: There is provided a semiconductor device comprising a Cu film provided above a main surface of a semiconductor substrate and used as a wiring, an intermediate layer formed at least on the Cu film, and an Al film formed on the intermediate layer and used as a pad, wherein the intermediate layer comprises a refractory metal nitride film and a refractory metal film formed on the refractory metal nitride film.

Abstract: A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component.

Abstract: A Cu wiring is formed on a higher layer than a Si substrate, and a via plug formed in a via hole communicates with the higher layer and the Si substrate. Etch rates of a HSQ layer surrounding a damascene and the first SiO2 layer formed on the Si substrate change in different modes depending on the ratio of the flow rate of the first reactive gas to that of the second reactive gas. According to the aforementioned structure, a dual damascene structure of the semiconductor device in which there is no necessity for forming a stopper layer formed of silicon nitride between the insulating layers, and a capacitance between wirings can be reduced.

Abstract: A connection between a contact plug and an interconnect in a semiconductor device is disclosed. A contact plug is formed in a hole within an insulating film with its upper end generally in flush with a surface of the interlayer insulating film. An interconnect uses a laminated film structure that includes an aluminum film over the upper end of each of the contact plug.

Abstract: A highly integrated system-on-chip system with a non-volatile memory unit, includes a chip having an integrated MRAM memory unit, and semiconductor layers disposed underneath the MRAM memory unit and functioning merely as carriers for the MRAM memory unit. An integration density of the chip may be increased by using the semiconductor layers for additional integrated circuits.

Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate; at least a pad electrode provided over the semiconductor substrate; a passivation film provided over the semiconductor substrate; an insulative resin stress buffer layer provided over the at least pad electrode and the passivation film, the insulative resin stress buffer layer having at least an opening positioned over at least a part of the at least pad electrode; and at least a land portion provided over the insulative resin stress buffer layer and also electrically connected to the at least pad electrode, and a top surface of the at least land portion being electrically connected to at least a bump which is positioned over the at least land portion, wherein the at least land portion and the passivation film are isolated from each other by the insulative resin stress buffer layer.

Abstract: A semiconductor device includes, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed, and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the first chip top surface is fixed on the die pad bottom surface, the second chip bottom surface is fixed on the die pad top surface.

Abstract: Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

Abstract: A control method for an injection molding machine comprises the steps of measuring a density of a molten resin in a heating cylinder, controlling a stroke of an injection screw in an injection process by feed forward control based on the measuring step, and controlling an operating parameter of the injection molding machine based upon the measuring step.

Abstract: The retreat completion position of the screw in the charging step in actual production is controlled based on the result in pilot production as follows. In pilot production, the measurement value Ts of the screw driving torque is integrated with respect to the screw position P from the forward limit to the retreat completion position Ps. When conforming item is produced in the pilot production, the value &Sgr;Ts·dP obtained as a result of the integration is stored as a reference value. After actual production begins, the measurement value Tx of the screw driving torque is integrated in real time with respect to the screw position P from the forward limit to the screw position at each time. The obtained value &Sgr;Tx·dP is monitored. When this value &Sgr;Tx·dP coincides with the reference value &Sgr;Ts·dP, it is determined that the charging step has been completed, and the retreat operation of the screw is stopped.

Abstract: An apparatus for producing an extruded film tube and supplying said tube to a collapsing and roller assembly includes a die for extruding a molten material in the form of a tube which is in a molten state below a frost line and in a solid state above the frost line. A blower system supplies and exhausts cooling air to and from an interior portion of the tube, and is regulated by a valve. At least two sensors are provided, one below the frost line for sensing the position of said tube, and one located proximate the tube in a position above said frost line. The upper sensor is used for sensing the position of the tube prior to collapsing and flattening it. A controller receives feedback signals from both sensors and controls operation of the valve.

Abstract: A method of producing a rubber-based covering comprising at least one layer formed from fragmented cohesible material comprises the steps of forming a substantially continuous bed of the fragmented cohesible material and subjecting the material of the bed to a compacting step so as to form a sheet material as a result of the cohesion of the material. The compaction step is performed with a substantial absence of stretching stresses on the fragmented material.

Abstract: A mold for molding a core for use in casting hollow parts includes, a lower mold portion and an upper mold portion defining therein a cavity corresponding to the outer surface of the core The lower mold portion includes a cutout disposed along a parting line defined between the lower mold portion and the upper mold portion and opening onto the cavity After introduction of a ceramic slurry mixture into the mold the upper mold portion is removable, to expose a first side of the core and a protective flash formed in the cutout Desirably, a heat shield is positioned over the protective flash and the exposed portion of the parting line of the lower mold portion so that the lower mold portion is not exposed directly to a flame during a preliminary firing to impart sufficient strength to the ceramic core so that the ceramic core may be handled.

Abstract: An actuator for a press comprises a piston disposed through a small bore diameter high speed actuating cylinder, having a piston head disposed within the actuating cylinder and another piston head disposed within a larger bore diameter hydraulic clamping cylinder to apply the required clamping force to the press.