Patents Issued in December 6, 2001
  • Publication number: 20010049130
    Abstract: An endocrine cell microdisk or macrodisk containing pancreatic cells for transplantation into an animal body is formed with a lateral extent much greater than its thickness to thereby enhance its diffusional capability. One or more concavities may also be formed therein to further enhance the diffusion of cellular products across the microdisk walls.
    Type: Application
    Filed: August 13, 2001
    Publication date: December 6, 2001
    Inventor: Theodore E. Spielberg
  • Publication number: 20010049131
    Abstract: The present invention relates to novel baths for generating microstructures which are required in numerous fields of application of the microsystem technique and in microstructuring. It is an object of the invention to provide novel baths for generating microstructures which offer a less expensive and, above all, a solution for their disposal which is more friendly to environment than the previous methods for manufacture of microstructures. The object is realized in that the respective baths are added at least one biogenic catalyst (in particular, an enzyme) which acts upon a preselectable thin layer.
    Type: Application
    Filed: February 5, 1999
    Publication date: December 6, 2001
    Inventors: EUGEN ERMANTRAUT, JOHANN MICHAEL KOHLER, TORSTEN SCHULZ, KLAUS WOHLFART
  • Publication number: 20010049132
    Abstract: The present invention relates to the field of producing starter cultures. In particular, a method for customers in need of a starter culture with a consistent quality, is provided. Specifically, the method involves the use of subsets of a stock inoculum material, which comprises a concentrate of starter culture organism cells to be propagated for direct inoculation of a cultivation medium, to obtain a starter culture whereby the conventional stepwise preparation of inoculum material for the production of a starter culture can be avoided. This novel method can be used for the manufacturing of starter cultures for the food, feed or pharmaceutical industry. Furthermore, the method is useful in the cultivation of cells expressing desired products, such as primary and secondary metabolites, including e.g. enzymes and flavors.
    Type: Application
    Filed: March 21, 2001
    Publication date: December 6, 2001
    Inventors: Borge Kringelum, Maibritt Kringel, Knud Striib Nielsen
  • Publication number: 20010049133
    Abstract: A method of protein removal is provided, which utilizes a protein digesting enzyme and a detergent that is compatible with ultrafiltration. The method is particularly suited for isolating trace amounts of nucleic acid from a solution that has high protein concentration. The recovered nucleic acid is free of protein that may interfere with downstream application such as nucleic acid quantification or diagnostic use. A kit suitable for use in the protein removal method is also provided.
    Type: Application
    Filed: July 13, 2001
    Publication date: December 6, 2001
    Applicant: GENETIC VECTORS, INC.
    Inventors: Mead M. McCabe, Raymond Henderson
  • Publication number: 20010049134
    Abstract: Apparatus for effecting reactions, said apparatus comprising a plurality of reaction vessels for holding reagents, an electrically conducting polymer which emits heat when an electric current is passed through it, and control means for controlling supply of current to the polymer, the polymer being connectable to an electrical supply via the control means. The control means may be arranged such that different currents and therefore different temperatures can be achieved in each reaction vessel.
    Type: Application
    Filed: July 13, 2001
    Publication date: December 6, 2001
    Applicant: The Secretary of State for Defence.
    Inventors: Martin A. Lee, Hilary Bird, Dario Lyall Leslie
  • Publication number: 20010049135
    Abstract: A metallic protective housing for a skid-mounted aerobic reduction reactor which includes a pitched roof supported by two side walls and an end wall, each wall being secured to the skid. The two side walls and roof having reinforced structural members secured to the skid and to the reactor to form a point of attachment for moving the reactor. A series of hinged doors in the side and end walls to provide selective access to the reactor. The interior surfaces of the walls and roof being covered by insulation to control temperatures within the housing.
    Type: Application
    Filed: February 12, 2001
    Publication date: December 6, 2001
    Inventors: Gary D. Roberts, Verlin J. Roberts
  • Publication number: 20010049136
    Abstract: Novel eective adenoviruses for the transfer and expression of an exogenous nucleotide sequence in a host cell or organism. The invention also relates to novel complementation lines and to the process for the preparation of these novel defective adenoviruses and their use in therapy and to a pharmaceutical composition containing same.
    Type: Application
    Filed: November 30, 2000
    Publication date: December 6, 2001
    Inventors: Jean-Luc Imler, Majid Mehtali, Andrea Pavirani
  • Publication number: 20010049137
    Abstract: The invention concerns DNA fragments derived from the genomic DNA of HPV-33. These fragments are selected from the group of fragments extending between the nucleotide extremities defined hereafter in relation to the nucleotide-numbering in FIGS.
    Type: Application
    Filed: April 12, 2001
    Publication date: December 6, 2001
    Applicant: INSTITUT PASTEUR
    Inventors: Stewart Cole, Rolf E. Streeck
  • Publication number: 20010049138
    Abstract: A method for chemically acellularizing a biological tissue sample, such as a peripheral nerve, is provided. The method includes disrupting the cell membranes of the biological tissue sample, and then denaturing intracellular proteins within the cells of the tissue sample and removing the denatured proteins from the cells while preserving the extracellular matrix to produce an acellularized tissue construct.
    Type: Application
    Filed: June 29, 2001
    Publication date: December 6, 2001
    Applicant: The Regents of the University of Michigan
    Inventors: Robert G. Dennis, William M. Kuzon, Paul S. Cederna
  • Publication number: 20010049139
    Abstract: Functional hepatic cells are generated from hematopoietic stem cells. In transplantation, populations of hematopoietic stem cells are shown to give rise to repopulating hepatocytes. The stem cells are obtained from a variety of sources, including fetal and adult tissues. The cells are useful in transplantation, for experimental evaluation, and as a source of lineage and cell specific products, including mRNA species useful in identifying genes specifically expressed in these cells, and as targets for the discovery of factors or molecules that can affect them.
    Type: Application
    Filed: March 23, 2001
    Publication date: December 6, 2001
    Inventors: Eric Lagasse, Irving L. Weissman
  • Publication number: 20010049140
    Abstract: Gel-based medium compositions and a method of use thereof in normothermic, hypothermic or cryopreservative storage and transport of cell samples are described. These gel-based compositions contain a cell maintenance and preservation medium together with a gelling agent. Such gel-based medium compositions protect various cell samples, such as animal or plant organs, tissues and cells, from the mechanical, physiological and biochemical stresses inherently associated with liquid preservation techniques.
    Type: Application
    Filed: January 11, 2001
    Publication date: December 6, 2001
    Applicant: Biolife Solutions, Inc.
    Inventors: John M. Baust, Robert Van Buskirk, John G. Baust
  • Publication number: 20010049141
    Abstract: The present invention relates generally to nutritive medium, medium supplement, media subgroup and buffer formulations. Specifically, the present invention provides powder nutritive medium, medium supplement and medium subgroup formulations, particularly cell culture medium supplements (including powdered sera such as powdered fetal bovine serum (FBS)), medium subgroup formulations and cell culture media comprising all of the necessary nutritive factors that facilitate the in vitro cultivation of cells. The invention further provides powder buffer formulations that produce particular ionic and pH conditions upon reconstitution with a solvent.
    Type: Application
    Filed: February 13, 1998
    Publication date: December 6, 2001
    Inventors: RICHARD FIKE, WILLIAM WHITFORD, WILLIAM BIDDLE
  • Publication number: 20010049142
    Abstract: A rapid, simple-to-use method for preparing hybrid cells, applicable to fully differentiate, non-dividing cells, entails bringing at least two different cells into contact under conditions that promote cell fusion and then purifying the resultant hybrid without antibiotic or metabolic selection. This approach yields hybrid cells useful in a variety of applications, including clinical treatment regimens, as cellular modulators of the immune system.
    Type: Application
    Filed: January 9, 2001
    Publication date: December 6, 2001
    Inventors: Thomas E. Wagner, Yanzhang Wei
  • Publication number: 20010049143
    Abstract: A method for producing human cell lines by immortalizing a precursor or undifferentiated cell with a controllable immortalizing agent, culturing the cell to provide a cell population, and terminating immobilization to allow differentiation.
    Type: Application
    Filed: April 18, 2001
    Publication date: December 6, 2001
    Inventor: Bradley Michael John Stringer
  • Publication number: 20010049144
    Abstract: Methods for high level expression of genes in primates are disclosed. Such methods involve expression of transgenes comprising an RSV promoter and a nucleic acid sequence that is heterologous thereto.
    Type: Application
    Filed: December 8, 2000
    Publication date: December 6, 2001
    Inventors: Victor Rivera, Philip Zoltick, James M. Wilson
  • Publication number: 20010049145
    Abstract: The present invention relates to novel hepatitis B virus vectors for use in gene therapy which can deliver therapeutic genes to liver cells. The invention also provides methods for the production of novel recombinant hepatitis B viruses. The recombinant viruses produced by this invention can deliver therapeutic genes specifically to liver cells either through in vivo or ex vivo therapy protocols. This vector can be used not only to treat liver diseases but also genetic diseases.
    Type: Application
    Filed: April 19, 2001
    Publication date: December 6, 2001
    Inventors: Wang-Shick Ryu, Jehan Lee, Jong Keun Jeong, Woo Young Cho, Gye Soon Yoon
  • Publication number: 20010049146
    Abstract: The present invention relates to the use of sterol esters for the long-term stabilization of biological fluids, in particular even those which are obtained by lyophilization and subsequent reconstitution.
    Type: Application
    Filed: October 29, 1999
    Publication date: December 6, 2001
    Applicant: Dade Behring Marburg, GmbH
    Inventor: HARALD ALTHAUS
  • Publication number: 20010049147
    Abstract: A system and method for identifying a biological sample associated with a container is disclosed. A universally unique-identifier is associated with each container. In one or more embodiments, the identifier comprises one or more markings having a specular reflectance which differs from the specular reflectance of the outer surface of the container adjacent the markings. A detection apparatus detects the differences in specularly reflected light to identify the identifier associated with the container. The identifier is associated with certain information regarding the container and biological sample. From that point forward, any information about the contents of the container may be retrieved by searching on its container ID. Because the container ID is assured by its manufacturer to be universally-unique, the container and sample may move from one organization to another under the same identifier, and information about the contents of the container may be shared by querying on its container ID.
    Type: Application
    Filed: December 30, 1998
    Publication date: December 6, 2001
    Inventors: PIERRE BIERRE, SREEDHAR PAYAVALA
  • Publication number: 20010049148
    Abstract: Ultra-high throughput systems and methods are used for sampling large numbers of different materials from surfaces of substantially planar library storage components. The systems and methods typically employ: microfluidic devices having integrated capillary elements for carrying out the analysis of the sampled materials; library storage components, e.g., planar solid substrates, capable of retaining thousands, tens of thousands and hundreds of thousands of different materials in small areas; sensing systems for allowing rapid and accurate sampling of the materials by the microfluidic devices, and associated instrumentation for control and analysis of the overall operation of these systems.
    Type: Application
    Filed: December 28, 2000
    Publication date: December 6, 2001
    Inventors: Jeffrey A. Wolk, Sherri Ann Biondi, J. Wallace Parce, Morten J. Jensen, Anne R. Kopf-Sill
  • Publication number: 20010049149
    Abstract: Several pin transfer assemblies are disclosed that utilize the surface tension of liquids for picking up and dispensing minute volumes of liquid from wells in a first well plate to a flat substrate surface or into wells in a second well plate. In one embodiment, a plurality of pins reciprocate through complementary arrays of holes in a base plate and an overlying spring plate biased apart by coil springs located around the periphery of the base plate. A foam layer sits on top of the spring plate and a weight plate sits on top of the foam layer. A single coil spring is positioned between a center of the weight plate and the cover to push the weight plate downwardly. The periphery of the cover guides the vertical movement of the weight plate and is connected to the periphery of the base plate. The periphery of the base plate is supported by a frame used to register the pin assembly in a receptacle of a manual or automated liquid transfer apparatus.
    Type: Application
    Filed: February 5, 2001
    Publication date: December 6, 2001
    Inventors: Craig M. Kennedy, Fernando J. Ramirez
  • Publication number: 20010049150
    Abstract: An organic film is etched by using plasma generated from an etching gas including a first gas containing, as a principal constituent, a compound including carbon, hydrogen and nitrogen and a second gas including a nitrogen component.
    Type: Application
    Filed: May 15, 2001
    Publication date: December 6, 2001
    Inventors: Hideo Nakagawa, Toshio Hayashi, Yasuhiro Morikawa
  • Publication number: 20010049151
    Abstract: In a method for manufacturing a semiconductor device, probe pads are formed simultaneously with formation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device ill accordance with characteristics of the semiconductor device obtained by the test operation.
    Type: Application
    Filed: July 11, 2001
    Publication date: December 6, 2001
    Inventor: Yuji Kayashima
  • Publication number: 20010049152
    Abstract: The purpose of the invention is to provide a photoelectric conversion element enable to ensure the connection of the contact electrode easily and accurately.
    Type: Application
    Filed: August 9, 2001
    Publication date: December 6, 2001
    Inventors: Takehiro Taniguchi, Hironobu Narui, Noriko Ueno, Nobukata Okano
  • Publication number: 20010049153
    Abstract: In a method for manufacturing an organic EL element, a low-resistance conductive layer is formed on an electrode of an organic EL element formed on a substrate in a state in which the substrate is at a temperature not higher than the freezing point so that no abnormal current nor short circuit occurs on the organic EL element when applying a voltage to it.
    Type: Application
    Filed: December 28, 2000
    Publication date: December 6, 2001
    Applicant: NEC CORP
    Inventor: Taizou Tanaka
  • Publication number: 20010049154
    Abstract: An array substrate for use in an X-ray sensing device is fabricated using an etching stopper that enables good control of the etching process, and an electrode that prevents damage caused by static electricity generated during a dry-etching step. During fabrication, the array substrate includes a plurality of gate lines that are all electrically connected to an electrode pattern via gate line extensions and gate line contact holes. The electrode pattern causes the gate lines to have equipotentials, which reduces static electricity induced defects.
    Type: Application
    Filed: February 21, 2001
    Publication date: December 6, 2001
    Inventors: Kyo-Seop Choo, June-Ho Park
  • Publication number: 20010049155
    Abstract: A plurality of semiconductor chips bent along the outer circumferential surface of a cylindrical substrate are mounted to the outer circumferential surface of the substrate. The bumps of these semiconductor chips are connected to connection pads formed on the outer circumferential surface of the substrate. By diminishing the curvature radius of the bent semiconductor chips, the size of the semiconductor module can be made smaller than the size of the chip.
    Type: Application
    Filed: June 4, 2001
    Publication date: December 6, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasuhiro Yamaji
  • Publication number: 20010049156
    Abstract: A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads are formed by etching such that they have a concave profile and a thickness far larger than that of conventional die pad and connection pads formed by plating. This prolongs the path and time for moisture diffusion into the package, and significantly increases the area of the interface between the package body and the die pad as well as the connection pads thereby promoting adhesion therebetween. The present invention further provides a method of producing the low-pin-count chip package described above.
    Type: Application
    Filed: June 7, 2001
    Publication date: December 6, 2001
    Applicant: ADVANCED SEMICONDUCTO ENGINEERING, INC.
    Inventors: Kyujin Jung, Kun-A Kang
  • Publication number: 20010049157
    Abstract: A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multi-conductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external circuitry.
    Type: Application
    Filed: August 6, 2001
    Publication date: December 6, 2001
    Inventors: Jerrold L. King, Jerry M. Brooks
  • Publication number: 20010049158
    Abstract: A method of making a microelectronic assembly comprises providing a first side assembly juxtaposed with a second side assembly and a first resilient element disposed therebetween. Leads extend between the first side assembly and the second side assembly. A compressive force is applied to the juxtaposed assemblies so as to compress the first resilient element and the compressive force is at least partially released so as to allow the first resilient element to expand, thereby moving one or both of the first side assembly and the second side assembly to deform the leads.
    Type: Application
    Filed: March 19, 2001
    Publication date: December 6, 2001
    Inventors: Mike Warner, Elliott Pflughaupt
  • Publication number: 20010049159
    Abstract: A flexible substrate strip comprises a plurality of substrate units adapted for mounting semiconductor chips. The surface of the flexible substrate strip is provided with a plurality of degating regions at locations such that the edges of mold runners and gates of a mold used to encapsulate the semiconductor chips in encapsulant material fit entirely within the degating regions when the substrate strip is placed in the mold during encapsulation of the semiconductor chips. The present invention is characterized in that each degating region has a buffer region at a location corresponding to the gate of the mold during encapsulation. The degating regions have a degating region material formed thereon with the buffer regions not coated with the degating region material. The adhesive force between the encapsulant material and the degating region material is less than the adhesive force between the encapsulant material and the substrate.
    Type: Application
    Filed: June 12, 2001
    Publication date: December 6, 2001
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kao-Yu Hsu, Shih Chang Lee, Wei-Chun Kung
  • Publication number: 20010049160
    Abstract: Semiconductor chips are formed on a wafer. The wafer is diced, while a dicing tape applied to the wafer is kept intact. Each of the semiconductor chips is fixed by suction and then removed from the dicing tape. Each of the semiconductor chips is unfixed by ceasing the suction and picked up and conveyed.
    Type: Application
    Filed: December 26, 2000
    Publication date: December 6, 2001
    Applicant: FUJITSU LIMITED
    Inventors: Mitsuhisa Watanabe, Kazuo Teshirogi, Eiji Yoshida, Yuzo Shimobeppu, Yoshito Konno, Kyouhei Tamaki
  • Publication number: 20010049161
    Abstract: An apparatus processing a gate portion in a semiconductor manufacturing apparatus includes a laser beam scanner unit and a cutter. The laser beam scanner unit is disposed along a carrying line on which a lead frame is carried. The laser beam scanner unit has an optical scanner unit second-dimensionally scanning laser beams, and a lens unit collecting the laser beams. The cutter has a punch. The punch mechanically pushes to cut a gate correspondence portion which is perfectly cut away or almost cut away from a semiconductor package body by the laser beams.
    Type: Application
    Filed: May 30, 2001
    Publication date: December 6, 2001
    Inventor: Takehiko Takahashi
  • Publication number: 20010049162
    Abstract: A semiconductor wafer diaphragm comprising a non-flat film coupled to a mounting lip is disclosed. The semiconductor wafer diaphragm is useful for reducing the edge fracture of semiconductor wafer die due to sagging of prior art semiconductor wafer tape after a semiconductor wafer adhered thereto is cut. The non-flat film of the semiconductor wafer diaphragm preferably has a surface of a convex shape and is either inherently sticky or has an adhesive layer applied to said surface. The semiconductor wafer diaphragm is used by mounting an uncut semiconductor wafer to the diaphragm in the ordinary way thereby collapsing the diaphragm, cutting the semiconductor wafer, thereafter restoring the diaphragm to the original expanded shape of the semiconductor wafer diaphragm, and removing the individually created die.
    Type: Application
    Filed: February 2, 1999
    Publication date: December 6, 2001
    Inventor: MICHELLE BROYLES
  • Publication number: 20010049163
    Abstract: Disclosed is a bottom-gate-type semiconductor device comprising crystalline semiconductor layers, in which the source/drain regions each have a laminate structure comprising a first conductive layer (n+ layer), a second conductive layer (n− layer) of which the resistance is higher than that of the first conductive layer, and an intrinsic or substantially intrinsic semiconductor layer (i-layer). In this, the n−layer functions as an LDD region, and the i-layer functions as an in-plane offset region. The semiconductor device has high reliability and high reproducibility, and is produced in a simple process favorable to mass-production.
    Type: Application
    Filed: March 5, 2001
    Publication date: December 6, 2001
    Inventors: Shunpei Yamazaki, Jun Koyama, Takeshi Fukunaga
  • Publication number: 20010049164
    Abstract: One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain zone (12) and a channel zone (13) formed in a surface zone (11) of a semiconductor substrate (10). Said semiconductor zones adjoin a surface (14) of the semiconductor substrate on which surface a layer structure (17) is formed comprising floating gates (16) and control gates (15). The layer structure is provided with windows (18) through which UV radiation can reach the edges of the floating gates. The memory is further provided with means for generating an electric voltage between the substrate (10) and the control gates (16) during programming the memory by means of UV radiation. Thus, the memory can be programmed without being externally contacted during programming.
    Type: Application
    Filed: April 30, 2001
    Publication date: December 6, 2001
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Franciscus Petrus Widdershoven
  • Publication number: 20010049165
    Abstract: A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is connected to other transistors and other IC components through interconnects formed on top of such self-aligned contact windows.
    Type: Application
    Filed: June 28, 2001
    Publication date: December 6, 2001
    Applicant: Mosel Vitelic, Inc.
    Inventor: Cheng-Tsung Ni
  • Publication number: 20010049166
    Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.
    Type: Application
    Filed: March 26, 2001
    Publication date: December 6, 2001
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniela Peschiaroli, Alfonso Maurelli, Elisabetta Palumbo, Fausto Piazza
  • Publication number: 20010049167
    Abstract: A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially perpendicularly from the major surface of the substrate), selectively forming a semiconductor layer around the dielectric pillar, and removing a predetermined length of the dielectric pillar to create a trench in the substrate, the trench defined by sidewalls and a bottom. The method permits the controlled formation of a dielectric plug at the bottom of the trench, the plug having predetermined dimensions.
    Type: Application
    Filed: February 9, 2001
    Publication date: December 6, 2001
    Inventor: Gordon K. Madson
  • Publication number: 20010049168
    Abstract: A DRAM semiconductor device has: a semiconductor substrate with one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of the semiconductor substrate, the first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of the semiconductor substrate, and one of a depth and the first conductivity type impurity concentration of the local maximum of the second well is larger than that of the first well, and the other is at least equal to that of the first well; a memory cell formed in the first well; and a peripheral circuit for the memory cell formed in the second well. A DRAM semiconductor device is provided whose refresh characteristics are improved without deteriorating other characteristics.
    Type: Application
    Filed: March 26, 1999
    Publication date: December 6, 2001
    Inventor: TAIJI EMA
  • Publication number: 20010049169
    Abstract: A semiconductor memory and its manufacturing method enable high-integrated memory cell to be realized easily. The semiconductor memory according to the present invention has an impurity diffusion region with a second conductive type that is opposite to a first conductive type on a surface of a semiconductor substrate with the first conductive type. Further, the semiconductor memory has structure in which there are provided a floating gate electrode formed on the semiconductor substrate via a gate insulator, and a control gate electrode formed on the floating gate electrode via an interelectrode insulating film. Furthermore, there are provided the gate insulator on the surface of the semiconductor substrate with the exception of an impurity diffusion region, and a third insulating film with film thickness thicker than that of the gate insulator on the surface of the impurity diffusion region.
    Type: Application
    Filed: May 2, 2001
    Publication date: December 6, 2001
    Applicant: NEC Corporation
    Inventor: Kazuhiro Tasaka
  • Publication number: 20010049170
    Abstract: The present invention discloses a single poly non-volatile memory structure includeing a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate.
    Type: Application
    Filed: July 26, 2001
    Publication date: December 6, 2001
    Applicant: Mosel Vitelic Inc.
    Inventors: Chun-Lin Chen, Ting-S. Wang, Juinn-Sheng Chen
  • Publication number: 20010049171
    Abstract: A CMOS device includes a reverse electric conduction type well (2) is formed on a monoelectric conduction type semiconductor substrate (1), a first MOS transistor (3) of a reverse electric conduction type channel is formed on a surface of the semiconductor substrate, and a second MOS transistor (4) of monoelectric conduction type channel is formed on a surface of the well. In the present invention, resistance elements (8R, 7R, 2R) are formed in the semiconductor substrate on a lower side of a thick field oxide film (9) covering a surface of the semiconductor substrate. Further, a second resistance element (11R) composed of a polycrystal silicon layer is formed on an upper side of the field oxide film.
    Type: Application
    Filed: May 19, 1999
    Publication date: December 6, 2001
    Inventor: SHIGEKI ONODERA
  • Publication number: 20010049172
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device and a method of manufacture therefor. The method of manufacturing the LDMOS device includes forming an amorphous region in a semiconductor substrate between isolation structures and adjacent a gate structure, by implanting an amorphizing element, such as silicon or germanium, in the semiconductor substrate. The method further includes diffusing a first source/drain dopant laterally in the amorphous region to form a first portion of a channel.
    Type: Application
    Filed: January 4, 2001
    Publication date: December 6, 2001
    Inventor: Charles W. Pearce
  • Publication number: 20010049173
    Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.
    Type: Application
    Filed: January 31, 2000
    Publication date: December 6, 2001
    Inventors: Zhiqiang Wu, Paul Hatab
  • Publication number: 20010049174
    Abstract: A method for configuring an integrated circuit chip having a non-volatile memory having a plurality of registers and a volatile memory includes, the method comprising: storing a plurality of configuration data in the non-volatile memory and, providing power to the volatile memory. After providing power to the volatile memory, serially loading the configuration data into the registers of the volatile memory to configure the semiconductor device.
    Type: Application
    Filed: January 12, 2001
    Publication date: December 6, 2001
    Inventors: Robert L. Pitts, Baher Haroun
  • Publication number: 20010049175
    Abstract: A semiconductor fabrication method is provided for fabricating a resistor and a capacitor electrode in an integrated circuit, which can help enhance the quality of the resultant integrated circuit. In this method, the first step is to form a polysilicon layer. Then, optionally, a first oxide layer is formed over the polysilicon layer. Next, a first ion-implantation process is performed on the entire polysilicon layer so as to convert it into a lightly-doped polysilicon layer with a first predefined impurity concentration. After this, a second ion-implantation process is performed solely on the predefined electrode part of the polysilicon layer so as to convert this part into a heavily-doped polysilicon layer with a second predefined impurity concentration higher than the first impurity concentration. Subsequently, a selective removal process is performed to remove selected parts of the lightly-doped part and the heavily-doped part of the polysilicon layer.
    Type: Application
    Filed: December 1, 1998
    Publication date: December 6, 2001
    Inventors: KUO-LIANG HUANG, I- HO HUANG
  • Publication number: 20010049176
    Abstract: The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal, a second terminal, and a third terminal connected, respectively, to a row line, to a column line, and to a common node by respective connection strips. In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer which covers the connection strips of the first terminals and of the third terminals, the formation of channels along the connection strips until the surfaces thereof are exposed, and the filling of the channels with a material having a resistivity lower than that of the connection strips.
    Type: Application
    Filed: March 2, 2001
    Publication date: December 6, 2001
    Inventors: Massimo Ati, Alfonso Maurelli, Nicola Zatelli
  • Publication number: 20010049177
    Abstract: There is provided a semiconductor device manufacturing method, in which a thin film made of a conductive film or an insulator film is formed on a substrate and then alignment is repeated using photolithography to thereby manufacture a DRAM. In this method, using a third photo-resist film as a mask, an opaque titanium nitride film as an upper capacitor electrode film is removed and then, a fourth photo-resist film is formed in alignment with an alignment mark on the substrate via a first inter-layer insulator film. After this, an upper capacitor electrode is formed using the fourth photo-resist film.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 6, 2001
    Applicant: NEC Corporation
    Inventor: Nobutaka Nagai
  • Publication number: 20010049178
    Abstract: First, a substrate, on which a plurality of semiconductor devices is formed, is provided. Next, a first etching treatment is carried out to the substrate with a first etching gas comprising CF4 to form a base trench having a rounded-off upper edge or tapered upper edge. A second etching treatment is carried out to the substrate to form a trench region at the base trench so that the trench region has a rounded-off upper edge. And then, an insulating layer is formed on the substrate to fill up the trench region therewith.
    Type: Application
    Filed: May 25, 2001
    Publication date: December 6, 2001
    Inventors: Shinzi Kawada, Hiroyuki Kawano
  • Publication number: 20010049179
    Abstract: A method is provided for processing a semiconductor wafer having a chip region where chips are formed and a non-chip region where chips are not normally formed. The method includes the steps of forming trench isolation regions in the semiconductor wafer, and forming dummy trench isolation regions in at least a part of the non-chip region of the semiconductor wafer.
    Type: Application
    Filed: January 17, 2001
    Publication date: December 6, 2001
    Inventor: Katsumi Mori