Patents Issued in January 9, 2003
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Publication number: 20030006805Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage.Type: ApplicationFiled: September 9, 2002Publication date: January 9, 2003Applicant: Xilinx, Inc.Inventors: Farshid Shokouhi, Ben Y. Sheen, Qi Lin
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Publication number: 20030006806Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.Type: ApplicationFiled: June 28, 2002Publication date: January 9, 2003Inventor: Tony T. Elappuparackal
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Publication number: 20030006807Abstract: This invention relates to switching-over to a higher speed clock from a lower speed clock. The switching-over of the clock is performed before, after, or simultaneously to a transition to a sleep mode is carried out. After the switching-over of the clock is performed, if oscillation of the high speed clock and an internal voltage are stabilized, it is returned to a normal mode from the sleep mode.Type: ApplicationFiled: February 13, 2002Publication date: January 9, 2003Applicant: FUJITSU LIMITEDInventors: Masashi Masuda, Hiroyoshi Yamashita, Akio Hara, Kohji Kitagawa
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Publication number: 20030006808Abstract: A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.Type: ApplicationFiled: May 22, 2002Publication date: January 9, 2003Applicant: VIA Technologies, Inc.Inventors: Chih Hsien Weng, Cheng-Yuan Wu, Chen-Hua Hsi
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Publication number: 20030006809Abstract: A capacitor multiplier/time constant circuit transforms (by approximately a scaling constant k) a relatively small valued capacitor to a much larger valued capacitor in circuit with a relatively small valued resistor. A first of a pair of terminals across which an impedance having a reactance component containing a desired value of capacitance is to be supplied is coupled through a first, relatively small valued resistor to the inverting input of a high input impedance operational amplifier, the output of which is fed back in common with its inverting input terminal. The first terminal is further coupled through a second resistor having a resistance that is a scaling constant multiple of the resistance of the relatively small valued reference resistor, to the non-inverting input of the operational amplifier and to one end of a small reference capacitor, a second end of which is coupled to the second terminal, and an AC (ground) node.Type: ApplicationFiled: July 9, 2001Publication date: January 9, 2003Applicant: Intersil Americas Inc.Inventor: Leonel Ernesto Enriquez
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Publication number: 20030006810Abstract: Charge accumulated at an output node of an output transistor is discharged to the ground through the output transistor as a spike current. To reduce noise of the spike current, a control signal is sent from an output transistor driving circuit set to a low impedance to the output transistor in a first driving stage to quickly turn on the output transistor, a control signal is sent from the output transistor driving circuit set to a high impedance to the output transistor in a second driving stage to output the spike current through the output transistor at a fixed rate, and a control signal is sent from the output transistor driving circuit set to a low impedance to the output transistor in a third driving stage to quickly discharge all the charge. Therefore, a time-current characteristic of the spike current is set almost in a trapezoid shape, and both a spike current peak value and a spike current occurrence time period in the spike current can be sufficiently lowered.Type: ApplicationFiled: June 4, 2002Publication date: January 9, 2003Inventor: Katsumi Miyazaki
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Publication number: 20030006811Abstract: An input/output pin for test corresponding to a test circuit of the digital section is used in common as the input/output pin for usual operation of the analog section, the selection switches are respectively provided between the relevant analog pin and analog circuit and on a signal line up to the test circuit of the digital section from the relevant analog pin and the switches are provided at both end portions of the signal line between the test circuit of digital section and the input/output pin for common use in order to fix the voltage of the signal line to the predetermined voltage such as the ground voltage during the usual operation.Type: ApplicationFiled: January 7, 2002Publication date: January 9, 2003Applicant: Hitachi, Ltd.Inventors: Hirotaka Oosawa, Masumi Kasahara, Kazuo Watanabe
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Publication number: 20030006812Abstract: A frequency divider circuit is provided having an even number of amplifier stages connected in series with the output of the the last amplifier stage connected to the input of the first amplifier stage; and modulating means responsive to an input signal to be frequency divided, for modulating the propagation delay through each of the amplifier stages about the period of the input signal to be divided, such that when propagation through the odd amplifier stages increases, the propagation through the even amplifier stages decreases. The frequency divider circuit can be used as a pre-scaler of a radio receiver circuit.Type: ApplicationFiled: April 3, 2000Publication date: January 9, 2003Inventors: James Digby Collier, Ian Michael Sabberton
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Publication number: 20030006813Abstract: A clock signal is supplied from a clock oscillator to a gate circuit. In a period in which a reset signal is at the “H” level, the clock signal is supplied to an internal circuit. When the reset signal becomes at the “L” level, a control is performed by a gate control circuit so as to stop the supply of the clock signal. Consequently, even when a delay signal in the internal circuit becomes longer than one cycle of the clock signal, occurrence of an erroneous operation can be prevented.Type: ApplicationFiled: June 11, 2002Publication date: January 9, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Kouichi Ishimi
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Publication number: 20030006814Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.Type: ApplicationFiled: July 9, 2001Publication date: January 9, 2003Inventor: Vincent R. von Kaenel
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Publication number: 20030006815Abstract: The present invention relates a circuit for generating a digital output signal (56) locked to a phase of an input signal (24), comprising a plurality of delay cells (42), a first register (31) containing a first value, a phase detector (26) and a control logic (25), which is characterized by comprising a plurality of flip-flop devices (37, . . . , 38), wherein storing said first value, a second register (30) containing a second value, a plurality of adder nodes (33) adapted to sum in each of said delay cells (42) said second value with the content of said selected flip-flop device (37, . . . , 38), being said delay cells (42) adapted to provide said digital output signal (56), said phase detector (26), receiving said input signal (24) and said digital output signal (56), adapted to detect the phase difference (27) between said input signal and said digital output signal (56), said control logic (25) adapted to control said first and second value in function of said phase difference (27).Type: ApplicationFiled: June 27, 2002Publication date: January 9, 2003Inventors: Jesus Guinea, Luciano Tomasini
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Publication number: 20030006816Abstract: A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.Type: ApplicationFiled: September 12, 2002Publication date: January 9, 2003Applicant: Hitachi, Ltd.Inventors: Hiroyuki Mizuno, Takahiro Nagano, Yoshinobu Nakagome
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Publication number: 20030006817Abstract: A digital phase interpolator including a plurality of delay stages to control delay time of an output signal from first and second input signals having different phase delays. The plurality of delay stages are connected serially, have a same internal structure, determine corresponding axes for interpolation in each stage, and each includes a first inverting section for inverting first and second signal inputs from the previous stage, a phase blender for blending outputs of the first inverting section, a second inverting section for inverting outputs of the first inverting section, and a multiplexer for generating input signals for the next stage in response to a selection signal for determining phase delay time of the output signal of the phase interpolator. Total area and current may be reduced by the present invention because the number of inverters comprising each stage is equal.Type: ApplicationFiled: November 15, 2001Publication date: January 9, 2003Inventors: Il-Won Seo, Kyu-Hyun Kim
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Publication number: 20030006818Abstract: A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cells connected in series are included, each having a delay time set according to a resistance control voltage and the current control voltage. Also, a variable resistance unit is included having a resistance value adjusted according to the resistance control voltage, where the variable resistance unit includes a cross coupled adjustment device that outputs signals to a next unit delay cell. The delay cells are controlled by using the operational amplifier and a replica cell to have a wide delay range. As a result, the working range can be set wide, jitters may be reduced and the chip size may also be reduced.Type: ApplicationFiled: May 6, 2002Publication date: January 9, 2003Inventors: Se Jun Kim, Sang Hoon Hong
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Publication number: 20030006819Abstract: A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.Type: ApplicationFiled: September 11, 2002Publication date: January 9, 2003Inventors: Yusuke Nitta, Toshihiro Hattori
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Publication number: 20030006820Abstract: An output current limiter circuit is effectively insensitive to variations in temperature. A first arm of each of an NPN and a PNP network has a first auxiliary resistor, the current through which is proportional to temperature, and compensates for the negative temperature coefficient of the base-emitter voltage of that arm's (NPN or PNP) transistor, as well as tracks the positive temperature variation in the Vbe-bias control resistor in the other arm of the network. The other arm includes a second additional resistor, the voltage across which is established by a (fixed) bandgap voltage device, that uses a current from which the current through the first arm of the network is derived.Type: ApplicationFiled: July 9, 2001Publication date: January 9, 2003Applicant: Intersil Americas Inc.Inventor: Leonel Ernesto Enriquez
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Publication number: 20030006821Abstract: An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circuit coupled to receive the select signals and coupled to an output node of the passgate circuit. If none of the select signals is asserted, the default circuit supplies a default voltage on the output node. Other passgate circuits and default circuits may be included coupled to other subsets of the input signals and select signals, and an output circuit may be included with inputs coupled to the output nodes of the passgate circuits. The default voltage may represent a logical value which allows the value from another passgate circuit to control the output of the output circuit.Type: ApplicationFiled: July 9, 2001Publication date: January 9, 2003Inventors: Robert Rogenmoser, Lief O'Donnell
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Publication number: 20030006822Abstract: The invention provides a temperature-compensating circuit which comprises first degree and second degree temperature-coefficient-generating circuits respectively comprising an operational amplifier and a plurality of resistors each having different temperature coefficient, a sign-inverting circuit, and first degree and second degree temperature-coefficient-adjusting circuits. Resistance values of the resistors of the first degree and second degree temperature-coefficient-generating circuits are decided so that voltage amplification factors are linearly or quadratically changed as a temperature changes. The sign-inverting circuit inverts signs of temperature coefficients generated by the first degree and second degree temperature-coefficient-generating circuits and the first degree and second degree temperature-coefficient-adjusting circuits adjust temperature coefficients generated by the first degree and second degree temperature-coefficient-generating circuits to predetermined values.Type: ApplicationFiled: September 18, 2001Publication date: January 9, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Mitsumasa Murakami, Masaya Hara
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Publication number: 20030006823Abstract: When a stage increasing signal, which is input into a sub boosting circuit, is at the L level, three boosting stages are used within the sub boosting circuit to boost a supply potential. On the other hand, when the stage increasing signal is at an H level, four boosting stages are used within the sub boosting circuit to boost the supply potential. Thus, by the semiconductor integrated circuit device of the invention, an internal potential can be boosted at a high speed while power consumption can be reduced.Type: ApplicationFiled: November 16, 2001Publication date: January 9, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yoshitsugu Dohi, Akira Hosogane
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Publication number: 20030006824Abstract: A four-phase charge pump circuit suitable for use on integrated circuits, such as flash memory devices, includes circuitry that drives charge pump nodes in two components separated by a time delay. The two components can be triggered by edges from the clocks that control the timing of the charge pump. Driving the charge pump nodes in two components separated by a delay decreases the peak current of the charge pump and improves noise characteristics of a voltage supply or ground line connected to the charge pump.Type: ApplicationFiled: August 2, 1999Publication date: January 9, 2003Inventors: YU SHEN LIN, CHUN-HSIUNG HUNG, RAY-LIN WAN
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Publication number: 20030006825Abstract: A charge pump circuit includes a plurality of serially connected pump stages. Each pump stage includes current paths connected between a gate terminal of a charge transfer transistor and a drain terminal thereof. One of the charge transfer paths allows charges to be transferred from the drain terminal to the gate terminal while the other path allows charges to be transferred from the gate terminal to the drain terminal. The charge pump circuit can generate a high target voltage using a very low power supply voltage (e.g., 2V or lower).Type: ApplicationFiled: January 22, 2002Publication date: January 9, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Byeong-Hoon Lee, Seung-Keun Lee, Seung-Won Lee
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Publication number: 20030006826Abstract: To mitigate against base current errors in a current mirror circuit that has limited overhead voltage, a compensated current mirror circuit includes a complementary polarity base current error reduction and auxiliary turn-on circuit, that provides an overhead voltage that enjoys a base-emitter diode drop improvement over the overhead voltage of a conventional circuit. Due to the base current error-reduction transistor in the circuit path from the power supply rail to the input port, the overhead voltage is improved by a base-emitter diode drop larger than the overhead voltage of the conventional circuit. In addition, it further reduces base current error.Type: ApplicationFiled: July 9, 2001Publication date: January 9, 2003Applicant: Intersil Americas Inc.Inventor: Leonel Ernesto Enriquez
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Publication number: 20030006827Abstract: A current control circuit capable of maintaining constant current characteristics with respect to a wide range of power source potential fluctuations, comprising: a first resistor (R7) with one end connected to a source potential (VDD); a first and second P-channel field-effect transistors (FETs) (MP10, MP11), each having a source connected to the other end of the first resistor and a gate coupled to a gate of the other P-channel FET, the first P-channel FET (MP10) having a drain directly connected to the mutually coupled gates; a second resistor (R6) through which a drain of the second P-channel FET (MP11) is connected to the mutually coupled gates; and a resistor element (R3P) through which the mutually coupled gates are connected to the zero potential, wherein a voltage arising at the drain of the second P-channel FET (MP11) is used as a gate-driving voltage for driving a gate of a current-setting transistor.Type: ApplicationFiled: June 11, 2002Publication date: January 9, 2003Inventor: Shinichi Watanabe
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Publication number: 20030006828Abstract: The invention relates to an arrangement for forming a reciprocal value of an input current (Iin), comprising: a power supply source (22); a current source (21) for generating a current (I0) for adjusting at least one operating point; a diode circuit with two devices operating as diodes (30, 31 and Q1, Q2), which are coupled in series; a transistor (Q3), in which a base of the transistor (Q3) is coupled between the diode circuit and the current source and in which a collector of the transistor (Q3) is coupled between the current source and the power supply source; and a further transistor (Q4), in which a base of the further transistor (Q4) is coupled to an emitter of the transistor (Q3) and an input current terminal and in which an emitter of the further transistor (Q4) is connected to the input current terminal of the diode circuit and the power supply source in such a way that an output current (Iout) flowing through the collector of the further transistor (Q4) is proportional to the reciprocal value of theType: ApplicationFiled: July 2, 2002Publication date: January 9, 2003Inventor: Cord-Heinrich Kohsiek
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Publication number: 20030006829Abstract: A power device with integrated voltage stabilizing circuit, comprising a MOS transistor that is connected in parallel to a circuit that is integrated in a power device, at least one Zener diode with a series-connected resistor being connected in parallel to the transistor, the gate terminal of the transistor being connected to an intermediate node between the Zener diode and the resistor, the anode terminal of the Zener diode and the drain terminal of the transistor being connected to an input voltage of the circuit.Type: ApplicationFiled: July 5, 2002Publication date: January 9, 2003Applicant: STMicroelectronics S.R.L.Inventors: Antonino Alessandria, Leonardo Fragapane
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Publication number: 20030006830Abstract: In a resistance control circuit, each source electrode of the first and second MOSFETs is connected to VDD, respectively, the first current source is connected to a point between a drain electrode of the first MOSFET and the ground, a non-reverse input terminal of an operation amplifier is connected to a drain electrode of the first MOSFET, and an output terminal of the operation amplifier is connected to the first and second MOSFETs. A voltage applying device applies a predetermined voltage to the reverse input terminal of the operation amplifier so that the MOSFETs is operated in MOS Ohmit region.Type: ApplicationFiled: July 9, 2002Publication date: January 9, 2003Applicant: A&CMOS COMMUNICATION DEVICE INC.Inventor: Shuhei Kawauchi
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Publication number: 20030006831Abstract: This band-gap circuit overcomes the deficiencies of conventional band-gap circuits by compensating for higher order temperature effects, thereby increasing accuracy. A first resistor network including two resistors is connect to a first transistor while a second resistor network that includes one resistor is connected to a second transistor. One resistor in the first resistor network has a high temperature sensitivity, and therefore produces a temperature dependent ratio of currents through the transistors. The inverting input and noninverting input of an operational amplifier are coupled to the collectors of the two transistors. The emitter region of the second transistor is coupled to two additional resistors which are connected in series to each other. The emitter region of the first transistor is coupled to the junction between these two additional resistors. The output of the operational amplifier is coupled to the bases of the transistors.Type: ApplicationFiled: June 28, 2001Publication date: January 9, 2003Inventor: Edmond P. Coady
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Publication number: 20030006832Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.Type: ApplicationFiled: July 23, 2002Publication date: January 9, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Tamio Ikehashi, Yoshihisa Sugiura, Kenichi Imamiya, Ken Takeuchi, Yoshihisa Iwata
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Publication number: 20030006833Abstract: A first transistor is turned on during operation of a circuit block, to connect a substrate of the transistor to a first substrate voltage line. A second transistor is turned on during non-operation of the circuit block, to connect the substrate of the transistor to a second substrate voltage line. ON resistance of the second transistor is higher than that of the first transistor. A source-to-substrate voltage of the transistor being not in operation is set to be higher than that of the transistor being in operation. When a semiconductor integrated circuit switches from the operation state to the non-operation state, its substrate voltage changes gradually to a second substrate voltage. Charging/discharging currents of the substrate voltage can be dispersed so that it is possible to suppress current consumption in shifting from the operation state to the non-operation state and reduce a standby current in the non-operation state.Type: ApplicationFiled: December 19, 2001Publication date: January 9, 2003Applicant: Fujitsu LimitedInventors: Toru Koga, Shinichi Yamada, Masato Takita
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Publication number: 20030006834Abstract: A transconductor which has a transconductance gm and which receives an input voltage Vin and outputs in response to the input voltage Vin an output current Iout of gm×Vin, wherein: the transconductor includes a plurality of sub-transconductors which are connected in parallel to one another; and at least one control signal is input to the plurality of sub-transconductors, and the plurality of sub-transconductors are controlled by the at least one control signal such that at least one of the plurality of sub-transconductors has a negative transconductance, whereby the transconductance gm of the transconductor can be varied.Type: ApplicationFiled: September 9, 2002Publication date: January 9, 2003Inventors: Takashi Morie, Shiro Dosho
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Publication number: 20030006835Abstract: An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.Type: ApplicationFiled: January 3, 2002Publication date: January 9, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Cheol Lee, Yong Jin Yoon, Kwang Jin Lee
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Publication number: 20030006836Abstract: A transconductance stage includes at least one principal bipolar transistor having a base linked to an input terminal, a collector linked to an output terminal, and an emitter linked to a supply terminal through a resistor. At least one bipolar compensation transistor is connected in parallel to the principal transistor and linked without going through the resistor to the supply terminal. The value RE of the resistance is chosen so that RE*I0>VT/2, where VT is the thermal voltage and I0 is the quiescent current of the principal transistor.Type: ApplicationFiled: April 17, 2002Publication date: January 9, 2003Applicant: STMicroelectronics S.A.Inventors: Bruno Pellat, Jean-Charles Grasset
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Publication number: 20030006837Abstract: A ternary modulation scheme for filterless switching amplifiers with reduced EMI reduces the common mode component of the signal by allowing only one state with zero differential voltage across the load to exist. The ternary modulation scheme is more efficient than the quaternary modulation scheme when applied to class-D filterless switching amplifiers since the gates of the power MOSFETs are being charged and discharged at only a small duty cycle instead of 50% duty cycle.Type: ApplicationFiled: July 6, 2001Publication date: January 9, 2003Inventors: Michael D. Score, Paras M. Dagli, Roy C. Jones, Wayne T. Chen
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Publication number: 20030006838Abstract: Disclosed herewith is a multi-channel digital amplifier. The multi-channel digital amplifier includes a PWM converter, switching circuits, and low pass filters. The PWM converter converts an input signal to N low power PWM signals (N is two or more). The switching circuits amplifies the N low power PWM signals to generate N high power PWM signals. The low pass filters convert the N high power PWM signals to analog signals inputted to a plurality of speakers. The phases of the N low power PWM signals are made to be different from each other to make the on/off times of the semiconductor switching elements of the switching circuit to be different.Type: ApplicationFiled: June 3, 2002Publication date: January 9, 2003Inventors: Choi Yeongha, Park Kyoungsoo, Sung Koeng-Mo
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Publication number: 20030006839Abstract: In an extended range amplifier, a simplified feedback system is provided to control a voltage control attenuator (or voltage control variable gain amplifier). The feedback loop may be embodied in analog or digital form. An input signal is applied to a variable gain or variable attenuating amplifier and, preferably, to a linear diode detector. The system logarithmic output is taken from the variable controlled device, and the linear diode detector supplies a linear output. The linear output from the diode detector is compared with a reference level. A resulting error signal is used to control the attenuation of the voltage control attenuator. In this matter, the simplified, reliable adjustment of extended dynamic range of amplification and power measurement are provided. The selection of reference level of the attenuator or amplifier will determine the gain of the amplifier.Type: ApplicationFiled: June 28, 2001Publication date: January 9, 2003Inventor: Paul P. Chominski
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Publication number: 20030006840Abstract: The invention relates to a method of amplifying an input signal having a DC component and an AC component, including the following steps:Type: ApplicationFiled: July 3, 2002Publication date: January 9, 2003Inventors: Eric Bernard Marie Francois Desbonnets, Guillaume Lebailly
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Publication number: 20030006841Abstract: A multiple input, fully differential amplifier. Embodiments make use of complementary differential transistors pairs connected with cascode transistors to form folded cascode pairs, to achieve wide common mode range, high common mode rejection, and high gain.Type: ApplicationFiled: June 28, 2001Publication date: January 9, 2003Inventors: Aaron K. Martin, Stephen R. Mooney
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Publication number: 20030006842Abstract: Two transistors are coupled in a cascode topology between a load resistor and a first current source. A third transistor is coupled between the cascode transistor output terminal and a second current source. The current provided by the second current source causes a constant voltage drop across the load resistor and consequently a steady offset voltage at the cascode transistor output terminal. When the control transistor in the cascode circuit switches on, the current provided by the first current source provides an additional voltage drop at the cascode transistor output terminal.Type: ApplicationFiled: July 3, 2001Publication date: January 9, 2003Inventors: Andy Turudic, William H. Davenport
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Publication number: 20030006843Abstract: A voltage amplifying circuit (100) that may have a selectable gain has been disclosed. Voltage amplifying circuit (100) may include a voltage amplifier (2) and a gain changing unit (7). A gain changing unit (2) may be capable of changing at least one of: a capacitance between a signal input terminal (6) and an input terminal of a voltage amplifier, the capacitance between an input terminal of a voltage amplifier and a ground (or reference potential), and a capacitance between an input and an output terminal (3) of a voltage amplifier. In this way, a gain from a signal input terminal (6) to an output terminal (3) of a voltage amplifier of a voltage amplifying circuit (100) may be changed.Type: ApplicationFiled: July 3, 2002Publication date: January 9, 2003Inventors: Shiro Tsunai, Akira Uemura
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Publication number: 20030006844Abstract: The present invention relates to an amplifier CD including a first and a second transistor T1 and T2, connected in series between a power supply terminal VCC and ground terminal. According to the invention the transfer terminal of the first transistor T1 is connected to the bias terminal of the second transistor T2 and forms an input of the amplifier CD, the bias terminal of the first transistor T1 being connected to a reference potential terminal. An amplifier CD in accordance with the invention has low input impedance and a low common-mode output level.Type: ApplicationFiled: June 3, 2002Publication date: January 9, 2003Inventors: Fabio Braz, Patrick Leclerc, Lionel Guiraud
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Publication number: 20030006845Abstract: A power amplifier circuit whose performance is optimized by operating its stages in substantially close to a Class B mode by reducing quiescent current during low driver signal levels. As the driver signal amplitude increases, the operation of the amplifier is configured to dynamically adjust to be in a Class AB mode, thereby increasing the power efficiency of the overall circuit at kiw drive levels. A further enhancement to the power amplifier circuit includes a temperature compensation circuit to adjust the bias of the amplifier so as to stabilize the performance in a wide temperature range.Type: ApplicationFiled: July 29, 2002Publication date: January 9, 2003Inventors: Osvaldo Jorge Lopez, Robert Bayruns, Mahendra Singh
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Publication number: 20030006846Abstract: A biasing system for biasing an electronic circuit includes a resistance connected in series with a transmission line which has a characteristic impedance substantially equal to the resistance and comprises a conductive line and a plurality of current sources distributed along the conductive line. The biasing system can be used as a biasing and/or matching supply for any type of broad-band low-noise power application requiring high bias currents.Type: ApplicationFiled: June 25, 2002Publication date: January 9, 2003Applicant: ALCATELInventors: Wissam Mouzannar, Rene Lefevre
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Publication number: 20030006847Abstract: A small aspect ratio, high power MMIC amplifier is disclosed. The small aspect ratio MMIC amplifier is capable of achieving the same power levels as conventional power amplifier designs, but with an aspect ratio of near 1:1, versus 4:1 of conventional power amplifiers. The small aspect ratio MMIC amplifier layout uses two different types of FETs, with all gate fingers of both types of FETs running in the same direction. One type of FET is a conventional FET, in which the gate stripes run parallel to the direction of the output. In the conventional FET, the gate manifold and the drain manifold both generally extend in the x-direction (parallel to each other). The other type of FET has gate fingers that run perpendicular to the direction of the output. In this other type of FET, the gate manifold generally extends in the x-direction, while the drain manifold generally extends in the y-direction (perpendicular to each other).Type: ApplicationFiled: July 6, 2001Publication date: January 9, 2003Applicant: Nanowave, Inc.Inventor: Stephen R. Nelson
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Publication number: 20030006848Abstract: A phase-locked loop synthesizer (8) has a charge pump (9) and a loop filter (22) with a frequency preset capacitor (27). The synthesizer (8) has a transistor (34) of which one main electrode (36) is connected to the frequency preset capacitor. Another main electrode (35) of the transistor (34) is connected to a power-up terminal (32) that is also connected to the charge pump (21). Upon powering up, the transistor (34) causes the frequency preset capacitor (27) to quickly charge before a first pulse of the charge pump (21).Type: ApplicationFiled: January 8, 2002Publication date: January 9, 2003Inventor: Jose Luis Cordoba
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Publication number: 20030006849Abstract: A random number generator on an integrated circuit has a first clock generator circuit with a first voltage supply for generating a first signal of a first frequency or of a first frequency range. A second clock generator circuit has a second voltage supply for generating a second signal of a second frequency or of a second frequency range, such that the second frequency or a mean value of the second frequency range is lower than the first frequency. A generator samples the first signal with the second signal and-generates at least one random number in dependence on the result of the sampling. The clock generator circuits are located as far away from one another as possible on the integrated circuit and/or the two voltage supplies are isolated from one another and/or at least one guard ring is placed around each of the clock generator circuits.Type: ApplicationFiled: July 29, 2002Publication date: January 9, 2003Inventor: Norbert Janssen
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Publication number: 20030006850Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.Type: ApplicationFiled: May 21, 2002Publication date: January 9, 2003Applicant: The National University of SingaporeInventors: Kin Mun Lye, Jurianto Joe
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Publication number: 20030006851Abstract: Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in travelling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact, as does two-way simultaneous data transfer.Type: ApplicationFiled: April 6, 2000Publication date: January 9, 2003Inventor: JOHN WOOD
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Publication number: 20030006852Abstract: Techniques and apparatus for causing electromagnetic interaction between an oscillator and a quantum ensemble with transition moments to transfer energy. In implementation, a mechanical oscillator with an electromagnetically polarized moving part is placed close to the quantum ensemble to extract energy from said quantum ensemble so as to reduce an entropy of the quantum ensemble.Type: ApplicationFiled: May 16, 2002Publication date: January 9, 2003Inventor: Daniel P. Weitekamp
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Publication number: 20030006853Abstract: Excitation electrodes are respectively affixed to central portions of both surfaces of a long plate-shaped AT-cut crystal resonator, the central portion starts a thickness shear oscillation in the length direction of the crystal resonator when an electric signal is applied to the central portion of the crystal resonator through the excitation electrodes. And, channel-shaped, half-circular-shaped, or trapezoid grooves in cross-section are respectively formed in the plate width direction on middle portions between the center portion and end portions of the crystal resonator. These grooves are formed so as to be symmetrical with respect to a thicknesswise central position of the crystal resonator through a well-known etching technique such as photo-etching and the like.Type: ApplicationFiled: June 5, 2002Publication date: January 9, 2003Inventors: Masami Yamanaka, Motoyuki Adachi, Akio Chiba, Kozo Ono
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Publication number: 20030006854Abstract: A voltage controlled oscillator (VCO) for connection and operation in a phase locked loop arrangement has two or more operational states in each of which the VCO circuit is operable to provide activation of a selected one of two or more different phase locked loops when connected to the VCO circuit, the VCO circuit including switching means for switching the state of the VCO circuit to allow the operational state of the VCO to be selected.Type: ApplicationFiled: May 23, 2002Publication date: January 9, 2003Inventors: Moshe Ben-Ayun, Mark Rozental, Gabi Nocham