Abstract: A flash EEPROM having an array of memory cells which include a common source line connecting together source electrodes of the memory cells. A resistive feedback element is coupled in series between the common source line and a positive potential when the memory cells must be electrically erased. The Flash EEPROM includes a voltage limiting circuit coupled to the common source line for limiting the potential of the common source line to be prescribed maximum value lower than the positive potential.

Abstract: A NOR-type flash memory device includes a source region, a drain region and a source line connecting the source region of a memory cell transistor to an source region of an adjacent memory cell transistor in the form of diffusion regions formed in a substrate, wherein the drain region and the source line are formed simultaneously after the step of forming the source region.

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract: A semiconductor device (10) is formed that is bi-lateral and has a voltage blocking capability that is well suited to applications involving portable electronics. The semiconductor device has an epitaxial layer (14) that is formed on a semiconductor substrate (11). A doped region (24) is formed that extends from a top surface (16) of the epitaxial layer (14) to the underlying semiconductor substrate (11). The semiconductor device (10) has a source region (31) that is separated from the doped region (24) to provide a channel region (29). The channel region (29) is modulated by a gate structure (20) to determine if a current flow should be allowed through semiconductor device (10) or if semiconductor device (10) is to provide voltage blocking capability.

Abstract: A lateral high-voltage sidewall transistor configuration includes a low-doped semiconductor substrate of a first conductivity type and a low-doped epitaxial layer of a second conductivity type disposed on the semiconductor substrate. First semiconductor layers of the first conductivity type and second semiconductor layers of the second conductivity type are disposed in an alternating configuration in the epitaxial layer. A source region and a drain region of the second conductivity type extend through the first and second semiconductor layers as far as the semiconductor substrate. A gate electrode includes a gate insulating layer lining a gate trench and includes a conductive material which fills the gate trench. The gate electrode extends through the first and second semiconductor layers as far as the semiconductor substrate and is disposed adjacent to the source region toward the drain region.

Abstract: In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, By existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

Abstract: MOS semiconductor device including a substrate having source and drain regions laterally spaced from one another and a channel therebetween, a gate electrode over the channel and an oxide layer. The oxide layer includes a gate oxide layer between the gate electrode and the substrate, an oxide film having a having a thickness greater than a thickness of the gate oxide layer and a boundary oxide layer between the gate oxide layer and oxide film. The boundary oxide layer has a thickness between the thickness of the gate oxide layer and the thickness of the oxide film. The oxide film boundary oxide layer are formed by selective oxidation before formation of the gate electrode. The gate electrode has end portions extending over a portion of the oxide film while receiving no distortion from the boundary oxide layer to thereby improve breakdown voltage performance at the end portions of the gate electrode.

Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

Abstract: Methods of forming a MOS transistor and a MOS transistor fabricated thereby are provided. The MOS transistor includes a semiconductor substrate of a first conductivity type, and an insulated gate pattern having sidewalls disposed on a predetermined region of the semiconductor substrate of a first conductivity type so that portions of the semiconductor substrate of a first conductivity type on at least one side of the insulated gate pattern remain uncovered by the insulated gate pattern. The MOS transistor also includes impurity regions having at least an upper surface of a second conductivity type disposed on the semiconductor substrate at at least one side of the insulated gate pattern, as well as at least one spacer disposed on at least one sidewall of the insulated gate pattern. The MOS transistor further contains a pad of a second conductivity type disposed on an upper surface of the impurity regions, whereby the pad covers a lower portion of the at least one spacer.

Abstract: A semiconductor transistor which is burned in by a burn-in signal having a burn-in frequency higher than a thermal transient response frequency of a transistor used at an operating frequency in the microwave region, and supplying the burn-in signal to the transistor, wherein the burn-in signal has a frequency lower than the operating frequency of the transistor and higher than a response frequency of impurities included in the transistor, and the operating frequency is higher than 1 GHz.

Abstract: A voltage nonlinear resistor is composed of an aggregate of silicon carbide particles doped with impurities, in which oxygen and at least one of aluminum and boron are diffused in the vicinity of the surfaces of the silicon carbide particles, the diffusion length of the oxygen is about 100 nm or less from the surfaces of the silicon carbide particles, and the diffusion length of at least one of the aluminum and the boron is in the range of about 5 to 100 nm from the surfaces of the silicon carbide particles. A method for fabricating a voltage nonlinear resistor and a varistor using a voltage nonlinear resistor are also disclosed.

Abstract: A MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon structure disposed on a gate dielectric over the channel region. A drain silicide and a source silicide having a first silicide thickness are formed in the drain region and the source region, respectively. A dielectric layer is deposited over the drain region, the source region, and the gate. The dielectric layer is polished until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. The capping layer on the polysilicon structure of the gate is etched away such that the top of the polysilicon structure is exposed. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon structure are exposed. A polysilicon spacer is formed at the exposed sidewalls at the top portion of the polysilicon structure.

Abstract: A static semiconductor memory device capable of preventing soft errors is provided. The static semiconductor memory device includes: a silicon substrate having a p-type well region; a storage node; an n-type-low-concentration impurity region and a high-concentration impurity region formed in the surface of p-type well region and connected to storage node; and a p-type impurity region formed to have contact with high-concentration impurity region.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximatethe edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: A structure to enable damascene copper semiconductor fabrication is disclosed. There is a silicon nitride film for providing a diffusion barrier for Cu as well as an etch stop for the duel damascene process. Directly above the silicon nitride film is a silicon oxynitride film. The silicon oxynitride film is graded, to form a gradual change in composition of nitrogen and oxygen within the film. Directly above the silicon oxynitride film is silicon oxide. The silicon oxide serves as an insulator for metal lines. Preferably, the film stack of silicon nitride, silicon oxynitride and silicon oxide is all formed in sequence, within the same plasma-processing chamber, by modifying the composition of film-forming gases for forming each film.

Abstract: A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.

Abstract: An image sensor has a light-shielding layer with openings corresponding to an array of light-sensing elements formed below on a substrate. Light-reflecting material is applied to form (e.g., vertical) via walls between each opening in the light-shielding layer and the corresponding light-sensing element. Light having a non-normal angle of incidence will reflect off the vertical light-reflecting via structures towards the light-sensing elements. As such, substantially all of the light that passes through an opening in the light-shielding layer will reach the light-sensing element, even light incident at relatively low angles, thereby reducing the problem of pixel vignetting associated with prior art image sensors. As a result, the image sensor has a greater and more uniform sensitivity across the entire sensor array.

Abstract: A semiconductor light-receiving element fabricated by using an impurity diffusion, in which a slow tail phenomenon caused in the processing of a digital signal may be suppressed. The semiconductor light-receiving element comprises a substrate including a first impurity diffused region, a first electrode provided on the bottom of the substrate, a second electrode provided on the first impurity diffused region, a second impurity diffused region provided so as to surround the first impurity diffused region with leaving a certain space therebetween, and a third electrode provided on the second impurity diffused region, wherein a reverse vias is applied to a PN junction formed by the substrate and the second impurity diffused region.

Abstract: A semiconductor device is provided which minimizes a reduction in the breakdown voltage caused by a metal electrode to which a high voltage is applied. An n− semiconductor layer (3) is formed on a p− semiconductor substrate (1). A p+ impurity region (4) is formed within the n− semiconductor layer (3), extending from the surface of the n− semiconductor layer (3) to the interface of the n− semiconductor layer (3) and the p− semiconductor substrate (1). The p+ impurity region (4) is formed to surround part of the n− semiconductor layer (3) and forms a high-potential island region (101) where a logic circuit (103), an n+ impurity region (5) which is a cathode region of a bootstrap diode (102), and a p+ impurity region (6) which is an anode region are located.

Abstract: A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure.

Abstract: A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.

Abstract: A power semiconductor device of the present invention comprises a voltage drive type power MOS transistor, a series connection of a first resistor and Zener diode, a second resistor, and a series connection of a third resistor and MOS transistor. The power MOS transistor has a gate, source and drain. A drain-to-source voltage of the power MOS transistor is applied across the series connection of the first resistor and Zener diode. A gate-to-source voltage of the power MOS transistor is applied across the second resistor. The gate-to-source voltage of the power MOS transistor is applied across a series connection of a third resistor and the MOS transistor. The MOS transistor has a gate, source and drain. The gate of the MOS transistor is connected to a node between the first resistor and the Zener diode.

Abstract: A semiconductor device is provided with a plurality of hetero junction bipolar transistors arranged in a specified direction. Also, the semiconductor device comprises emitter wiring connected to each emitter of the plural hetero junction bipolar transistors, collector wiring connected to each collector of said plural hetero junction bipolar transistors, and base wiring connected to at least one base of said plural hetero junction bipolar transistors. Bases that are not connected to the base wiring among the bases of the plural hetero junction bipolar transistors are connected to the emitter wiring.

Abstract: A method and a structure of for an Electro Static Discharge (ESD) device that is silicided. There are three preferred embodiments of the invention. The first embodiment has a N/P/N structure. The emitter, the collector and the substrate form a parasitic transistor and the substrate is connected to the p+ diffusion region. The emitter and the substrate act as a first diode D1 and the collector and the substrate act as a second diode D2. The second embodiment has a first N+ well between a second n+ (collector) region and a P+ base region. The Vt1 is controlled by the dopant profiles of the P+ base and the n− first well where they intersect. The third embodiment is similar to the second embodiment, but the n− well covers all of drain. A parasitic NPN bipolar transistor comprises: an emitter, a parasitic base and a drain. The emitter is formed by the first n+ region. The parasitic base is formed by the p-substrate.

Abstract: An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1−xGex alloy into which indium is implanted, with 10−5≦x≦4×10−1. A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si1−xGex alloy layer, in which 10−5≦x≦4×10−1, and an external silicon layer. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided.

Abstract: A semiconductor device is provided, which device includes a semiconductor chip including external terminals formed on a surface thereof and a sealing resin formed on the surface of the semiconductor chip. A contaminant film formed on the surface of said semiconductor chip has a laser-processed edge so that a peripheral portion of the surface of said semiconductor chip is bonded to the sealing resin.

Abstract: A lead frame and a semiconductor device fabricated by using the same. The lead frame comprises: first and second band shaped members disposed parallel to each other; a plurality of island portions for mounting semiconductor pellets thereon having first end portions connected to the first band shaped member; coupling strip each provided for one of the island portions whose first end portion connects to a second end portion of each of the island portions and whose second end portion connects to the second band shaped member. The lead frame further comprises at least one electrode portion for each of the island portions and electrically coupled with a corresponding electrode of the semiconductor pellet. The at least one electrode portion is disposed between each of the island portions and the second band shaped member, a first end portion thereof is connected to the second band shaped member, and a second end portion thereof is opposed to the second end portion of each of the island portions.

Abstract: A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: A wiring board comprises a substrate (10) in which an opening (14) is formed, a wiring pattern (20) formed on one surface of the substrate (10) and having a bent portion (22) intruding into the opening (14) and protruding from the other surface of the substrate (10), and a resin 26 with which an inside of the bent portion (22) is filled and allowing deformation to a certain degree while preventing large deformation, and the bent portion (22) forms the external terminals of the semiconductor device.

Abstract: A tape having implantable conductive lands, which realizes a new structure in which an organic rigid substrate is removed from a semiconductor package in a semiconductor packaging process, and a method for manufacturing the tape are provided. The tape includes a tape film, which can be detached from a semiconductor package after an encapsulation process and serves as a general rigid substrate until the encapsulation process is completed, and implantable conductive lands adhering to the tape film.

Abstract: A hermetic package for a pyroelectric-sensitive electronic device and methods of manufacturing one or more of such packages. In one embodiment, the package includes: (1) a device substrate having: (1a) an active region containing an electrically conductive pattern that constitutes at least a portion of the device and (1b) a bonding region surrounding the active region, (2) a non-porous mounting substrate having a bonding region thereon and (3) a nonmetallic hermetic sealing adhesive, located between the bonding region of the device substrate and the bonding region of the mounting substrate, that cures at a temperature substantially below a pyroelectric sensitive temperature of the device, the active region proximate a void between the device substrate and the mounting substrate.

Abstract: A multi-chip packaging structure in which a plurality of chips is aligned on two surfaces of a substrate and the substrate has an opening. The chip located on the second surface of the substrate has center bonding pads arrangement. These bonding pads are connected to the conductive connections on the first surface of the substrate by means of the opening. The other chips are attached to the first surface of the substrate and have a plurality of bonding pads connected to the conductive connections on the first surface of the substrate by wire bonding or flip-chip bonding. Furthermore, a heat sink is attached to the back surface of the chip located on the second surface in order to improve the heat dissipation performance of the package.

Abstract: An integrated circuit carrier includes a plurality of receiving zones. Each receiving zone includes electrical contacts and each receiving zone is configured to receive a particular type of integrated circuit. A plurality of island-defining portions is arranged about each receiving zone. Each island-defining portion has an electrical terminal electrically connected to one electrical contact of its associated receiving zone. A rigidity-reducing arrangement connects each island-defining portion to each of its neighboring island-defining portions.

Abstract: A packaging substrate is formed with electrically non-functional areas of Cu on the upper surface and/or lower surface for improved strength and rigidity and reduced warpage and bending. Embodiments of the present invention include substrates containing electrically non-functional grid-like Cu areas on the upper and lower surface such that the ratio of the total Cu area on one surface is about 55% to about 100% of the total Cu area on the other surface.

Abstract: A low-cost EMI shield that fits around an integrated circuit package to absorb electromagnetic energy and dissipate it as heat. The shield is not ohmically conductive so it may contact electrically active conductors without affecting the operation of the circuit. EMI is prevented from being radiated by and around an integrated circuit package by a perimeter of material that is lossy to high-frequency electromagnetic currents. This perimeter is fitted around an integrated circuit package such that the gap between a heat sink or other top conductor and the printed circuit board is completely closed by the lossy material. This provides not only a line-of-sight obstruction to RF currents, but also provides a lossy return path to close the circuit loop for currents on the skin of the heat sink. Since the material is lossy, rather than purely conductive, it can be used with a less than perfect ground attachment.

Abstract: A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press.

Abstract: In order to provide a semiconductor device which has a bonding layer capable of providing electrical continuity between the cap and the semiconductor substrate, the semiconductor device comprises a semiconductor substrate whereon an element is formed on one principal plane thereof and a cap which hermetically seals the element so that a space is formed over the element, while the element is sealed by bonding a laminated bonding layer, which is formed around the element provided on the principal plane, and an Ni layer formed on the cap, wherein the laminated bonding layer is constituted from a first polysilicon layer which is doped with an impurity, an insulation layer and a second polysilicon layer which is not doped with an impurity, while the first polysilicon layer and the second polysilicon layer contact with each other in a part thereof so that the impurity diffuses through the contact area from the first polysilicon layer into the second polysilicon layer.

Abstract: A semiconductor package with an embedded heat-dissipating device is proposed. The heat-dissipating device including a heat sink and a plurality of connecting bumps attached to connecting pads formed on the heat sink is mounted on a substrate by reflowing the connecting bumps to ball pads of the substrate. The connecting bumps and the ball pads help buffer a clamping force generated during the molding process, so as to prevent a packaged semiconductor chip from being cracked. Moreover, the reflowing process allows the connecting bumps to be self-aligned on the substrate, so as to assure the toning and planarity of the heat sink mounted thereon. Accordingly, during molding, the precisely-positioned beat sink can have its upper side closely abutting an upper mold, allowing a molding resin to be prevented from flashing on the upper side thereof i.e.

Abstract: A member for semiconductor devices comprising a composite alloy of aluminum or an aluminum alloy and silicon carbide, wherein silicon carbide grains are dispersed in aluminum or the aluminum alloy in an amount of from 10 to 70% by weight, the amount of nitrogen in the surface of the member is larger than that in the inside thereof, and the ratio of aluminum or the aluminum alloy to silicon carbide is the same in the surface and the inside. The member is produced by mixing powdery materials of aluminum or an aluminum alloy and silicon carbide, compacting the mixed powder, and sintering the compact in a non-oxidizing atmosphere containing nitrogen gas, at a temperature between 600° C. and the melting point of aluminum. The member is lightweight and has high thermal conductivity as well as thermal expansion coefficient which is well matches with that of ceramics and others. Therefore, the member is especially favorable to high-power devices.

Abstract: A semiconductor module of the type having a number of semiconductor chips disposed on a chip carrier has at least a second subset of the semiconductor chips disposed above a first subset and conductive connections between the semiconductor chips disposed one above another. The improvement includes flexible tapes forming conductive connections between the first subset of semiconductor chips and the second subset of semiconductor chips. Two of the flexible tapes originate from the first subset and lead to the second subset. The two flexible tapes respectively extend from a contact-making side of the first subset around respectively mutually opposite side faces of the first subset to the second subset.

Abstract: A computer system and a printed circuit board assembly are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between a first active surface of the first semiconductor die and a second active surface of the second semiconductor die. The first semiconductor die is electrically coupled to the intermediate substrate. The intermediate substrate defines a passage there through The second semiconductor die is secured to the second surface of the intermediate substrate within a cavity in the second surface of the intermediate substrate such that the conductive bond pad of the second semiconductor die is aligned with the passage. The second semiconductor die is electrically coupled to the intermediate substrate by at least one conductive line extending from the second semiconductor die through the passage and to the first surface of the intermediate substrate.

Abstract: The invention relates to a power semiconductor module (10) having a baseplate (1) on which at least one substrate (13) is arranged which is fitted with power semiconductor chips (11, 12) and can be pressed via pressure elements and contact cords (17) against the baseplate (1). The baseplate (1) has centering elements on which a frame (3) which defines fields (7) and is in the form of a grid is provided, with corresponding substrates (13) with power semiconductor chips being arranged in at least some of the fields (7), which substrates (13) can be made contact with via contact rails (15).

Abstract: A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.

Abstract: A microwave device, including a substrate having a first surface and a second surface, a plurality of electrically conductive vias extending through the substrate from the first surface to the second surface, a first interconnect trace connected to the first surface of the substrate and electrically connected to a first of the plurality of vias, a second interconnect trace connected to the first surface of the substrate and electrically connected to a second of the plurality of vias, and a microwave circuit chip connected to the second surface of the substrate and electrically connected to the first and second conductive vias.

Abstract: A high-frequency circuit is provided, which makes it possible to prevent degradation of its high-frequency characteristic even if the lengths of bonding wires used are not decreased. This circuit includes: (a) an electronic element having a capacitance; (b) a signal line for transmitting a high-frequency electric signal to the element; (c) a terminating resistor for impedance matching; (d) a first bonding wire for electrically connecting the signal line and the element; and (e) a second bonding wire for electrically connecting the element and the resistor. A characteristic impedance of combination of the element and the first and second bonding wires is equal to or greater than that of input side of the electric signal with respect to the combination. An inductance of the second wire is greater than that of the first wire. Preferably, at least one of the lengths of the first and second bonding wires is decreased, which enhances the advantage of the high-frequency circuit.

Abstract: The present invention provides a bonding structure between a bonding pad and a bonding portion of a bonding wire made of an Au-base material, wherein said bonding pad further comprises: a base layer; at least a barrier layer overlying said base layer; and a bonding layer overlying said at least barrier layer, said bonding layer including an Al-base material, and wherein said bonding portion of said bonding wire is buried in said bonding layer, and an Au—Al alloy layer extends on an interface between said bonding portion and said bonding layer, and a bottom of said Au—Al alloy layer is in contact with or adjacent to an upper surface of said barrier layer.

Abstract: One type of electronic interface structure includes a base; at least one elastomeric island supported by the base; and patterned metallization overlying the at least one elastomeric island and including at least one floating pad at least partially overlying the at least one elastomeric island. Another type of electronic interface structure includes a base; a first dielectric layer overlying the base and having at least one first dielectric layer opening therein; a second dielectric layer overlying the first dielectric layer; and patterned metallization overlying the second dielectric layer and including at least one floating pad at least partially overlying the at least one opening.

Abstract: A BOC (board-on-chip) semiconductor package includes a semiconductor die having die contacts, a substrate bonded circuit side down to the die, and an adhesive layer bonding the substrate to the die. The substrate includes a circuit side having a pattern of conductors and wire bonding sites, and a back side having an array of external contacts (e.g., BGA solder balls) in electrical communication with the conductors. The bonding sites on the conductors overhang the peripheral edges of the substrate such that access is provided for bonding wires to the bonding sites and to the die contacts. Because the substrate is bonded circuit side down to the die, a loop height of the wires, and an overall height (profile) of the package are reduced by a thickness of the substrate. In addition, a planarity of molded segments that encapsulate the wires is improved, and mold bleed during molding of the molded segments is reduced.

Abstract: A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

Abstract: An electronic package and method of making same in which a thermally conductive member is in thermally conductive communication with a semiconductor chip encapsulated within a dielectric material that surrounds portions of a thermally conductive member, semiconductor chip, and a predefined portion of a circuitized substrate. The present invention's thermally conductive member includes two portions of different bending stiffness to assure reduced interfacial stresses between the semiconductor chip and the circuitized substrate.