Patents Issued in January 14, 2003
-
Patent number: 6507167Abstract: The present invention relates to a power factor compensation device for a motor driving inverter which can improve a power factor of a voltage and a current inputted to the inverter driving a motor. The present invention detects a zero crossing point of an utility alternating current power, and outputs a driving signal corresponding to a plurality of sine wave form voltage values stored in a memory according to a detection result, when the zero crossing point of the utility alternating current power is detected in a state where the plurality of sine wave form voltage values corresponding to a voltage of the utility alternating current power and frequencies are stored in the memory. A switching transistor is switched according to the driving signal, and the voltage applied to the inverter is switched according to the switching operation, thereby improving the power factor.Type: GrantFiled: August 27, 2001Date of Patent: January 14, 2003Assignee: LG Electronics Inc.Inventors: Gyeong-Hae Han, Jong-Ho Kim, Keon Sim, Hyung-Sang Lee, Dong-Hyuk Lee
-
Patent number: 6507168Abstract: A battery of an uninterruptible power supply unit 1a is configured by at least two batteries (a first battery 2 and a second battery 21a). A control circuit 12a judges opened/closed states of a first cover 6a and a second cover 25a on the basis of information from a first cover-opening detecting device 7a and a second cover-opening detecting device 11a. When the first cover 6a is opened, a first switch 8 which connects a charge and discharge circuit 3 to the first battery 2 is opened, and, when the second cover 25a is opened, a second switch 10 which connects the charge and discharge circuit 3 to the second battery 21a is opened.Type: GrantFiled: February 5, 2002Date of Patent: January 14, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kensaku Matsuda, Manabu Yamamoto
-
Patent number: 6507169Abstract: A power control system (10) for managing power output from a battery (11) includes an output terminal (12) for delivering power from the battery (11) to a load, control means (14) connected to the battery (11) to sense pre-selected operating parameters of the battery (11), and in a first mode of operation to provide power from the battery (11) to the output terminals (12). A first capacitor (15), which stores a predetermined quantity of power is connected between the control means (14) and the battery (11), supplies its stored power to the battery (11) in response to a signal from the control means (14) which is in a second mode of operation. A second capacitor (16), which stores a predetermined quantity of power and is connected between control means (14) and the output terminals (12), supplies its stored power to the output terminals (12) in response to a signal from the control means (14) in its second mode of operation.Type: GrantFiled: January 23, 2001Date of Patent: January 14, 2003Assignee: Farnow Technologies PTY LimitedInventors: Stephen Wayne Holtom, Goran Abrahamsson, Anna Norlin
-
Patent number: 6507170Abstract: A battery pack includes a case and an adapter contoured to mate with a battery socket of a power-consuming device. The battery socket is formed to receive an intended, standard-sized battery. The battery pack includes positive and negative leads electrically connecting the adapter to the case and two battery slots formed to receive intended, standard-sized batteries in parallel electrical communication with the positive and the negative leads.Type: GrantFiled: September 19, 2001Date of Patent: January 14, 2003Assignee: QuartexInventors: Terrence J. O'Neill, Fred Koermer
-
Patent number: 6507171Abstract: Disclosed is a method for charging a battery and circuitry for performing the method. The method includes steps of: (A) generating at a first node a battery charge current (Icharge) for charging the battery; (B) generating at a second node a replica current (Irep) from Icharge, where Irep<Icharge; and (C) operating a closed loop current sink for sinking Irep, where a digital output of said closed loop current sink is a measure of the magnitude of Icharge. In the preferred embodiment the digital output is input to a control circuit for controlling the generation of Icharge. Also in the preferred embodiment the closed loop current sink is constructed from a multi-stage DAC that is driven by an output of an n-level digital filter that is incremented or decremented as a function of a voltage difference between the first node and the second node. Preferably the multi-stage DAC is a multi-stage current steering DAC, and the n-level digital filter is constructed using an up/down counter.Type: GrantFiled: December 21, 2001Date of Patent: January 14, 2003Assignee: Nokia CorporationInventors: Antti Ruha, Tarmo Ruotsalainen, Jussi-Pekka Tervaluoto, Jani Kauppinen
-
Patent number: 6507172Abstract: Universal serial bus powered battery charger primarily intended for use in battery powered hand-held and other portable devices to charge the battery or batteries within the battery powered device when the same is connected to a host device, powered hub or a bus powered hub through a universal serial bus (USB) port. The battery charger includes one or more current limits to conform to the universal serial bus current supply limit set in the USB specification. Any of the universal serial bus voltage and current limits may be used to charge batteries in the battery powered device, such as single cell lithium-ion batteries. Various features are disclosed.Type: GrantFiled: March 19, 2001Date of Patent: January 14, 2003Assignee: Maxim Integrated Products, Inc.Inventor: Leonard Harris Sherman
-
Patent number: 6507173Abstract: A power management unit (PMU) apparatus and method may include: a bi-directional pin configured to serve as an input pin during a first condition and as an output pin during a second condition; or a battery charge controller for providing a first conditioning charge and a second full charge to a voltage source of the PMU; or an adapter detector configured to detect the presence of a continuous output adapter and a pulse output adapter; an under voltage lockout protection circuit to prevent start up of the PMU until a power source reaches a predetermined threshold lockout level and to shut down the PMU once the power source reaches a lower threshold lockout disabling level; or a plurality of internal switches for allowing an external switch to have multiple functions; or a power on reset circuit; or multi-output charge status pin.Type: GrantFiled: September 13, 2001Date of Patent: January 14, 2003Assignee: 02 Micro International LimitedInventors: Constantin Spiridon, Vlad Mihail Popescu-Stanesti, You-Yuh Shyr, Alexandru Hartular, William L. Densham, III
-
Patent number: 6507174Abstract: A circuit for clamping a voltage across a switching element to a value equal to or less than the sum of the input voltage plus the voltage across a clamping capacitor is provided. The circuit achieves voltage clamping accordance with one embodiment in which an active clamp circuit includes a switch and a clamping capacitor connected in parallel with a first winding of a coupled winding. The active clamp prevents the occurrence of voltage spikes across the switch. The clamping capacitor recovers energy stored in the first winding of the coupled winding. The circuit achieves voltage clamping in accordance with a second embodiment in which a passive clamp circuit includes a switch a clamping capacitor,and first and second diodes. The passive clamp circuit prevents the occurrence of voltage spikes across the switch. The clamping capacitor recovers energy stored in the first winding of the coupled winding.Type: GrantFiled: September 6, 2001Date of Patent: January 14, 2003Assignee: Koninklijke Philips Electronics N.V.Inventor: Jinrong Qian
-
Patent number: 6507175Abstract: The present invention is directed to a circuit that is configured to detect a zero current condition at a certain point. The circuit includes a current mirror coupled to two transistors, where the first transistor is coupled to ground and the second transistor is coupled to the point being sensed. The outputs of both the first transistor and the second transistor are each coupled to an input of a comparator. The comparator is configured to determine when an equal voltage condition is present at the two inputs, which signifies a zero-current condition. Such a zero current detector can be used in a buck regulator to prevent a current flow from load to ground and attendant inefficiencies that result. An alternative embodiment involves the use of a controller to sense three different voltages to determine the state of the switches.Type: GrantFiled: October 15, 2001Date of Patent: January 14, 2003Assignee: Primarion, Inc.Inventors: David Susak, Ryan Goodfellow
-
Patent number: 6507176Abstract: Five circuit synthesis methods, for forming new power conversion circuits with enhanced electromagnetic compatibility and improved AC performance from old circuits with AC performance and/or electromagnetic compatibility deficiencies, are revealed. The new synthesis methods achieve performance improvements without requiring the addition of magnetic cores. In all cases a simple toroidal magnetic core structure is not precluded. In all cases splitting or adding magnetic windings is required, and, in many cases, additional capacitors are required. Many new circuits formed by applying the synthesis methods are revealed. The results achieved by application of the synthesis methods include zero ripple current at all terminals without adding magnetic cores or requiring a complex magnetic circuit element, cancellation of common mode currents, improved control loop bandwidth, and faster transient response.Type: GrantFiled: September 4, 2001Date of Patent: January 14, 2003Assignee: Technical Witts, Inc.Inventor: Ernest H. Wittenbreder, Jr.
-
Patent number: 6507177Abstract: A control circuit is provided for the power-controlled operation of a load in a portion of a load range. A semiconductor switch is provided which is effective in a load circuit. A drive circuit for the switch generates a control signal. The control signal comprises drive pulses following one another and separated by interpulse periods, for controlling the load in a portion of the load range. In an upper portion of the portion of the load range, the control signal comprises a first pulse signal, with first individual pulses following one another with a first pulse frequency, and a second pulse signal, with second individual pulses following one another with a second pulse frequency in the interpulse periods of the first pulse signal. The second pulse frequency may be greater than the first pulse frequency by at least a factor of 10.Type: GrantFiled: June 5, 2001Date of Patent: January 14, 2003Assignee: Alcoa Fujikura Gesellschaft mit beschraenkter HaftungInventors: Horst Flock, Ignaz Fortmeier
-
Patent number: 6507178Abstract: An integrated self-powered and switching electronic circuit regulates a stable reference voltage and comprises a band-gap voltage generator to produce said stable reference voltage for a system circuit block that is generally supplied by the output of the band-gap generator through a comparator and an error amplifier. A regulating loop is provided between the output of the system block and the input of the voltage generator circuit to supply a voltage signal produced by the output of the system block. Advantageously, the voltage generator circuit incorporates both the comparator and the error amplifier.Type: GrantFiled: August 30, 2001Date of Patent: January 14, 2003Assignee: STMicroelectronics S.r.l.Inventors: Franco Cocetta, Giorgio Rossi
-
Patent number: 6507179Abstract: Methods and apparatus are disclosed for reducing output ripple voltages in bandgap voltage reference circuits. Ripple rejection circuitry is connected to a supply voltage and a first control signal, such as from an amplifier. The ripple rejection circuitry provides a second control signal representative of a difference between the supply voltage and the first control signal. The second control signal is then used to generate a reference voltage output. The incorporation of the supply voltage component in the second control signal operates to reduce or suppress the effects of power supply ripple on the bandgap voltage output.Type: GrantFiled: November 27, 2001Date of Patent: January 14, 2003Assignee: Texas Instruments IncorporatedInventors: Chen Jun, Hoon Siew Kuok
-
Patent number: 6507180Abstract: A bandgap reference (BGR) circuit of the present invention includes a first serial circuit made up of a first diode, a first transistor, and a first resistor. A second serial circuit includes a second diode having a greater current feed area than the first diode, a second transistor, and a second resistor. An amplifier amplifies a difference between the voltage drop of the first resistor and that of the second resistor. A third serial circuit includes a third transistor control led by the output of the amplifier, a third resistor and a fourth resistor, and a third diode. Opposite ends of the fourth resistor are respectively connected to the gate of the first transistor and the gate of the second transistor. A reference voltage appears on opposite ends of the portion of the third serial circuit including the third resistor, fourth resistor, and third diode.Type: GrantFiled: November 6, 2001Date of Patent: January 14, 2003Assignee: NEC CorporationInventor: Yoshiki Eguchi
-
Patent number: 6507181Abstract: A method and an arrangement (300, 400) for separating partial discharge pulses originating from various partial discharge sources in an electric system, comprises the steps of measuring a variable of the electric system, such as voltage or current, to which partial discharges occurring in the electric system cause pulses, separating the pulses caused by partial discharges, i.e.Type: GrantFiled: October 17, 2000Date of Patent: January 14, 2003Assignee: ABB Substation Automation OyInventors: Pertti Pakonen, Mats Björkqvist, Vesa Latva-Pukkila
-
Patent number: 6507182Abstract: A non-invasive method and apparatus accurately measures the time difference between two signal edges by optically detecting the emission from a ‘beacon device’ that is modulated as a function of time difference. Through the use of this modulation it is possible to perform timing measurement accurately. Embodiments of a voltage modulator circuit modulate timing information into emission intensity. The method and system of the present invention can be used in applications such as clock skew and pulse width measurements.Type: GrantFiled: December 29, 2000Date of Patent: January 14, 2003Assignee: Intel CorporationInventors: Harry Muljono, Stefan Rusu
-
Patent number: 6507183Abstract: Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.Type: GrantFiled: June 29, 2000Date of Patent: January 14, 2003Assignee: STMicroelectronics S.r.l.Inventors: Jacopo Mulatti, Marco Maccarrone
-
Patent number: 6507184Abstract: A measure of the current through a first terminal of a device in a three-phase power system is obtained for each phase of the system. A measure of the current through a second terminal is also obtained for each phase. To compensate for any changes in phase introduced by the device between the first and second terminals, the measured currents obtained for each phase at those terminals are normalized using a novel, generalized normalization transform having the form: G(&thgr;)=cos(&thgr;)U+sin(&thgr;)J where U represents a unit zero degree phase shift with zero sequence components removed, and J represents a unit ninety degree phase shift with zero sequence components removed. From the normalized currents, a differential current is then calculated for each phase.Type: GrantFiled: March 28, 2001Date of Patent: January 14, 2003Assignee: ABB Automation Inc.Inventor: Joel A. B. Elston
-
Patent number: 6507185Abstract: The invention relates to a test device for testing electronic components mounted on a carrier such as a lead frame, comprising: a transport path for supplying a carrier for testing; a manipulator for engaging and displacing a supplied carrier; a test contact with which a carrier and/or at least one component mounted on the carrier can be placed in contact by the manipulator; and a transport path for discharging a tested carrier. The invention also embraces a test assembly which includes at least one described test device. The invention furthermore provides a method for testing electronic components mounted on a carrier and method for calibrating a test device.Type: GrantFiled: November 9, 2000Date of Patent: January 14, 2003Assignee: FICO B.V.Inventors: Willem Antonie Hennekes, Antoon Willem Pothoven
-
Patent number: 6507186Abstract: In a test and repair method with a test and repair system of the present invention, even when a defect is found in some of a plurality of members to be processed transferred collectively on a member transfer jig, the defective member to be processed is transferred and repaired while it is mounted on the member transfer jig. The condition of the defect occurrence in the member transfer jig is set in processing state data with a member test apparatus. The processing state data is transferred to a data processing apparatus from the member test apparatus. Repair instruction data in accordance with the processing state data is transmitted from the data processing apparatus to a member repair apparatus.Type: GrantFiled: November 16, 2000Date of Patent: January 14, 2003Assignee: NEC CorporationInventor: Yutaka Sugikawa
-
Patent number: 6507187Abstract: An ultrasensitive displacement sensing device for use in accelerometers, pressure gauges, temperature transducers, and the like, comprises a sputter deposited, multilayer, magnetoresistive field sensor with a variable electrical resistance based on an imposed magnetic field. The device detects displacement by sensing changes in the local magnetic field about the magnetoresistive field sensor caused by the displacement of a hard magnetic film on a movable microstructure. The microstructure, which may be a cantilever, membrane, bridge, or other microelement, moves under the influence of an acceleration a known displacement predicted by the configuration and materials selected, and the resulting change in the electrical resistance of the MR sensor can be used to calculate the displacement. Using a micromachining approach, very thin silicon and silicon nitride membranes are fabricated in one preferred embodiment by means of anisotropic etching of silicon wafers.Type: GrantFiled: August 24, 1999Date of Patent: January 14, 2003Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: John D. Olivas, Bruce M. Lairson, Rajeshuni Ramesham
-
Patent number: 6507188Abstract: An apparatus for detecting the angular position of a first rotatable body (10, L) has a number n of uniform angle markings or teeth (11), with at least two rotatable gear wheels (12, 13, 14, 15), which respectively have n1, n2, n3, n4 uniform angle markings or teeth. The angle markings of the at least two rotatable gear wheels (12, 13, 14, 15) cooperate with the angle markings (11) of the first rotatable body (10) in such a way that by detecting the angular positions &thgr;, &psgr; of the at least two rotatable gear wheels (12, 13, 14, 15), the angular position a of the first rotatable body can be determined. When there are two of the at least two rotatable gear wheels (12, 13; 12, 14; 12, 15; 13, 14; 13, 15; 14, 15), ¦ni-nj¦>1 and (ni, nj)=1 or ni, nj are relatively prime and when there are more than two of the at least two rotatable gear wheels, (ni, nj)=1, where 1=i<N, with N being the total number of the at least two rotatable gear wheels (12, 13, 14, 15).Type: GrantFiled: May 24, 2001Date of Patent: January 14, 2003Assignee: Robert Bosch GmbHInventors: Elmar Dilger, Bernd Mueller
-
Patent number: 6507189Abstract: A core of a proximity sensor is made of a highly permeable metal and is shaped and sized to operate as a saturable core proximity sensor, a variable reluctance proximity sensor, and an eddy current proximity sensor. The core has a cross-sectional shape including a head portion, two legs extending from the head portion, and two foot portions (feet) extending from the two legs. The head portion forms a substantially planar section along the upper surface and is perpendicular to the sectional direction created by the two legs. The sectional direction of the two legs are perpendicular to the sectional direction of the two feet. The two feet are in a common plane along the bottom surface. Both foot portions are also parallel to the head portion. The cross-sectional shape of the core may further comprises two tail portions (tails), wherein each tail extends from one of the two foot portions in a direction toward the upper surface.Type: GrantFiled: February 28, 2001Date of Patent: January 14, 2003Assignee: Eldec CorporationInventors: Kevin Woolsey, Jeff Lamping, John Marler, Bernie Burreson, Steve Knudson
-
Patent number: 6507190Abstract: Monitor signals are acquired in an interleaved manner during a scan with an MRI system. Frequency changes caused by variations in the polarizing field B0 are measured using the monitor signals, and these measured frequency changes are employed to compensate image data acquired during the scan. Electrical currents are produced in a set of shim coils that shim the polarizing field B0 in the immediate vicinity proximal to the monitor coil.Type: GrantFiled: August 1, 2000Date of Patent: January 14, 2003Assignee: GE Medical Systems Global Technologies Company LLCInventors: Richard Scott Hinks, John E. Lorbiecki
-
Patent number: 6507191Abstract: There is disclosed an NMR cell system for supercritical fluid measurements. This cell system has an NMR cell in which convection is prevented. A reactive gas and a reactive liquid can be smoothly introduced into the NMR cell. The oxygen (air) inside the NMR cell can be removed before measurement. The NMR cell system comprises a cylindrical cell, a cell holder, and an external pumping system. The cylindrical cell and the cell holder are made of a nonmagnetic material that withstands high temperatures, high pressures, and strong acidity. A pipe is mounted inside the cell holder to connect the external pumping system into the cell. A high-pressure cell for use with an NMR spectrometer is also disclosed. This high-pressure cell comprises a pressure-proof cell for receiving a sample, a pressure transfer tube for transmitting pressure to the sample in the cell, and a coupling portion for coupling together the pressure-proof cell and the tube.Type: GrantFiled: September 7, 2000Date of Patent: January 14, 2003Assignee: JEOL Ltd.Inventors: Takefumi Eguchi, Mamoru Imanari, Yoshiaki Yamakoshi
-
Patent number: 6507192Abstract: NMR apparatus for achieving construction of improved patient access. Facilities and methods of mobile and fixed site scanning.Type: GrantFiled: October 22, 2001Date of Patent: January 14, 2003Assignee: Fonar CorporationInventors: Raymond V. Damadian, Gordon T. Danby, John W. Jackson, Hank Hsieh, Terry Morrone, Timothy Damadian
-
Patent number: 6507193Abstract: A permanent magnet for an MRI scanner is made by removing extraneous elements from an ore containing rare earth elements to leave elements Pr and Nd therein, and then selectively stripping therefrom a portion of the element Nd as a byproduct to leave an ore residuum including both elements Pr and Nd therein. The residuum is alloyed with a transition metal to form an alloy therewith. The alloy is then formed into a rare earth permanent magnet configured for use in the MRI scanner.Type: GrantFiled: January 3, 2002Date of Patent: January 14, 2003Assignee: General Electric CompanyInventors: Mark Gilbert Benz, Juliana Ching Shei
-
Patent number: 6507194Abstract: The method of calculating remaining battery capacity specifies battery discharge efficiency with discharge rate and/or temperature as parameters, and calculates remaining battery capacity from integrated discharge current based on the specified discharge efficiency. This method of calculation stores discharge efficiency as an nth order function of discharge rate and/or temperature where n is 2 or greater, computes discharge efficiency based on the stored nth order function with discharge rate and/or temperature as parameters, and calculates remaining battery capacity based on the computed discharge efficiency.Type: GrantFiled: March 28, 2002Date of Patent: January 14, 2003Assignee: Sanyo Electric Co., Ltd.Inventor: Katsuhiro Suzuki
-
Patent number: 6507195Abstract: The present invention is electronic apparatus using removable batteries as a drive source, the apparatus comprising a control section for detecting an internal resistance value of the batteries and using this value to determine how the batteries are consumed, a memory that stores a result of the determination made by the determination circuit, a display section for showing how the batteries are consumed, and a control circuit for controlling the display section. In particular, the control circuit determines display contents depending on information stored in the memory.Type: GrantFiled: June 9, 2000Date of Patent: January 14, 2003Assignee: Olympus Optical Co., Ltd.Inventor: Osamu Nonaka
-
Patent number: 6507196Abstract: A storage battery of the conventional kind for supplying power to electrical devices has a supervising unit for determining the electric capacity. The supervising unit is electrically connected to terminal posts of the battery in order to measure the battery voltage and also measures the battery current. Measurement posts are connected to the end cells of the battery in parallel to the terminal posts and to the supervising unit through bridges. The supervising unit also measures the voltage between the measurement posts and the difference between the measured voltages is a measure of the current flowing through the battery, this difference voltage corresponding to a sum of the voltages over portions of the terminal posts and the bridges. From this difference voltage the current through the battery is calculated and therefrom the remaining electric capacity of the battery is determined by repeating regularly the measurement.Type: GrantFiled: December 22, 2000Date of Patent: January 14, 2003Assignee: Intra International ABInventors: Jes Thomsen, Tore Rehnberg
-
Patent number: 6507197Abstract: An electrostatic force microscope wherein electrostatic force applied to the detector is determined through obtaining the field distribution on several different shaped detectors with the calculation of the voltage distribution near the detector with the Finite Element Method to direct the measurement of the absolute charge amount on surface under test so that one can define the differences between the analysis and the results from the parallel plate model. Of interest is how large the error in the charge detection occurs in conjunction with thickness change of dielectric materials to be tested. There is provided a detector with cantilever which has proper shape for the spatial resolution of 10&mgr; made out of nickel foil for an electrostatic force microscope and the electrostatic force which appeared on it has been calculated.Type: GrantFiled: October 30, 1998Date of Patent: January 14, 2003Assignee: Trek, Inc.Inventors: Akiyoshi Itoh, Katsuji Nakagawa, Manabu Tani, Toshio Uehara, Bruce T. Williams
-
Patent number: 6507198Abstract: The invention is directed to a method and an arrangement for detecting faults in the context of measurement quantities in a motor vehicle. At least one measurement quantity is represented by two redundant signal values. The time-dependent changes of the signal values are determined for fault recognition and a fault condition can be assumed when the signal changes no longer correlate with each other. The arrangement for fault recognition includes an input circuit of a control apparatus to which the measurement quantities are supplied via two lines from two measuring devices. One line is provided with a resistor to ground or to the supply voltage; whereas, the other line is configured without such a resistor or has a resistor to the supply voltage or to ground having an ohmage higher than the first resistor.Type: GrantFiled: May 22, 2000Date of Patent: January 14, 2003Assignee: Robert Bosch GmbHInventor: Martin Streib
-
Patent number: 6507199Abstract: For measuring the operating properties of a subscriber line module (1) for high bit rate data transmission, a test signal is generated within the module and supplied into a test line (6) with a defined line termination (7) who line or terminating properties are known. The echo signal arising in the test line (6) as a result of the test signal is in turn detected in the subscriber line module (1) and interpreted for evaluating the operating properties.Type: GrantFiled: September 29, 2000Date of Patent: January 14, 2003Assignee: Siemens AktiengesellschaftInventors: Thomas Ahrndt, Johann Neumayer
-
Patent number: 6507200Abstract: In a moisture sensor for monitoring the moisture content of layers, at least two parallel electrical conductors connected to a measuring apparatus are disposed adjacent the layers to be monitored. The conductors are surrounded by an insulating material and carry, at their side remote from the layer whose dielectric coefficient is to be monitored, a metal shielding layer for limiting the measurement field of the sensor.Type: GrantFiled: January 5, 2001Date of Patent: January 14, 2003Assignee: Forschungszentrum Karlsruhe GmbHInventors: Alexander Brandelik, Christof Hübner
-
Patent number: 6507201Abstract: A measuring system has at least four electrodes and an electric current measuring resistance placed in a material under measurement in a desired manner. A power supply supplies an alternating current between two of the electrodes through the resistance. A current measuring unit measures an electric current flowing through the resistance. A voltage measuring unit measures an electric potential difference between electrodes other than the electrodes supplied with the alternating current. A computing unit obtains a conductivity on the basis of the measured electric current and electric potential difference, together with a coefficient determined by the manner in which the electrodes are placed, and performs conversion based on calibration data to obtain the amount of a specific substance mixed in the material under measurement.Type: GrantFiled: July 10, 2001Date of Patent: January 14, 2003Assignee: National Research Institute for Earth Science and Disaster PreventionInventor: Masaki Tominaga
-
Patent number: 6507202Abstract: A sensed-pressure-data converter having a circuit for reducing a fluctuation of the output due to a fluctuation of a resistance and a resistance changing characteristic of a pressure sensitive resistance element and for reducing the output offset and offset drift of the pressure sensitive resistance element. The converter of the invention comprises a pressure sensitive resistance element (1), and a controller (2). The controller is an electric circuit connected to the pressure sensitive resistance element for detecting the electric characteristic of the element and includes A/D converters (3, 4), a D/A converter (6), and a memory (5). The controller compensates the electric characteristic due to a resistance change of the pressure sensitive resistance element and issues it from the D/A converter (6).Type: GrantFiled: April 3, 2001Date of Patent: January 14, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyotaka Sasanouchi, Susumu Nishimoto, Norimitsu Kurihara
-
Patent number: 6507203Abstract: Disclosed is a test head assembly for a test system, comprising a test head having a plurality of test head contact areas for providing electronic signals to one or more devices under test (DUT) and/or for receiving electronic signals therefrom. The test head assembly further comprises fastening means for fastening one or more individual, physically separated DUT boards to the test head, each DUT board being provided for holding one or more of the DUTs and adapting electrical contacts thereof to at least one of the plurality of test head contact areas. In order to provide a flexible and modular test head arrangement allowing an easy exchange of different DUT boards with different seizes, the arrangement of the fastening means and the plurality of test head contact areas is commensurable, so that one or more DUT boards with same and/or different lateral dimensions are attachable to the test head.Type: GrantFiled: December 1, 1999Date of Patent: January 14, 2003Assignee: Agilent Technologies, Inc.Inventor: Peter Hirschmann
-
Patent number: 6507204Abstract: The conventional semiconductor element testing equipment is arranged to position each probe accurately and need a burdensome operation for fixing, and includes only a limited number of electrode pads and chips to be tested at a batch. An equipment for testing a semiconductor element is arranged to keep each of electrode pads formed on a semiconductor element to be tested in direct contact with each of probes formed on a first substrate composed of silicon, one of electric connecting substrates disposed in the equipment. On the first substrate, each probe is formed on a cantilever and a wire is routed from a tip of each probe along a tip of the cantilever to the electrode pad formed on an opposite surface to the probe forming surface through an insulating layer.Type: GrantFiled: March 9, 2000Date of Patent: January 14, 2003Assignee: Hitachi, Ltd.Inventors: Masatoshi Kanamaru, Yoshishige Endo, Atsushi Hosogane, Tatsuya Nagata, Ryuji Kohno, Hideyuki Aoki, Akihiko Ariga
-
Patent number: 6507205Abstract: A tester to device-under-test interface is disclosed in which a PCB has a socket for a device under test (DUT), one or more cable connectors for cables from an IC tester, an interface matrix card slot having a plurality of contacts electrically connected to the DUT socket and the cable connector pins, and an interface matrix card having a plurality of horizontal and vertical conductors capable of being electrically connected to each other for mapping the proper connection of signals between the DUT socket and the tester cables.Type: GrantFiled: November 14, 2000Date of Patent: January 14, 2003Assignee: Xilinx, Inc.Inventors: Michael J. Dibish, Sunae Kang
-
Patent number: 6507206Abstract: For ensuring that each of a plurality of IC (integrated circuit) packages are placed within a temperature soaking chamber for a predetermined time period before being transferred to a testing chamber, an input stopper device is disposed at an input of a track with the track being disposed through the temperature soaking chamber. A prior container holding a prior plurality of IC packages is placed at the input of the track such that the prior plurality of IC packages slides out of the prior container along the track into the soaking chamber when the input stopper device is at a passing position. The prior plurality of IC packages is placed within the soaking chamber for the predetermined time period before each of the prior plurality of IC packages is transferred to the testing chamber when an output stopper device at an output of the track within the soaking chamber is placed to a passing position.Type: GrantFiled: October 16, 2000Date of Patent: January 14, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Supachai Vesaruch, Kittinan Chanvivatkun, Nopadon Upakaew
-
Patent number: 6507207Abstract: An improved contact probe pin for wafer probing apparatus including an elongated metal conductor having a connector (or proximal) end, a center or medial section coated with an elastic material, and a contact pad engaging tip end. At least a portion of the center section of the probe pin is coated with a poorly conductive, but highly elastic material so as to enhance its flex characteristics. The coating may uniformly cover a portion of the center section of the probe pin or it may take on a predetermined pattern or shape. The coating may also unevenly cover a portion of the center section of the probe pin. The coating is selected such that it augments or enhances the resiliency of the pin and causes it to have a predetermined stress-strain profile with vertical (or Z-axis) displacement, and thus enables it to have predetermined probe pin tip contact force characteristics.Type: GrantFiled: February 20, 2001Date of Patent: January 14, 2003Inventor: Vinh T. Nguyen
-
Patent number: 6507208Abstract: A low-current probe card for measuring currents down to the femtoamp region includes a dielectric board, such as of glass-epoxy material, forming an opening. A plurality of probing devices, such as ceramic blades, are edge-mounted about the opening so that the probing elements or needles included thereon terminate below the opening in a pattern suitable for probing a test device. A plurality of cables are attached to the card for respectively connecting each device to a corresponding channel of a test instrument. The on-board portion of each cable is of coaxial type and includes an inner layer between the inner dielectric and outer conductor for suppressing the triboelectric effect. An inner conductive area and a conductive backplane that are respectively located below and on one side of each device are set to guard potential via the outer conductor of the corresponding cable so as to guard the signal path on the other side of the device.Type: GrantFiled: March 21, 2001Date of Patent: January 14, 2003Assignee: Cascade Microtech, Inc.Inventor: Randy J. Schwindt
-
Patent number: 6507209Abstract: A test circuit generally comprising a tester connected to a socket for holding a device under test. The device may be configured to have (i) a first function and (ii) a final function. The tester may be configured to (i) stimulate the first function with a test signal to present a first output signal, (ii) stimulate the final function with the first output signal to present a final output signal; (iii) measure a result between the test signal and the final output signal, and (iv) allocate the result between the first function and the final function to disperse a measurement error in the result.Type: GrantFiled: May 8, 2001Date of Patent: January 14, 2003Assignee: Cypress Semiconductor Corp.Inventor: Christopher W. Jones
-
Patent number: 6507210Abstract: A load test board is configured for plugging into a backplane of a chassis. The load test board has a CPU, a variable load controlled by the CPU, a voltage sensor to detect voltage across the variable load, and a current sensor to detect current through the variable load. To test the chassis, one or more of the load text boards are plugged into the backplane of the chassis. Each load test board provides a variable load, using circuitry on the test board to control the variable load, and measures current through the variable load and voltage across the variable load. Information corresponding to the measurements is conveyed to a host computer.Type: GrantFiled: November 22, 2000Date of Patent: January 14, 2003Assignee: Ulysses ESD, Inc.Inventor: Philip D. Olson
-
Programmable logic device capable of preserving user data during partial or complete reconfiguration
Patent number: 6507211Abstract: A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBs) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that-results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The user data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.Type: GrantFiled: July 29, 1999Date of Patent: January 14, 2003Assignee: Xilinx, Inc.Inventors: David P. Schultz, Lawrence C. Hung, F. Erich Goetting -
Patent number: 6507212Abstract: A wide input programmable logic system includes a plurality of logic gates that receive a plurality of row driver signals and memory cell outputs to generate a plurality of logical NOR or NAND outputs for their respective one of said row driver signals and memory cell outputs that are programmed. At least one additional stage of logic gates having a plurality of logical NAND or NOR gates receive the respective logical NOR or NAND outputs and generate a plurality of respective logical NAND or NOR outputs. At least one respective logical NOR or NAND gate receives the respective plurality of logical NAND or NOR outputs and generates an output term. The memory cell may include an electrically erasable non-volatile memory cell having a storage cell that stores a logical value and a select transistor coupled to the storage cell.Type: GrantFiled: November 2, 2000Date of Patent: January 14, 2003Assignee: Lattice Semiconductor CorporationInventor: Ravindar M. Lall
-
Patent number: 6507213Abstract: A programmable logic device comprising a plurality of configuration blocks that may be configured to store configuration information for configuring the programmable logic device. The configuration blocks may be simultaneously programmed.Type: GrantFiled: March 15, 2001Date of Patent: January 14, 2003Assignee: Cypress Semiconductor Corp.Inventor: Harish Dangat
-
Patent number: 6507214Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.Type: GrantFiled: July 18, 2001Date of Patent: January 14, 2003Assignee: Cypress Semiconductor CorporationInventor: Warren Snyder
-
Patent number: 6507215Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.Type: GrantFiled: April 18, 2001Date of Patent: January 14, 2003Assignee: Cygnal Integrated Products, Inc.Inventors: Douglas S. Piasecki, Alvin C. Storvik, II
-
Patent number: 6507216Abstract: Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.Type: GrantFiled: July 17, 2001Date of Patent: January 14, 2003Assignee: Altera CorporationInventors: Christopher F. Lane, Giles V. Powell, Wayne Yeung, Chiakang Sung, Bruce B. Pedersen