Abstract: An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer.

Abstract: An example embodiment of a method and apparatus for reducing back-to-back voltage glitch on a high speed bus is described. A pre-driver circuit receives an input voltage signal whose voltage level swings from a logically low voltage level to a logically high voltage level where the logically low voltage level approximately equals VSS and the logically high voltage level approximately equals VCC. The pre-driver circuit reduces the magnitude of the voltage swing to create a signal that when delivered to a driver transistor ensures that the driver transistor will operate in its saturation region even when the voltage on the high speed bus is at its minimum specified voltage. When the driver transistor operates in its saturation region it can sink a constant current and provide a high output impedance.

Abstract: A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.

Abstract: A typical occurrence in communication circuits, such as transmitters and receivers, is the internal transfer of a sequence of pulses, known as a clock signal, from an amplifier to a digital circuit. For proper operation, it is critical that the digital circuit accurately comprehends the clock signal. However, in some communications circuits a phenomenon called duty-cycle distortion—that is, a distortion of the apparent duration of the pulses in clock signals—causes the digital circuit to read the clock signals as having a longer or shorter duration than intended. Accordingly, the inventors devised unique circuitry for correcting or preventing this distortion. One exemplary circuit uses a voltage divider, comprising a pair of transistors, to set the DC or average voltage of the clock signals input to the digital circuit at a level approximating the logic threshold voltage of the digital circuit.

Abstract: A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

Abstract: An apparatus and method for processing a data input signal with a single ended sense amplifier. The single ended sense amplifier includes a transmission gate circuit and a control circuit coupled between a feedback inverter circuit and an output signal that is fed back to the feedback inverter circuit. An inverter circuit is coupled between an enable signal and the transmission gate and control circuits. During pre-charge operation, the input to the feedback inverter circuit is driven to a first state. The feedback inverter correspondingly drives the input signal to a sensing inverter to a state that is complementary to the input to the feedback inverter circuit, thereby assisting the pre-charge mode and substantially reducing time delay due to the input signal contending with the feedback inverter circuit. One advantage of the present invention is that sense amplifiers can be sized for faster sensing than would other-wise be feasible due to the excessive contention during the pre-charge mode.

Abstract: A differential line driver that includes a 1st operational amplifier, a 2nd operational amplifier, an adjustable reference module, a 1st feedback impedance, and a 2nd feedback impedance. First inputs (e.g. the inverting input or non-inverting input) of the 1st and 2nd operational amplifiers are coupled to receive an input signal. The 2nd inputs (e.g. the compliment of the 1st input) of the 1st and 2nd operational amplifiers are operably coupled to receive an adjustable reference voltage from the adjustable reference module. The adjustable reference module provides the adjustable reference voltage based on the common mode of the power source for the 1st and 2nd operational amplifiers (e.g. Vdd, Vss) and/or the common mode of the input signal. The 1st and 2nd feedback impedances, (e.g. resistors) are coupled from the output of the respective operational amplifiers to either the 1st or 2nd input of the respective operational amplifiers.

Abstract: An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.

Abstract: A simultaneous bidirectional data port circuit includes a current mode output driver for driving an output node and a current mode return driver for driving a differential receiver. The current mode return driver is scalable to reduce current requirements. Each driver is divided into driver segments. Some driver segments are driven by outbound data, and other driver segments are driven by pre-equalization data. Variable pre-equalization is provided by a pre-driver that selects the number of driver segments to be driven with pre-equalization data and the number of driver segments to be driven by outbound data.

Abstract: The circuit and method translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract: A latch includes memory and pulldown circuitry coupled to nodes of the memory for pulling one of the nodes down responsive to data. The pulldown circuitry has gating circuitry for gating the pulling down responsive to a clock signal. The latch also has pull up circuitry coupled to the other one of the memory nodes. A first pull up circuitry section is operable to pull the other one of the memory nodes up to a high state responsive to data. The first pull up circuitry section includes second gating circuitry. The second gating circuitry is operable to gate the pulling up of the other one of the memory nodes responsive to a pull up circuitry clock signal. The first pull up circuitry section more quickly pulls up its memory node, so that the two nodes are pulled up and down at more nearly the same time.

Abstract: A voltage controlled delay circuit comprising n-type inverter delay circuits comprised of n-type inverters each having a PMOS transistor, as a load, with a source connected to a power supply node and with a gate to which a delay time amount control voltage is applied and having an NMOS transistor for driving, an NMOS transistor for bias with a drain-source pass connected between a ground node and a node at which sources of NMOS transistors of the inverter delay circuits each as a stage are commonly connected and with a gate to which a bias voltage to set to be “ON” is applied, and a push-pull inverter circuit which inputs a signal of which the amplitude changes over the entire amplitude in a range of power supply voltage to a first-stage delay circuit.

Abstract: A clock generator having a deskewer is disclosed. The clock generator includes a waveform generator and a deskewer. Clocked by an input clock signal, the waveform generator generates a waveform signal. The deskewer circuit, which is connected to the waveform generator, gates the waveform signal from the waveform generator with the input clock signal to produce an output clock signal such that the output clock signal has less skew with respect to the input clock signal.

Abstract: A clamp for use with a circuit (having an output for delivering an output voltage) forms a voltage boundary for the output voltage based upon a clamp voltage. To that end, the clamp includes a clamp input for receiving the clamp voltage, a clamp transistor in communication with the clamp input, and a control transistor in communication with the output. The clamp also includes a driving source for driving at least one of the clamp and control transistors based upon the voltage at the clamp input and the voltage at the output. The output is clamped at a voltage within the voltage boundary of the clamp voltage after the clamp transistor begins being driven by the driving source.

Abstract: A semiconductor device includes an input and output section, an internal circuit section, and a capacitance section. A signal is inputted to or outputted from the input and output section. The internal circuit section receives the signal inputted to the input and output section or outputs the signal via the input and output section. The capacitance section includes a capacitance connected to the input and output section. The signal is outputted on a signal transmitting line from the internal circuit section to the input and output section. The capacitance section is provided on a conductive line different from the signal transmitting line.

Abstract: A temperature-compensated monolithic logarithmic amplifier includes a logarithmic amplifier cell (26) configured to produce a logarithmic voltage signal (V3) representative of a difference between a first voltage (V1) developed across a first PN junction device (D1) in response to an input signal (Iin) and a second voltage (V2) developed across a second PN junction device (D2) in response to a reference signal (Iref) and an output circuit (36) including an output amplifier (19), a temperature-dependent first resistive element (R1) having a positive temperature coefficient, and a second resistive element (R2). The output circuit (36) produces a temperature-compensated output signal (Vout) in response to the logarithmic voltage signal (V3). The first resistive element (R1) is composed of conductive aluminum or aluminum alloy interconnection metallization that also is utilized as interconnection metallization throughout the monolithic logarithmic amplifier.

Abstract: A superconductor circuit (50) for providing active timing arbitration between SFQ pulses. The superconductor circuit (50) includes a first superconducting transmission line (52) having at least one inductor (54) for transmitting first input pulses, and a second superconducting transmission line (62) having at least one inductor (64) for transmitting second input pulses that are correlated to the first input pulses. The first and second superconducting transmission lines (52, 62) are coupled together in order to generate a flux attraction between the first and second input pulses for reducing relative timing uncertainty.

Abstract: A method is disclosed wherein the voltage of a semiconducting substrate can be locally pumped to a voltage different than the bulk of the semiconducting substrate generally. The local voltage may be pumped into a localized portion of the bulk substrate, or it may be pumped into a portion of the substrate that is isolated from the bulk substrate. This localized biasing may be used for various purposes, including the adjustment of body effect in a plurality of transistors, adjusting the threshold voltage of a capacitor, and reducing latch-up sensitivity of a transistor circuit.

Abstract: To mitigate against base current errors in a current mirror circuit having a low overhead supply voltage, a complementary polarity base current error reduction and auxiliary turn-on circuit provides an overhead voltage that enjoys a base-emitter diode drop improvement over a conventional circuit. The emitter area of an input stage's input current mirror transistor is used as a normalizing factor, and each output stage contains additional current circuitry that compensates for geometry differences of current mirror transistors, minimizing power dissipation and crosstalk. Emitter areas of input stage transistors are defined in accordance with current compensation relationships between the transistor circuits of the output stages and the input stage.

Abstract: A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt.

Abstract: A reference generator having a temperature-dependent output variation that is greater than an absolute temperature variation includes a first source and a second source, the first source generating a proportional to absolute temperature (PTAT) output. The second source generates an output having a temperature coefficient less than or equal to zero. The reference generator further includes a subtraction circuit coupled to the first and second sources, the subtraction circuit operatively subtracting the output of the second source from the PTAT output and generating an offset output, the offset output having a variation greater than an absolute temperature variation. Using the reference generator described herein in accordance with the invention, circuits having a relatively high temperature dependency can be easily compensated. Moreover, the reference generator is suitable for temperature sensing with large temperature dependency without requiring a high supply voltage.

Abstract: The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor. The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET. The current through the second amplifier determines the output signal VOUT. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors.

Abstract: A musical amplifier that includes a vacuum tube and a transistor. The vacuum tube is connected to the gate of the transistor, so that the current flow through the transistor is controlled by the vacuum tube. According to one example of the invention, the vacuum tube-transistor arrangement is set up in a “push-pull” arrangement, where a vacuum tube-transistor combination controls positive voltages, and another vacuum tube-transistor combination controls the negative voltages delivered by the system, the system output being at approximately zero voltage when not under load. Also, the use of the “Edison effect,” referred to as “thermionic emission” from vacuum tubes to variably regulate output transistor bias current resulting in substantially reduced total harmonic distortion is also disclosed.

Abstract: A circuit (and method) for correcting offset voltage in high-gain differential amplifier chains includes a detector element for detecting an offset voltage and a current mirror for generating an offset correction voltage. The circuit further has a current switch which outputs the offset correction voltage into the correct arm of the amplifier chain and a logic element which clocks the circuit, inputs a signal from the detector element and outputs a signal to the current switch.

Abstract: One embodiment of the present invention is an improved feedback amplifier circuit having a variable closed loop gain which avoids including switching elements in its feedback network and maintains a constant output voltage window for an input signal having a wide dynamic range. That is, the switching elements are not on the active feedback path (e.g., they are isolated from the active feedback path). In this manner, the gain of the amplifier circuit may be determined only by the feedback resistance which can be more easily controlled through the use of precision resistors. Additionally, by removing the switches from the feedback network, the parasitics associated with each switch may also be removed from the feedback path of the amplifier circuit. Accordingly, the bandwidth of the feedback amplifier circuit can be controlled more effectively. Specifically, the present embodiment avoids locating the switching functionality in the feedback network by changing the output stage of the feedback amplifier circuit.

Abstract: A controller-based radio frequency amplifier method and module are employed in a modular transmission system in which respective of the controller-based radio frequency amplifier modules amplify a portion of a signal that is input into the system. Each amplifier module includes an amplifier submodule have a plurality of discrete amplifiers arranged in an amplifier chain, a processor submodule is configured to control a level of the amplified output signal that is output from each amplifier module, a power supply module, and an enclosure. The processor submodule is configured to control the discrete amplifiers in the amplifier submodule such that the module may be removed or added to the system without damaging the power amplifier module or other system components.

Abstract: A transmitter has a power amplifier amplifying a radio frequency transmit signal. The radio frequency transmit signal is a non-constant envelope modulated signal. The power amplifier has a first compression point. In a method for sliding a compression point in the transmitter, the power amplifier is operated at a first backoff from the first compression point such that a given adjacent channel power ratio requirement is met for a first peak-to-average ratio of the radio frequency transmit signal. The first compression point is slide to a second compression point for a second peak-to-average ratio of the radio frequency transmit signal, the second compression point being lower than the first compression point. The first and second peak-to-average ratios are dependent on information content of the non-constant envelope modulated signal.

Abstract: An amplifier includes a push-up circuit and a pull-down circuit. The push-up circuit includes a first differential pair and a first driving circuit. The first driving circuit is connected to the first differential pair in a cascade manner. The first driving circuit has a common source amplifying circuit formed of a MOS (metal-oxide-semiconductor). The pull-down circuit includes a second differential pair and a second driving circuit. The second driving circuit is connected to the second differential pair in a cascade manner. The second driving circuit has a common source amplifying circuit formed of a MOS. A portion of a normal operation voltage range of the push-up circuit overlaps a portion of a normal operation voltage range of the pull-down circuit.

Abstract: A circuit is presented which sets the transconductance of a FET using a resistor. The circuit comprises a resistor and first and second FETs series-connected in sequence between a supply voltage and a circuit common point, and third and fourth FETs and a bias current source series-connected in sequence between the supply voltage and the circuit common point. The drain and gate of the fourth FET are connected to the gate of the second FET and the gates of the first and third FETs are cross-coupled to the drains of the third and first FETs, respectively. The bias current source provides a starting current for the circuit. When so arranged, and with the threshold voltages of the first and second FETs matched, the transconductance of the second FET is directly proportional to 1/R1. The circuit can in turn be used to bias other transistors in a reproducible way to fix the transconductance of an amplifier according to the selected resistor value.

Abstract: A circuit and method for generating a variable frequency clock signal that uses a first, lower frequency oscillator, to modulate and vary the frequency of a second, higher frequency oscillator to generate a variable frequency clock signal. The circuit includes a first oscillator, a control circuit, and a second oscillator. The first oscillator generates a first signal having a substantially fixed-frequency magnitude. The control circuit is coupled to receive the first signal from the first oscillator and outputs control signals based on the received first signal. The second oscillator is coupled to receive the control signals from the control circuit and generates the variable frequency magnitude clock signal in response to the received control signal.

Abstract: Disclosed is an integrated voltage-controlled crystal oscillator intended to present the conditions for circuit constants in an oscillator circuit that can improve the oscillator's frequency tuning range with respect to the variable capacitance range of a variable-capacitance element. The voltage-controlled crystal oscillator comprises a crystal, an amplifier, and a load capacitor, wherein the load capacitor includes a voltage-controlled variable-capacitance element integrated on a semiconductor substrate and a DC cut capacitor element connected in series with the voltage-controlled variable-capacitance element, and the DC cut capacitor element has a capacitance value (Ccut) whose ratio to a maximum capacitance value (Cvmax) of the voltage-controlled variable-capacitance element (Ccut/Cvmax) is more than 0.5 and not more than 10.

Abstract: The performance of broadband isolators and circulators can be characterized by the ratio fmax/fmin, where fmin and fmax are defined as the edges of the frequency band in which the devices have acceptable operating characteristics. For the most advanced isolators and circulators available today this ratio is approximately 3:1. This invention teaches how to improve broadband performance substantially. The present limitations are shown to be primarily due to two causes: 1.) lack of bias field homogeneity, and 2.) previously unrecognized low-field loss due to excitation of magnetostatic surface waves. These surface waves are excited at the dielectric/ferrite interfaces on the side faces of the ferrite platelets or discs in the devices. For stripline edge-mode isolators and stripline circulators, the undesired low-field loss can be reduced by using certain rf device structures in combination with suitable bias magnets.

Abstract: A dielectric filter or a dielectric duplexer is provided which comprises a dielectric block in a substantially rectangular parallelepiped shape, having a pair of opposite parallel end-faces and plural sides extending between the paired opposite end-faces, one of the plural sides being a mounting face; plural resonator holes elongating through the inside of the dielectric block across the paired opposite end-faces; inner conductors provided on the inner walls of the plural resonator holes, respectively; an outer conductor provided on the outside of the dielectric block; input-output electrodes provided only on one of the paired opposite end-faces, separated from the outer conductor, and capacitance-coupled to the predetermined inner conductors, respectively; and conductive terminals for external connection, connected to the input-output electrodes, having at least portions thereof lying substantially in the same plane as the mounting face.

Abstract: In a dual-mode bandpass filter, a metal film is partially formed on one surface of a dielectric substrate or at a certain vertical level within the dielectric substrate, first and second input/output coupling circuits are coupled to the metal film, at least one capacitor is loaded to the metal film so that when an input signal is applied from either input/output coupling circuit, two resonant modes generated in the metal film are coupled. The capacitor preferably includes via-hole electrodes opposing the metal film.

Abstract: An integrated circuit multiplexer comprises a waveguide having an interior cavity, first RF input port, and a first and second output ports; a dielectric structure positioned in the cavity; an RF input feed attached to the dielectric structure that extends through the RF input port; a first RF output feed attached to the dielectric structure that extends through the first RF output port; a second RF output feed attached to the dielectric structure that extends through the second RF output port; a first resonator pair mounted to the dielectric structure between the RF input feed and the first RF output feed, and electrically connected to the waveguide; and a second resonator pair mounted to the dielectric structure between the RF input feed and the second RF output feed, and electrically connected to the waveguide so that the first and second resonator pairs are generally coplanar.

Abstract: A delay circuit in which amplitude characteristic and delay time characteristic of the output signals do not have any ripple relative to the length of the transmission line is provided. The delay circuit includes a circuit that makes a part of signals distributed into two parts by the power divider (103) to be identical in amplitude and inverse in phase relative to the component of signals outputted from the terminal-a directly to the terminal-c of the circulator (104). By composing with the power combiner (107) both signals are offset each other at the output terminal. As a result, only the signals that are inputted from the input terminal (101) and transmitted through the circulator (104) and the open-ended transmission line (105) are outputted to the output terminal (102).

Abstract: A multimode dielectric resonator device is provided in which a dielectric core can be easily disposed in a cavity, a dielectric resonator device comprising resonators in plural stages can be obtained, and the Q0 is maintained at a high value. Dielectric cores 1b, 1c to resonate in plural modes such as TM01 &dgr;−(x−z), TE01&dgr;−y, TM01&dgr;−(x+z) or the like are supported substantially in the center of a cavity 2 by means of a support 3, in the state that the cores are substantially separated from the inner walls of the cavity 2 at a predetermined interval, respectively.

Abstract: A circuit breaker has a set of remotely controllable secondary contacts electrically connected in series with the main contacts which provide overcurrent or fault current protection. An operating mechanism opens and closes the set of main contacts. The secondary contacts are opened and closed by a latching solenoid. The latching solenoid includes a plunger latchable to a first position, which opens the set of secondary contacts, and to a second position which closes the set of secondary contacts. The latching solenoid also includes an open/close coil which when energized with a first polarity signal operates the plunger to the first position and which when energized with an opposite second polarity signal operates the plunger to the second position. A circuit is structured for cooperation with a remote control circuit for energizing the coil with the first polarity signal or, alternatively, the second polarity signal.

Abstract: An auxiliary magnetic trip system for a circuit breaker, the auxiliary magnetic trip system includes a strap configured to conduct a first level of electrical current and a second level of electrical current; a u-shape collar with a first pole face, the u-shape collar disposed around the strap; a trip lever rotatably mounted on an axis; and a holdback system releasably coupled to the trip lever, wherein the holdback system prevents movement of the trip lever at the first level of electrical current and releases the trip lever at the second level of electrical current.

Abstract: A bi-directional latching actuator is comprised of an output shaft with one or more rotors fixedly mounted thereon. The shaft and rotor are mounted for rotation in a magnetically conductive housing having a cylindrical coil mounted therein and is closed by conductive end caps. The end caps have stator pole pieces mounted thereon. In one embodiment, the rotor has at least two oppositely magnetized permanent magnets which are asymmetrically mounted, i.e., they are adjacent at one side and separated by a non-magnetic void on the other side. The stator pole piece has asymmetric flux conductivity and in one embodiment is axially thicker than the remaining portion of the pole piece. An abutment prevents the rotor from swinging to the neutral position (where the rotor magnets are axially aligned with the higher conductivity portion of the pole piece). Thus, the rotor is magnetically latched in one of two positions being drawn towards the neutral position.

Abstract: A limited angle rotary actuator is disclosed comprising: an arcuate stator mountable on a platform, the stator being of predetermined length and predetermined radius so as to define a limited angle of rotation, the stator having a plurality of poles along its arcuate length which are energizable to alternate their polarity; and a rotor mountable on an element to be rotated at a position remote from the center of rotation of the element, the rotor comprising a number of magnetic poles.

Abstract: A magnet coil arrangement comprising an actively shielded superconducting primary circuit (21) comprising first and second magnet windings (1,2,3 and 4,5), and being wound e.g. in winding chambers (7,8,9 and 10,11) in a supporting body (6a,6b) for generating a strong magnetic field in a working volume with a small magnetic stray field and a short circuited secondary circuit (22) which is inductively coupled with the primary circuit (21) and contains third and fourth magnet windings (13,14,15 and 16,17) is characterized in that the magnet windings (13,14,15 and 16,17) of the secondary circuit (22) form an actively shielded magnet coil. This permits a simple and robust coil protection for actively shielded superconducting magnets during a quench wherein the superconducting magnet windings are reliably relieved and the magnetic stray field of the entire arrangement remains small.

Abstract: A toroidal transformer for a communications application where a first winding is wound on the core. A separator comprising a pair of annular-shaped cups then encloses the core and first winding. A second winding is wound on the outer surface of the separator. The separator, fabricated from a low K material, provides substantial reduction in the capacitance between the first and second winding.

Abstract: A coil bobbin for a current transformer is provided which requires no adhesive and no eyelets, as well as enables easy fixing of a primary coil to the coil bobbin without an increase in cost. The coil bobbin includes a configuration in which a coil bobbin 1 is formed, at an outer surface of one of flanges 4 thereof, with a primary coil mounting portion 7 and a primary coil fixing portion 8 so as to protrude outwardly. The primary coil mounting portion 7 and the primary coil fixing portion 8 are formed, at both sides thereof, with through holes 9, 9′ through which a pair of legs 3a of a primary coil 3 for detecting electric current extend. The primary coil fixing portion 8 is formed with a window 12 into which a jig is inserted. The window 12 is formed with concave fixing portions 12a.

Abstract: Magnetic cores including coiled amorphous ferromagnetic alloy strips in which at least fifty percent of the volume contains fine crystalline particles with an average particle size of 100 nm or less are addressed. The composition of the alloy essentially corresponds to the formula FeaCobCucSidBeMf, where M is at least one of the elements V, Nb, Ta, Ti, Mo, W, Zr, and Hf; and a, b, c, d, e, and f are indicated in atom percent and meet the following conditions: 0.5≦c≦2; 6.5≦d≦18; 5≦e≦14; 1≦f≦6; with d+e>18 and 0≦b≦15, and a+b+c+d+e+f=100.

Abstract: The present invention provides a foil winding with multiple high current terminals and a method for producing the foil winding. Conductive foil and insulation film are wound together to form a wound assembly. During winding, temporary pins are placed along the axis at radii where terminals are desired. Foil windings are cut from the wound assembly and terminals pressed into place where the cutoff pins remain in the foil winding from the temporary pins. In an alternate method, a terminal pin can take the place of the temporary pin when winding the wound assembly and remain in the foil winding as the electrical connection to the conductive foil.

Abstract: A fuse element partially encapsulated in an arc-suppression material which can, in turn, be integrated along with a semiconductor device into a semiconductor package to provide overcurrent protection, as well as a method of integrating such a fuse along with a semiconductor device into a semiconductor package wherein the semiconductor package has a standard form factor based on the semiconductor device integrated within.

Abstract: A fuse that includes an arc energy reducing coating to reduce arc energy during a short-circuit and/or a full voltage overload current interrupt is described. The fuse includes end conductor elements, and at least one fuse element secured between and making electrical contact with the end conductor elements. An elongate fuse housing, having a passageway extending longitudinally through the housing, extends between the end conductor elements. The fuse element extends through the housing passageway. An arc energy reducing coating at least partially coats each end portion of the fuse element.

Abstract: The invention concerns an electromechanical protective relay comprising deformable bimetal switches in the event of overload in power lines. A triggering mechanism acts on a flexible blistering segment (20) which can pivot by means of a support (30) on a fixed rest (17) and whereof the stem (21) has an extension (27) formed along the length of the segment and folded back in U- or V-shape to press elastically against a bearing surface (36) of the box so as to cause the segment to exert pressure on the pivot.