Abstract: An apparatus (1) for optical inspection of an article(s) is presented. The apparatus utilizes near-field illumination, and comprises a light source unit (4) generating incident light, a detector unit (14), a fiber bundle for directing (16C) the incident light onto a substantially large surface area (2A) of the article and collecting light (16B) returned from the illuminated surface area, and a control means (28). The control means comprises sensing means consisting of at least three tips for atomic force (AFM) or current tunneling (STM) measurement at sample surface, and is capable of adjusting the position of the fiber bundle relative to the surface of the article.

Abstract: A non-dither spatio-temporal low pass filter method for compensating non-uniformity of the responses of detector elements of an infrared detector array. The methods can be used for one-dimensional scanning arrays and for two-dimensional staring arrays. (FIGS. 3 and 6). First it is determined whether the scene and the detector array have sufficient relative motion for use of a spatio-temporal low pass filter type non-uniformity compensation (NUC) algorithm. If so the NUC algorithm is applied, which recursively uses both spatial and temporal information from near neighbors as a basis to correct fixed pattern noise on the detector array.

Abstract: There is provided a method of effecting mass analysis on an ion stream, the method comprising passing the ion stream through a first mass resolving spectrometer, to select parent ions having a first desired mass-to-charge ratio. The parent ions are then subject to collision-induced dissociation (CID) to generate product ions, and the product Ions and any remaining parent ions are trapped the CID and trapping can be carried out together in a linear ion trap. Periodically pulses of the trapped ions are released into a time of flight (TOF) instrument to determine the mass-to-charge ratio of the ions. The delay between the release of the pulses and the initiation of the push-pull pulses of the TOF instrument are adjusted to maximize the duty cycle efficiency and hence the sensitivity for a selected ion with a desired mass-to-charge ratio. This technique can be used to optimize the performance for a parent ion scan, and MRM scan or a neutral loss scan.

Abstract: A mass spectrometry apparatus is provided with an emitter for emitting metal ions, a reaction chamber where the detected gas is introduced and ionized by the metal ions, an aperture for guiding molecules of the ionized detected gas, and a mass spectrometer for measuring the guided molecules. The metal ions emitted from the emitter are caused to fly to the reaction chamber to ionize said detected gas. The detected gas is a halide compound. Further provision is made of a sample gas source for feeding a halide compound to the reaction chamber and an N2 gas source for feeding to the reaction chamber a gas (N2 etc.) to which the metal ions attach less easily than to the halide compound. It is therefore made possible to apply cation attachment of the Fujii system to mass spectrometry of a halide compound and enable precise measurement of fluoride compounds etc. having a large impact on global warming.

Abstract: A reference bolometer and the associated methods for fabricating a reference bolometer and for fabricating an array of bolometers are provided. The reference bolometer is fabricated such that a thermally conductive layer underlies the detector element, i.e., the absorber and transducer elements, and is encapsulated by a protective coating. The protective coating serves to prevent the thermally conductive layer underlying the detector element of the reference bolometer from being etched during the process of etching or otherwise removing other portions of the thermally conductive layer that underlie the detector elements of the imaging bolometers. As such, the thermally conductive layer of the reference bolometer maintains the desired thermal communication between the detector element and the substrate such that the output of the reference bolometer is unaffected by incident radiation.

Abstract: An optical apparatus (10) is provided for non-destructive examination of characteristics of an object (102). The apparatus has a light source (28) for directing a beam of NIR Light towards the object (102), an aperture (24) for diverging the NIR beam through or reflected from the object, a collimating lens (30) for collimating the divergent beam, a diffraction device (32) for separating the collimated beam into wavelength components and focusing lens (36) for focusing the wavelength components onto a matrix of photodetectors (34) which in turn produce electrical output signals proportional to energy levels in the wavelength components. The apparatus (10) can be made compact so that it can be used to examine objects in fields. In one example the apparatus (10) has a pistol-shaped housing with a slot (12) in its turret (18) and a body (16) with a display monitor (14). The body (16) also has an opening through which a correlation device (26) in the form of a PCMCIA card can be connected to the apparatus (1).

Abstract: A process and system for flame detection includes a microprocessor-controlled detector with a first sensor for sensing temporal energy in a first optical frequency range, and a second sensor for sensing temporal energy in a second optical frequency range. The temporal energy sensed in the respective first and second optical frequency ranges are transformed into respective first and second spectra of frequency components. A compensated spectrum of frequency components is generated by performing a frequency bin subtraction of the first and second spectra of frequency components. The compensated spectrum of frequency components represents the energy emitted from the environment with energy emitted from false alarm sources. An average amplitude and centroid of the compensated spectrum of frequency components are obtained and used to determine if a monitored phenomenon represents an unwanted fire situation.

Abstract: An infra-red camera apparatus having a primary mirror assembly formed in a first molded plastic housing; and, a secondary mirror assembly formed in a second molded plastic housing and disposed in front of and in optical alignment with the primary mirror assembly for collecting an image. The first and second housings snap together for assembly of the camera. A focal plane array is disposed in optical alignment with the primary and secondary mirrors for receiving an image focused thereon by the secondary mirror. A substrate is added for supporting the focal plane array and system electronics, which are responsive to images formed on the focal plane array.

Abstract: A system for detecting and graphically displaying a contents of a fast-moving target object comprises: a radiation source, having a position such that at least a portion of radiation emitted from the radiation source passes through the fast-moving target object, the fast-moving target object having a variable velocity and acceleration while maintaining a substantially constant distance from the radiation source and being selected from the group consisting of: a vehicle, a cargo container and a railroad car; a velocity measuring device configured to measure the variable velocity of the fast-moving target object; a detector array comprising a plurality of photon detectors, having a position such that at least some of the at least a portion of the radiation passing through the target object is received thereby, the detector array having a variable count time according to the variable velocity and a grid unit size; a counter circuit coupled to the detector array for discretely counting a number of photons enterin

Abstract: A planar X-ray detector has an X-ray charge conversion film converting an incident X-ray into electric charges, pixel electrodes provided on the X-ray charge conversion film corresponding to respective pixels arranged in an array, switching elements connected to the respective pixel electrodes, signal lines, each of which is connected to a column of switching elements, scanning lines, each of which transmits driving signals to a row of switching elements, and a common electrode provided on the surface of the X-ray charge conversion film opposite to the surface on which the pixel electrodes are provided. The X-ray charge conversion film contains an X-ray sensitive material made of inorganic-semiconductor particles, and a carrier transport material made of an organic semiconductor.

Abstract: Charged-particle-beam microlithography apparatus are disclosed that exhibit minimal deflection aberrations while providing large-magnitude deflections of the charged particle beam using a relatively small excitation current. The apparatus comprises multiple deflectors. A representative deflector comprises a toroidal deflector coil having a semi-angle of 72° and a toroidal saddle deflector coil having a semi-angle of 36°. By adjusting the dimensions and number of windings of each coil, and the excitation current applied to each coil, magnetic-field components associated with cos[3&phgr;] and with cos[5&phgr;], which are higher-order components in the deflection field, are minimized. As a result, four-fold aberrations are minimized and deflection sensitivity is increased.

Abstract: There is disclosed an improved radiation source module having a power supply adapted to be at least partially immersed in a fluid being treated. In one embodiment, the power supply is partly immersed in the fluid being treated. In another embodiment, the power supply is fully submersible in the fluid being treated. A fluid treatment system comprising the radiation source module is also described.

Abstract: In an electron particle machine for observing, inspecting, processing or analyzing a semiconductor wafer as a substrate or a sample, a light source is installed in a preparation chamber. A chucking stage for chucking the semiconductor wafer with a chuck using static electricity is provided with parts for connecting to earth such that they are in contact with the chucked semiconductor wafer. After the chuck using static electricity is released after observation, inspection, process or analysis, a surface of the semiconductor wafer and the parts for connecting to earth are irradiated with light from the light source. This provides conductivity to the surface of the semiconductor wafer, so that charge accumulated on the semiconductor wafer is removed from the surface through the parts for connecting to earth.

Abstract: A sterilizer comprising an openable enclosure (2,4) for surrounding one or more articles (8A, 8B) to be sterilized, the enclosure being arranged to attenuate microwave radiation such that in use, when the enclosure is irradiated with microwave energy, the microwave field energy throughout the interior of the enclosure is significantly less than that outside the enclosure, and the enclosure including a gas tight cavity (2C, 4C) containing a gaseous charge, the charge being chosen from the group of materials which emit ultraviolet radiation when irradiated with microwave radiation.

Abstract: An ultraviolet light beam irradiating apparatus of the present invention has a bed for supporting a work in atmosphere, an ultraviolet light irradiation light source for irradiating the surface of the work with an ultraviolet light beam having a wavelength of 175 nm or shorter, and inert gas inflow structure for allowing an inert gas, preferably nitrogen, helium or argon, into a space in the atmosphere above the work surface of the work. The inert gas is allowed to flow into the space, whereby the oxygen concentration between the ultraviolet light irradiation light source and the work surface is decreased, so that the absorption of the ultraviolet light beam is decreased.

Abstract: A storage phosphor panel having a storage phosphor layer, characterized in that a focusing layer (8) which comprises a multiplicity of adjacent microlenses (9) is incorporated in said storage phosphor panel and forms an outer surface of said panel.

Abstract: An improved Faraday cup array for determining the dose of ions delivered to a substrate during ion implantation and for monitoring the uniformity of the dose delivered to the substrate. The improved Faraday cup array incorporates a variable size ion beam aperture by changing only an insertable plate that defines the aperture without changing the position of the Faraday cups which are positioned for the operation of the largest ion beam aperture. The design enables the dose sensitivity range, typically 1011-1018 ions/cm2 to be extended to below 106 ions/cm2. The insertable plate/aperture arrangement is structurally simple and enables scaling to aperture areas between <1 cm2 and >750 cm2, and enables ultra-high vacuum (UHV) applications by incorporation of UHV-compatible materials.

Abstract: There are provided a second aperture having a beam adjustment opening group and a pattern exposure opening group, a stage for mounting a wafer to which a pattern should be transferred, and a control computer for controlling an electron beam to be irradiated onto the wafer. The control computer has a drawing parameter table which stores an optimum beam adjustment parameter for an electron beam using a pattern density as a parameter. A pattern is transferred by selecting an optimum beam adjustment parameter corresponding to the pattern density from the drawing parameter table for each pattern.

Abstract: A photocoupler device includes a light emitting element; a monitor photodetector and an output photodetector for receiving light from the light emitting element; a primary side lead frame for mounting the light emitting element and the monitor photodetector; and a secondary side lead frame for mounting the output photodetector, wherein the light emitting element and the output photodetector are placed so as to face each other.

Abstract: A method of determining the color and profile of a target surface involves scanning the target surface with an incident light beam containing a plurality of component wavelengths, forming a beam of light reflected from the target surface and synchronized with the incident beam; and splitting the reflected beam into separate sub-beams of different wavelengths. The sub-beams are directed onto a sensor array to permit their relative positions to be determined as the incident beam moves over the target surface. A portion of the reflected beam is directed onto a color sensitive photodetector to obtain data representative of the approximate color composition of the reflected beam. The color and profile of the target surface is determined from the relative positions of the sub-beams on said sensor array using the data representative of the approximate wavelength composition to resolve ambiguities in the results.

Abstract: A stimulable phosphor film in which acicular particles of stimulable phosphor having an aspect ratio of 1.5 or more are oriented in the direction of depth of the phosphor film gives a reproduced radiation image having increased sharpness when it is employed in a radiation image recording and reproducing method.

Abstract: The gain correction image is composed of a grid-free image regardless of the presence or absence of the grid or the kind thereof. The gain correction images are stored in the image memory unit, and, under the control of the pre-process unit and according to the result of the grid detection means, reference is made to the image process parameter table stored in the image process parameter memory unit and the matching gain correction image is downloaded from the image memory unit.

Abstract: Apparatus for reading information stored in a memory layer (15) which includes a shielding device (22), and an X-ray cassette and an X-ray table for use with the apparatus, are disclosed. The shielding device (22) serves to shield a reader device (10) from an information recording beam (25). The reader device (10) includes a receptor (12) to receive emission radiation (17) that contains an image of the information recorded in the memory layer (15). Instead of the shielding device (22), it is also possible to provide a converter (29) that serves to convert an information-recording beam (25) into converted radiation (28) that possesses less energy than the information recording beam (25).

Abstract: In a radiation image read-out apparatus, the line sensor has a light receiving face whose width in the transverse direction of the line portion of the stimulable phosphor sheet exposed to the line stimulating beam is such that 30% to 90% of the amount of stimulated emission corresponding to a part of the stimulated emission spreading beyond the width of the line stimulating light beam as measured on the plane of the light receiving face of the stimulated emission detecting means can be received by the light receiving face in addition to the amount of stimulated emission corresponding to the width of the line stimulating light beam.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: The present invention relates to a semiconductor device with quantum dots and a method of manufacturing the same, and a structure of the semiconductor device which can control an emission wavelength of the quantum dots and a method of manufacturing the same are provided. The semiconductor device comprises a compound semiconductor substrate containing at least three elements, and quantum dots which are formed on the compound semiconductor substrate and whose emission wavelength is adjusted by the lattice constant of the compound semiconductor substrate.

Abstract: A method of epitaxially growing backward diodes as well as apparatus grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: A method for position-selective and material-selective etching of silicon, and examination structures formed using the method, are presented. A semiconductor topography is exposed to an electron beam in the presence of xenon difluoride (XeF2) gas. The beam is scanned over a portion of the semiconductor topography, and silicon portions of the topography contacted by the electron beam and the XeF2 gas are etched. Non-silicon portions, such as dielectrics, metals, and/or metal silicides, are not believed to be etched. Shorter exposure times may be used to remove polycrystalline silicon portions of a topography, while leaving monocrystalline silicon portions intact. Removal of silicon and non-silicon portions of the topography by other means may be used to expose silicon portions of the topography. The electron beam controlled etching recited herein may be used alone or combined with such removal by other means to form examination structures for use in evaluation of semiconductor manufacturing techniques.

Abstract: A liquid crystal display having an increased pixel aperture ratio is disclosed along with a method of making same. An array of a-Si TFTs is deposited on a transparent substrate. Subsequently, an organic insulating layer (e.g. Benzocyclobutene) and a corresponding array of pixel electrodes are deposited over the TFT array so that the pixel electrodes overlap the display address lines thereby increasing the display's pixel aperture ratio. The low dielectric constant &egr; (e.g. about 2.7) and relatively high thickness (e.g. greater than about 1.5 &mgr;m) of the insulating layer reduce the pixel electrode-address line parasitic capacitance CPL in the overlap areas thereby reducing cross-talk (or capacitive coupling) in the display. In sum, an increased pixel aperture ratio is achieved without sacrificing display performance.

Abstract: A high-resistivity silicon carbide single crystal is disclosed that includes at least one compensated dopant having an electronic energy level far enough from an edge of the silicon carbide bandgap to avoid conductive behavior, while far enough from mid-gap towards the band edge to create a greater band offset than do mid-level states when the substrate is in contact with a doped silicon carbide epitaxial layer and when the net amount of the dopant present in the crystal is sufficient to pin the Fermi level at the dopant's electronic energy level. The silicon carbide crystal has a resistivity of at least 5000 ohms-centimeters at room temperature.

Abstract: A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighbouring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 &mgr;m. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 &mgr;m.

Abstract: The invention provides a lead frame size requiring a reduced area, and a package reduced in size. Adjacent light couplings have an insulating and light shielding element disposed therebetween to block a light transmission from one to the other. The insulating and light shielding element allows the light couplings to be arranged close together while preventing crosstalk occurring therebetween. In another construction, a primary light coupling section and a secondary light coupling section are formed around each light emitting element on the primary side and each light receiving element on the secondary side. The primary and secondary light coupling sections are optically interconnected through an insulating and light transmitting element. This construction realizes optical paths of reduced volume, and secures a sufficient distance for preventing crosstalk even where adjacent light couplings are arranged with a reduced distance therebetween.

Abstract: A packaged solid state device having a package, a chip, and an encapsulate having an epoxy resin, a boron containing catalyst that is essentially free of halogen. A LED device having a package, a LED chip, a encapsulate having a cycloaliphatic epoxy resin and a boroxine catalyst essentially free of halogen. A method of encapsulating a solid state device whereby a solid state device is placed into a package, and an encapsulant comprising an epoxy resin, and a boron containing catalyst that is essentially free of halogen, are provided.

Abstract: The forward and reverse blocking voltage capability of a thyristor in accordance with the invention is substantially independent of the active thyristor area (Aa), thereby facilitating its design and its manufacture. This is achieved by means of a concentric arrangement of a deep inner lower-doped perimeter zone (42) of the forward base region (2) with a deep outer perimeter zone (43) of the same conductivity type, doping profile and depth (A4xj=Axj). The outer perimeter zone (43) brings the reverse blocking p-n junction (34) to the front surface (11) at a lateral distance (D3) around the forward blocking p-n junction (32). The outer perimeter zone (43) extends in depth to a lower perimeter zone (44) of the underlying region (4) that forms the reverse blocking junction with the high-resistivity base region (3) of opposite conductivity type. All these perimeter zones (42-44) together provide the thyristor with a deep peripheral termination which surrounds the active thyristor area (Aa).

Abstract: A semiconductor device includes a semiconductor layer structure, and gate, drain and source electrodes provided on the semiconductor layer structure, the gate electrode being located between the drain and source electrodes. A depletion modulating part is located between the gate electrode and the drain electrode and includes portions spaced apart from each other in a gate-width direction.

Abstract: A semiconductor memory device has a reference section which includes a first reference cell block and second reference cell blocks. The first reference cell block includes a second contact diffusion region which is arranged under a virtual ground line and is connected to this virtual ground line via a contact hole. The second reference cell blocks include first and third contact diffusion regions which are arranged under a bit line and can be connected to the bit line via contact holes as needed. Thereby, the number of reference cell blocks to be connected in series can be selected freely, allowing finer settings of a reference current value.

Abstract: The present invention relates to a one-time programmable (OTP) device including three fuses connected in parallel to a logic element which determines that the device is programmed when at least one of the fuses open. The present invention comprises a one-time programmable device that, before the one-time programmable device is programmed, provides, in response to a test signal, a simulation output signal that simulates an output signal that the one-time programmable device provides if the one-time programmable device is programmed.

Abstract: A solid-state imaging device having contacts for a charge sweeping component or the like, with which increases in dark current can be suppressed while increases in contact resistance and the production of alloy spikes can be prevented, and a method for manufacturing this device. A solid-state imaging device has a charge accumulator for producing and accumulating signal charges when light is received, and a charge transfer component for transferring these signal charges, including a conductive layer 18 formed on a substrate 10, such as a silicon layer or metal wiring; an insulating film 21 formed over the conductive layer 18; an opening CH formed over the insulating film 21 and leading to the conductive layer 18; and a wiring layer 34 composed of aluminum containing copper in an amount between 0.4 and 5 wt %, formed at least inside the opening CH contiguously with the surface of the conductive layer 18.

Abstract: A solid state image pickup device is provided, that improves the transfer efficiency of charges in the horizontal charge transfer path by implementing a selectively arranged matrix of semiconductor layers with differing conductivity type, impurity concentration and orientation. Further, the solid state image pickup device prevents the lowering of the transfer efficiency of charges transferred from the vertical charge transfer path to the horizontal charge transfer path.

Abstract: The present invention is a structure for a fast-dump gate (FDG) and a fast-dump drain (FDD) for a charge coupled device. It is envisioned that the charge coupled device be a horizontal readout register of a solid-state image sensor. This structure uses a third layer of polysilicon (or other suitable gate material) to form the fast-dump gate which is in addition to the other two layers of gate material used to form the gates in the horizontal readout register. This allows the channel region under the fast-dump gate (FDG) to form without the use of highly-doped channel stop regions thereby eliminating any potential wells or barriers that may result in transfer inefficiency often time found with other structures.

Abstract: A cross under metal wiring structure which may prevent “latch-up” from causing at a pnpn-structure is provided. The cross under metal wiring structure comprises a lower wiring provided on a topmost layer of the pnpn-structure isolated in an island by a groove, and an upper wiring connected to the lower wiring through a first contact hole opened in an insulating film covered the isolated pnpn-structure and to a layer just below the topmost layer through a second contact hole opened in the insulating film.

Abstract: A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion and merge together into a single channel region. The resulting channel region has a dopant concentration that is less than the dopant concentrations of the individual HV regions. The compact MOS device exhibits a low threshold voltage characteristic.

Abstract: A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.

Abstract: A silicon based PT/PZT/PT sandwich structure is disclosed. A dielectric layer is formed over a semiconductor substrate. The dielectric layer preferably comprises a silicon dioxide layer. A first and the second conductive films are sequentially formed over the dielectric layer. A first ferroelectric film is formed over the first and second conductive films. A second ferroelectric film is formed over the first ferroelectric film. A third ferroelectric film is formed over the second ferroelectric film. The resulting structure is annealed. A third and fourth conductive films are sequentially formed over the third ferroelectric layer. The third and fourth conductive films are patterned.

Abstract: A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Abstract: A capacitor for a semiconductor memory device includes a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate, having contact plugs filled with a conductive material; a diffusion barrier film formed on the interlayer insulation film including the contact plugs; a lower electrode formed on the diffusion barrier film; a dielectric film formed on the lower electrode; an upper electrode formed on the dielectric film; and a different type film formed adjacent to the upper electrode for applying a compressive stress to the dielectric film.

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: An apparatus and method is presented for a DRAM memory cell array exhibiting improved alignment tolerance for bit line contact formation and utilizing closely-spaced double-sided stacked capacitors for increased overall feature density on the circuit die. The use of a sacrificial insulating layer, an etch-stop insulating layer, and insulating spacers surrounding the bit line contact plug permits wet etching of the sacrificial layer to enable double-sided capacitors to be formed close together. In the resulting structure, only the bit line contact plug and insulating sidewall spacers separates adjacent capacitors and hence DRAM cells can be more tightly packed on the circuit die. Another aspect of the invention is improved alignment tolerance of the bit line contact plug.

Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughen ed inner and outer surfaces using ion implantation and an unplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughen ed by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughen ed outer surface to which has been transferred a near-impression image topography of the opposing inner surface.

Abstract: A method of forming a Flash EEPROM device with a gate electrode stack includes forming a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next, form a surface P+ doped halo region in the surface of the N+ source region juxtaposed with the control gate electrode. The P+ halo region is surrounded by the N+ source region. The result is a device which is erased by placing a negative voltage of about −10V on the control gate and a positive voltage of about 5V on the combined source region/halo region to produce accumulation of holes in the channel which distributes the flow of electrons into the channel rather than concentrating the electrons near the interface between the source region and the edge of the tunnel oxide layer. The tunnel oxide layer has a thickness from about 70 Å to about 120 Å.