Patents Issued in February 6, 2003
  • Publication number: 20030025528
    Abstract: The invention implements a Positive Emitter Coupled Logic (PECL) output using CMOS transistors that approximate the Motorola ECL characteristics into standard PECL termination schemes. By creating a PECL output using a switchable current source the PECL output can be integrated into a Low Voltage Differential Signaling (LVDS) structure. The invention allows the user to switch between PECL and LVDS outputs via control logic by enabling the specific circuit elements for each signaling technology. With this invention, the combination of two drivers on one IC device gives system designers the flexibility to use the same circuitry in two separate signaling schemes. Thus, the designers can select to use one output characteristics or the other for their designs.
    Type: Application
    Filed: August 2, 2001
    Publication date: February 6, 2003
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Jeffrey Alma West, Robert John Marshall, Alma Anderson, Dominicus M. Roozeboom
  • Publication number: 20030025529
    Abstract: A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is deasserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same principles.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Inventor: Daniel William Bailey
  • Publication number: 20030025530
    Abstract: A circuit for reducing the noise associated with a clock signal for a latch based circuit has been developed. The circuit includes a charge control portion that stores charge at a pre-determined time of the clock cycle and a dump control portion that releases the stored current also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Inventors: Brian W. Amick, Claude R. Gauthier
  • Publication number: 20030025531
    Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 6, 2003
    Inventors: Sudarshan Kumar, Gaurav Mehta, Vivek Joshi
  • Publication number: 20030025532
    Abstract: A sense amplifier that is configurable to operate in two modes in order to control a voltage swing on the sense amplifier output. The sense amplifier has two feedback paths including a first feedback path having a transistor with a fast response time in order to allow the circuit to operate as fast as possible, and a second feedback path for providing voltage swing control. In the first operating mode, the “turbo” mode, both feedback paths are in operation to provide a higher margin of swing control, thus higher sensing speed. In the second operating mode, the “non-turbo” mode, only the first feedback path is in operation which allows for greater stability and a reduction in power consumption.
    Type: Application
    Filed: October 9, 2002
    Publication date: February 6, 2003
    Inventor: Nicola Telecco
  • Publication number: 20030025533
    Abstract: The invention provides a NANO-ampere operable differential circuit by means of a few additional components. The multi-input differential circuit consists of more than three input elements that are connected to the same tail node, and an adaptive bias current control circuit. Applications of this multi-input differential circuit, which are, for instance comparators and voltage followers, do have a very low operation current at a normal operation mode. The proposed differential circuit is applicable for all kinds of analog complex circuits to attain nano-power operation.
    Type: Application
    Filed: June 24, 2002
    Publication date: February 6, 2003
    Inventors: Shin-ichi Akita, Yasuhide Ikura, Tatsuhiro Yano
  • Publication number: 20030025534
    Abstract: A circuit arrangement for generating specific waveforms includes a controllable voltage transformer circuit for generating an output signal (VOUT) with a specific waveform, which increases the voltage of its output signal depending on a first control signal (VH) or reduces it depending on a second control signal (VL). The arrangement also includes a control unit that generates the first and second control signal (VH, VL) for the voltage transformer circuit depending on a reference signal (VREF) in the form of an open-loop control or in the form of a closed-loop control.
    Type: Application
    Filed: May 8, 2002
    Publication date: February 6, 2003
    Inventor: Christian Kranz
  • Publication number: 20030025535
    Abstract: The invention features an output driver for integrated circuits that includes a driver that has a data input connected to the integrated circuit, a data output connected to a transmission line leading to the external circuit, and impedance adjusting means for adjusting the output impedance of the driver circuit according to determinable impedance adjusting data. The output driver also includes a dummy circuit having a dummy driver circuit and transmission line, and an impedance control circuit for controlling the output impedance of the driver circuit. The impedance control circuit controls the impedance of the driver circuit by determining the impedance adjusting data (necessary for matching the output impedance of the dummy driver circuit to the characteristic impedance of the dummy transmission line and outputting the determined impedance adjusting data to the impedance adjusting means of the driver circuit.
    Type: Application
    Filed: June 11, 2002
    Publication date: February 6, 2003
    Inventor: Arindam Raychaudhuri
  • Publication number: 20030025536
    Abstract: A voltage follower includes a follower stage including first and second bipolar junction transistors connected in cascade, and a first current generator connected to the follower stage for biasing the first and second bipolar junction transistors. A cascode stage is connected between the first current generator and the first bipolar junction transistor, and a second current generator is connected between the first bipolar junction transistor and a first voltage reference. The voltage follower dissipates less power when the output current is small.
    Type: Application
    Filed: July 8, 2002
    Publication date: February 6, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventor: Tiziana Mandrini
  • Publication number: 20030025537
    Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.
    Type: Application
    Filed: July 24, 2002
    Publication date: February 6, 2003
    Applicant: Zarlink Semiconductor Limited
    Inventor: Peter Graham Laws
  • Publication number: 20030025538
    Abstract: A phase-lock loop (PLL) filter architecture includes a first charge pump (508) and a second change pump (510). The second charge pump (510) operates in opposite phase of the first charge pump (508) in order to take away excess charge from the loop filter capacitor(s) . By using a second charge pump as described, the PLL filter does not require the use of a large capacitor and can therefore be integrated.
    Type: Application
    Filed: February 8, 2002
    Publication date: February 6, 2003
    Inventors: Biagio Bisanti, Stefano Cipriani, Francesco Coppola
  • Publication number: 20030025539
    Abstract: An apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate the first and the second control signals in response to the input signal and the output signal.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Applicant: CYPRESS SEMICONDUCTOR CORP.
    Inventor: Timothy E. Fiscus
  • Publication number: 20030025540
    Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.
    Type: Application
    Filed: July 29, 2002
    Publication date: February 6, 2003
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoji Nishio, Seiji Funaba, Kayoko Shibata, Toshio Sugano, Hiroaki Ikeda, Takuo Iizuka, Masayuki Sorimachi
  • Publication number: 20030025541
    Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by adjusting the source resistance of the pre-drive devices to generate a slew-controlled pre-drive signal for driving the output drive devices.
    Type: Application
    Filed: August 2, 2001
    Publication date: February 6, 2003
    Inventors: Guy Harlan Humphrey, Laurent Francois Pinot
  • Publication number: 20030025542
    Abstract: A novel method and apparatus is presented for reducing the slew rate of transition edges of a digital signal on a node of an integrated circuit by connecting transistors with differing threshold voltages between the node and a voltage source and driving the gates of these transistors with the same driving signal.
    Type: Application
    Filed: August 2, 2001
    Publication date: February 6, 2003
    Inventor: Guy Harlan Humphrey
  • Publication number: 20030025543
    Abstract: A flip-flop circuit (100) that may have a reduced delay time between an edge of a clock input signal and a data output signal has been disclosed. A data signal may be received at a data input terminal (1), a clock input signal may be received at a clock signal input terminal (2), and data may be provided at a data output terminal (3). Data may be transferred from a master latch to a slave latch through a transfer circuit in response to an edge of a clock input signal. A transfer circuit may include a transfer device (6) which may have a control terminal connected to a clock signal input terminal (2) and a transfer device (5) which may have a control terminal connected to a buffered clock signal (C). In this way, delay time may be reduced while maintaining high-speed operations even if an input clock signal has a rounded or distorted waveform.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 6, 2003
    Inventor: Takaharu Itoh
  • Publication number: 20030025544
    Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 6, 2003
    Inventors: David Marshall, Karl J. Bois, David W. Quint
  • Publication number: 20030025545
    Abstract: A clock signal generating system using a wobble signal and a data reproducing apparatus, has a first block to detect a frequency error signal or a phase error signal from the RF signals on the recording medium and to output the detected frequency error signal or the detected phase error signal. A second block detects a wobble error signal from the wobble signals on the recording medium and outputs the detected wobble error signal. A clock generating unit generates a clock signal using the detected frequency error signal or the detected phase error signal of the second block when the RF signals have an error, and using the detected wobble error signal of the first block when the wobble signals have an error.
    Type: Application
    Filed: June 24, 2002
    Publication date: February 6, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyun-soo Park, Jae-seong Shim, Kiu-hae Jung, Ki-hyun Kim
  • Publication number: 20030025546
    Abstract: A protection circuit 10 has a diode 31 being connected in parallel to an inductive load 11 and having a forward direction set reverse to the conduction direction of a power supply current and a Zener diode 33 being placed between one terminal of the diode 31 and one terminal of the load 11 corresponding to the terminal of the diode and having a forward direction matched with the conduction direction of the power supply current.
    Type: Application
    Filed: July 26, 2002
    Publication date: February 6, 2003
    Applicant: AUTONETWORKS TECHNOLOGIES, LTD.
    Inventors: Keizou Ikeda, Kouichi Takagi, Shuji Mayama
  • Publication number: 20030025547
    Abstract: A level shifting circuit for level shifting a control signal which sets a Gate voltage of a power amplifier includes circuitry for adding gain to the level shift. The addition of gain to the level shift causes the gate voltage to change faster than the control voltage, and this, in turn, makes it possible to get higher dynamics to control the Gate voltage of the power amplifier. When the circuitry is utilized in a power amplifier including a plurality of amplifier stages, problems associated with the output stage showing non-monotonic behavior can be avoided. The level shifting circuit is particularly useful in power amplifiers using MESFET transistors such as power amplifiers used in cellular telephones.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Inventor: Per-Olof Brandt
  • Publication number: 20030025548
    Abstract: A voltage generation circuit generates an output voltage at an output node thereof by sharing charge between a first node and a second node so as to increase a potential at the second node from a first voltage to a second voltage. The first node is charged to a third voltage and the second node is driven to a fourth voltage that is greater than the third voltage. Charge is shared between the first node and the second node so that the first and second nodes reach a common fifth voltage, which is between the third and fourth voltages. The first node is driven to a sixth voltage, which is greater than the fourth voltage. Charge is shared between the first node and the output node to generate the output voltage thereat.
    Type: Application
    Filed: August 1, 2002
    Publication date: February 6, 2003
    Inventor: Seong-Jin Jang
  • Publication number: 20030025549
    Abstract: In a booster circuit comprising a first pump capacitor (CP1) connected between nodes (N1, N3) and a second pump capacitor (CP2) connected between nodes (N2, N4), the booster circuit comprises first through fifth switches (S1-S5). Connected to the node (N1), the first switch (S1) is connected to one of a power-supply node, a ground node, and a booster node. Connected to the node (N2), the second switch (S2) is connected to one of the power-supply node, the ground node, and the booster node. Disposed between the nodes (N3, N4), the third switch (S3) makes or breaks. Connected to the node (N3), the fourth switch (S4) is connected to one of the power-supply node, the booster node, and a non-connective node. Connected to the node (N4), the fifth switch (N5) is connected to one of the power-supply node, the booster node, and the non-connective node.
    Type: Application
    Filed: July 23, 2002
    Publication date: February 6, 2003
    Inventors: Yutaka Ito, Takeshi Hashimoto
  • Publication number: 20030025550
    Abstract: A method and an integrated circuit for boosting a voltage are disclosed. A two-stage charge pump is used and has switches and capacitors. Known charges pumps can be single-stage or multi-stage and can achieve only a doubling of the input voltage in practice, depending on the configuration of the switches and capacitors and whereby each stage is provided with a separate drive. An improved two-stage charge pump can triple the input voltage and is advantageously achieved. N-type field effect transistors that are embedded in the substrate of an integrated circuit are utilized as the switches. It is further provided that a second series pass transistor is driven at its bulk terminal and/or its gate by a capacitor and a level shifter. This advantageously obviates the need to expand the width of the additional series pass transistor.
    Type: Application
    Filed: August 1, 2002
    Publication date: February 6, 2003
    Inventor: Jens Egerer
  • Publication number: 20030025551
    Abstract: A reference voltage generator to operate under the supply voltage of 1V or less is provided. In order to output a reference voltage, the change as caused by the ambient temperature of the forward bias voltage of any one of the plural Schottky diodes is compensated with the difference in the forward bias voltage between said plural Schottky diodes. The semiconductor region corresponding to the Schottky contact interface is formed in the same process as for an N well region corresponding to the channel region of the PMOS transistor or for a P well region corresponding to the channel region of the NMOS transistor and the metallic region thereof corresponding to the Schottky contact interface is formed in the same process as for the silicide region comprising the contact region of the MOS transistor.
    Type: Application
    Filed: May 29, 2002
    Publication date: February 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Naoki Kobayashi, Takayuki Kawahara, Takahiro Onai, Hideaki Kurata
  • Publication number: 20030025552
    Abstract: In a static circuit or the like, upper and lower terminals are both set to a first power supply potential Vdd1 in the operating state of an inverter circuit. In the non-operating state, the power supply potential of the upper terminal is reduced to a second power supply potential Vdd2 (<<Vdd1). Provided that an input signal of the inverter circuit has a potential Vdd2 (H level), an output signal thereof must be held at the ground potential (L level) in the operating state. This requires that a conductance Gp of a PMOS transistor and a conductance Gn of a NMOS transistor satisfy the relation: Gp<Gn. Therefore, a well terminal (lower terminal) of the PMOS transistor is set to a potential higher than the power supply potential Vdd2 in order to maintain the relation: Gp<Gn. Accordingly, a signal determined by the circuit in the operating state can be held even in the non-operating state, and the power supply voltage is set to an extremely low potential in the non-operating state of the circuit.
    Type: Application
    Filed: July 15, 2002
    Publication date: February 6, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiichi Kusumoto, Tomoyuki Kumamaru, Takashi Andoh, Tetsuji Gotoh
  • Publication number: 20030025553
    Abstract: The preferred embodiments of the present invention provide a resource managed power amplifier. The resource managed power amplifier is dynamically configurable. The amplifier includes a switching unit for routing an input signal to at least one of a plurality of amplifier cells. Preferably, the switching unit routes the input signal in response to at least one input selector. The amplifier also includes a plurality of amplifier cells amplifying the input signal to produce an amplified signal.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 6, 2003
    Inventor: Alan E. Faris
  • Publication number: 20030025554
    Abstract: An input signal from a signal source (10) is applied to an amplifier (20) via an input coupling capacitor (CIN). An output signal from the amplifier (20) is supplied to a headphone (30) via an output coupling capacitor (C1), and negatively fed back by a first negative feedback circuit configured by resistors (R2, R1), and a capacitor (CNF). A second negative feedback circuit configured by a capacitor (C2) and a resistor (R3) is disposed between the output of the capacitor (C1) and the terminal of the amplifier (20). When a capacitor which is sufficiently smaller in capacitance than the capacitor (C1) is used as the capacitor (C2), the capacitance of the capacitor (C1) can be made smaller than that of a capacitor used in the conventional art and the frequency characteristics in a low-frequency band can be enhanced.
    Type: Application
    Filed: July 29, 2002
    Publication date: February 6, 2003
    Applicant: Yamaha Corporation
    Inventor: Masao Noro
  • Publication number: 20030025555
    Abstract: The present invention provides a radio frequency power amplifier which may not introduce radio frequency loss during switching power amplifier units between high and low output power levels. By connecting a first-stage matching network M12 and first-stage matching network M13 to respective output nodes of a power amplifier unit A11 and power amplifier unit A12 that either one operate by switching, connecting the output nodes of the first-stage matching network M12 and M13 in parallel, connecting a last-stage matching network M11 between the junction of M12 and M13 and the output terminal OUT, the first-stage matching networks M12, M13, and last-stage matching network M11 are formed, for both power amplifier units A11 and A12, so that impedance matching is established between the output terminal OUT and the power amplifier unit in operation when one unit is in operation the other is in stop of operation.
    Type: Application
    Filed: June 5, 2002
    Publication date: February 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Masami Ohnishi, Hidetoshi Matsumoto, Tomonori Tanoue, Osamu Kagaya, Kenji Sekine
  • Publication number: 20030025556
    Abstract: A differential amplifier which provides a precise phase difference of 180 degrees between a pair of differential output signals and which has low power consumption. The differential amplifier comprises a differential amplifying stage which has a differential pair of transistors. An unbalanced input signal is applied to the control electrode of one of the transistors and a pair of differential signals are outputted from a pair of output nodes of the differential amplifying stage. The differential amplifier also has a signal delay element, coupled between the output node on the side of the transistor to which the unbalanced input signal is applied and an output terminal of the differential amplifier, for compensating the phase difference. The signal delay element may have a plurality of taps for precisely adjusting the phase difference.
    Type: Application
    Filed: July 23, 2002
    Publication date: February 6, 2003
    Applicant: NEC COMPOUND SEMICONDUCTOR DEVICES, LTD.
    Inventor: Mitsuhiro Muraoka
  • Publication number: 20030025557
    Abstract: A linear transconductance amplifier which is easily implemented with LSI and superior in a frequency characteristic. The linear transconductance amplifier includes N-channel MOS transistors M1, M2, M3 and M4 having their sources grounded, a current mirror circuit 1 for outputting a constant current 4Ib, and a current mirror circuit 2 in which the ratio between the input current and the output current is 2:1. Gates of the MOS transistors M1 and M3 are connected to each other to constitute an input terminal IN1. The constant current 4Ib is separated into two currents, one of which is the sum ISQ+ of the drain currents ID3 and ID4 of the MOS transistors M3 and M4 and the other of which is the input current ISQ− of the current mirror circuit 2. The sum of the drain current ID1 of the MOS transistor M1 and the output current ISQ/2 of the current mirror circuit 2 determine the differential output current I+.
    Type: Application
    Filed: June 7, 2002
    Publication date: February 6, 2003
    Applicant: NEC Corporation
    Inventor: Katsuji Kimura
  • Publication number: 20030025558
    Abstract: The amplifier circuit includes at least one amplification branch having an input transistor, an output transistor, having a source terminal connected to the input terminal and a drain terminal connected to a first output terminal, and a gain raising stage, having an input and an output connected to the source terminal and, respectively, to a gate terminal of the output transistor. The amplifier circuit includes, moreover, a compensation capacitor connected between the gate terminal and the drain terminal of the output transistor.
    Type: Application
    Filed: June 3, 2002
    Publication date: February 6, 2003
    Applicant: STMicroelectronics S.r.l.
    Inventors: Paolo Cusinato, Andrea Baschirotto, Melchiorre Bruccoleri
  • Publication number: 20030025559
    Abstract: A common mode feedback circuit includes first and second nodes defining a differential node pair. A collective plurality of transconductors includes a first plurality of transconductors associated with the first node and a second plurality of transconductors associated with the second node. Each plurality, for example, may consist of 2 transconductors such that one may be serve as a common mode current sink and the other may be operated as a current source during calibration. At least one transconductor of the collective plurality has an adjustable transconductance. In various embodiments, each node has at least one transconductor with an adjustable transconductance. The common mode feedback circuit includes a calibration engine. The calibration engine adjusts at least one adjustable transconductor until a sensed differential voltage across the differential node pair is substantially zero without the use of external current sources.
    Type: Application
    Filed: June 15, 2001
    Publication date: February 6, 2003
    Inventor: Marius Goldenberg
  • Publication number: 20030025560
    Abstract: A high output amplifier includes a comparison amplifier having a first input, a second input, and an output, wherein a set voltage is applied to the first input, a voltage of the output is coupled to the second input, and the output is generated in response to a difference between the voltage applied to the first input and the voltage coupled to the second input. The high output amplifier also includes a low-pass filtering device that receives and performs low-pass filtering on the output of the comparison amplifier, a conversion device that converts the output of the low-pass filtering device to complementary signals, and a push-pull output device, driven by the complementary signals, that supplies electrical current to a load, wherein an increase in the electrical current supplied by the push-pull output device is decreased by changes in the load due to the low-pass filtering device.
    Type: Application
    Filed: June 19, 2002
    Publication date: February 6, 2003
    Applicant: Agilent Technologies, Inc.
    Inventors: Kenji Kinsho, Hideo Akama
  • Publication number: 20030025561
    Abstract: The present invention relates to controlling load impedance during wireless communications to maintain amplifier linearity for transmissions, such as voice and high-speed data, having significantly different peak-to-average power ratios. At a desired output power, a first load impedance is selected for transmissions having a first peak-to-average power ratio and a second load impedance is selected for transmissions having a second peak-to-average power ratio, in order to ensure that appropriate amplifier linearity is achieved for both voice and high-speed data transmissions. Preferably, amplifier efficiency is optimized for transmissions having the first and second peak-to-average power ratios. Changing the effective load impedance may be effected by providing a first impedance network and switching a second impedance network in association with the first impedance network.
    Type: Application
    Filed: August 6, 2001
    Publication date: February 6, 2003
    Inventors: Kevin Hoheisel, Richard Hohneke, Rohan Houlden, Neal Mains, Stephen Oglesby
  • Publication number: 20030025562
    Abstract: A low-power differential optical receiver useful for high-speed optical communication between CMOS chips includes a multi-stage differential amplifier circuit including a first differential transimpedance stage (22) followed by a plurality of differential feed-forward, high-bandwidth gain stages (24) and a final, differential-to-single-ended converter output stage (26). The inputs of the transimpedance stage receive input signals from a MSM or PIN diode photo-detector. Transistors having plural, different threshold levels are employed within each differential amplifier stage to reduce the size of the footprint of the circuit and improve the gain and bandwidth while decreasing the parasitic capacitance. The optical receiver is fabricated on a silicon on insulator chip, such as in an ultra-thin silicon on sapphire CMOS process which enables the design of high speed circuits with low power consumption and no substrate cross-talk.
    Type: Application
    Filed: June 11, 2002
    Publication date: February 6, 2003
    Inventors: Andreas G. Andreou, Alyssa Apsel
  • Publication number: 20030025563
    Abstract: A bandpass filter is tuned by converting the filter into an oscillator using a negative resistance circuit, tuning the oscillator by using conventional tuning techniques such as tuning a varactor via a phase locked loop, sampling and holding the tuning signal and switching off the negative resistance circuit to convert the oscillator back into a bandpass filter.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Inventor: Kaare Tais Christensen
  • Publication number: 20030025564
    Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described. The frequency synthesizer includes two directly-connected, sequential chains of flip-flops, the first chain having N flip-flops, and the second chain having M flip-flops. The first chain of N flip-flops is clocked by a reference frequency input. Each chain provides a clocked output to an optional duty-cycle recovery circuit, which is in turn coupled to a frequency-update module. There is a sub-threshold low-pass filter included in the frequency-update module which feeds into an oscillator, providing, in turn, the generated frequency as an input to the second chain of M flip-flops, and a sub-carrier frequency output.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 6, 2003
    Applicant: Intel Corporation
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20030025565
    Abstract: A fractional-N frequency synthesizer is offered which does not produce spurious signals of periodically conspicuous spectral intensities and can cancel produced spurious signals up to a practical level even with a spurious-canceling circuit of low accuracy. The synthesizer has a sigma-delta noise shaper. The integral and fractional parts of a frequency divide ratio-setting value that frequency-divides the output signal are set. The fractional part of the frequency divide ratio-setting value is applied to the sigma-delta noise shaper every phase comparison period. The output from the noise shaper and the integral part of the frequency divide ratio-setting value are summed up to thereby produce a sum. The output signal is frequency-divided, using this sum as a frequency divide ratio. The difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper is produced and accumulated in an accumulator every phase comparison period.
    Type: Application
    Filed: July 10, 2002
    Publication date: February 6, 2003
    Inventors: Minoru Takeda, Akira Toyama
  • Publication number: 20030025566
    Abstract: A novel circuit topology which provides for the digital automatic gain control of a VCO is disclosed. The topology of the VCO is based on the negative transconductance oscillator due to its intrinsically simple biasing scheme. A system parameter sensitive to the performance level of the VCO is firstly measured. A digital control signal is then generated in response to the measured system parameter. The biasing current provided by the tail circuit of the VCO is adjusted based on the value of the digital control signal. In this way, the biasing current of the VCO may be adjusted to an optimal value for all frequencies of operation. The automatic control aspects of the present invention is useful in monolithic implementations since it automatically compensates for variations in load resistance, process parameters and component tolerances without requiring expensive manual adjustments at the board level.
    Type: Application
    Filed: August 1, 2001
    Publication date: February 6, 2003
    Applicant: AR card
    Inventor: John William Mitchell Rogers
  • Publication number: 20030025567
    Abstract: A crystal oscillator has a quartz-crystal unit, a first oscillating capacitor connected between a first end of the crystal unit and a reference potential point, a second oscillating capacitor connected between a second end of the crystal unit and the reference potential point, a CMOS inverter connected parallel to the crystal unit, and a feedback resistor connected across the inverter. The crystal oscillator can easily be incorporated into integrated circuits and has an increased variable oscillation frequency range. The crystal oscillator also has an adjustable capacitive assembly having selectable capacitances which is connected parallel to a combined capacitor comprising the first and the second oscillating capacitors.
    Type: Application
    Filed: July 23, 2002
    Publication date: February 6, 2003
    Inventors: Kuichi Kubo, Fumio Asamura
  • Publication number: 20030025568
    Abstract: A quartz-crystal oscillator comprises an oscillating stage and a buffering stage. The oscillating stage has a resonance circuit including a quartz-crystal unit and a capacitor, and an inverting amplifier amplifying a resonance frequency component of the resonance circuit due to feedback oscillation. The buffering stage is provided for outputting the output of the oscillating stage by reducing the amplitude thereof, and has first and second MOS FETs of the same conductive type arranged in series between a power supply and a reference potential. A signal at the output terminal of the inverting amplifier is impressed to the gate of the first MOS FET, a signal at the input terminal of the inverting amplifier is impressed to the gate of the second MOS FET, and an output signal is obtained from a connecting point of the first and second MOS FETS.
    Type: Application
    Filed: August 1, 2002
    Publication date: February 6, 2003
    Inventors: Kuichi Kubo, Fumio Asamura
  • Publication number: 20030025569
    Abstract: A tunable resonator is provided. The resonator includes a housing having a cavity. A resonator body is disposed adjacent to a first surface within the cavity. A gap is formed between the resonator body and the first surface. The resonator is tuned by controlling the size of the gap.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 6, 2003
    Applicant: ADC Telecommunications, Inc.
    Inventor: Markku J. Tiihonen
  • Publication number: 20030025570
    Abstract: The present invention, in various embodiments, provides techniques for reducing effects of electrical impedance. In one embodiment, the impedance is in the form of inductance and arises from vias in a termination PCB and from resistors used on the PCB. In one embodiment, a power plane is placed near the resistors. Additional power and ground planes are created in parallel among themselves and perpendicular to the vias, which cause capacitance to be formed between each pair of the ground and power planes, the ground planes and the vias, and the power planes and the vias. In one aspect, the power plane near the resistors and the formed capacitance allow the high-frequency returned currents to flow through a smaller loop and thus be affected by a smaller inductance. Additionally, the created capacitance reduces both the total impedance of the vias and the resistors and any impedance that result from power-ground discontinuity.
    Type: Application
    Filed: August 6, 2001
    Publication date: February 6, 2003
    Inventors: Thane M. Larson, Andrew H. Barr
  • Publication number: 20030025571
    Abstract: The present invention comprises baluns 2a, 2b which convert balanced line signals and unbalanced line signals mutually, and filters 3a, 3b which are electrically connected to the baluns 2a, 2b and pass or attenuate the predetermined frequency bands. Electrode layers 15a-22a, 25a, 41, 42, 43 which compose the electrode patterns of the baluns 2a, 2b and the filters 3a, 3b, and the dielectric layers 30-39 are integrally stacked.
    Type: Application
    Filed: August 2, 2002
    Publication date: February 6, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomoya Maekawa, Hiroshi Shigemura, Hideaki Nakakubo, Emiko Kawahara, Toru Yamada
  • Publication number: 20030025572
    Abstract: An antenna duplexer has
    Type: Application
    Filed: July 25, 2002
    Publication date: February 6, 2003
    Inventors: Tomoya Maekawa, Hiroyuki Nakamura, Toru Yamada, Toshio Ishizaki
  • Publication number: 20030025573
    Abstract: An improved delay line with an input and an output is disclosed wherein a signal passing through the delay line from the input to the output can be optimized regarding the delay line component size, delay time, and signal configuration. The design and use of more than one impedance conductor is taught. The impedance conductors are arranged in specific alignments with each other and with dielectric bases to result in reduced component size, increased delay time, and to adjust the signal configuration. Further optimization of these features is taught through the use of a shield cover in specific alignment to the impedance conductors and dielectric bases.
    Type: Application
    Filed: June 26, 2001
    Publication date: February 6, 2003
    Inventors: Yuriy Nikitich Pchelnikov, David Scott Nyce
  • Publication number: 20030025574
    Abstract: An integral dual frequency by-pass and transient suppressor device has at least two ceramic semiconductor layers, the upper surfaces of which are formed with electrodes of generally U-shaped configuration. The base portions of the electrodes are exposed at opposite surfaces of the semiconductor layers, the leg portions of the U-shaped electrodes extending toward the base portions of electrodes of opposite polarity. The overlap or registration area of one pair of legs differs from the overlap area of the other leg pair with the result that two capacitors of different values are formed, the capacitors being in parallel and accordingly defining a low impedance path at two discrete frequencies. By varying the conductive paths as a function of the length of the electrode and/or the base of the U, a desired internal inductance is developed.
    Type: Application
    Filed: August 1, 2001
    Publication date: February 6, 2003
    Applicant: AVX CORPORATION
    Inventors: John Barris, Jeff Cain, Wilson Hayworth
  • Publication number: 20030025575
    Abstract: A multilayer filter array, which is formed by layering a plurality of conductive patterns, includes: coils corresponding to respective plurality of lines, which are formed by arranging the plurality of conductive patterns respectively to a single insulator layer; and capacitors corresponding to respective plurality of lines, which are formed by facing the conductive patterns to each other with insulator layers therebetween on insulator layers differing from the insulator layers the coils exist thereupon, wherein only a single conductive pattern, which configures a capacitor corresponding to a respective line, of the capacitors corresponding to respective plurality of lines, is deployed on each respective insulator layer forming each of the capacitors. Accordingly, inductance and capacitance become independently adjustable, as in addition, disparity of damping characteristics between signal lines may be made smaller.
    Type: Application
    Filed: July 10, 2002
    Publication date: February 6, 2003
    Applicant: TDK CORPORATION
    Inventor: Masashi Orihara
  • Publication number: 20030025576
    Abstract: A SAW filter includes a plurality of IDTs arranged on substrate along a SAW propagation direction, and balanced signal terminals connected to an IDT. The SAW filter is a floating balanced type. The plurality of IDTs are arranged so as to provide a horizontally asymmetrical structure with respect to an imaginary axis that is positioned at the approximate center of the center IDT in the SAW propagation direction and which is substantially perpendicular to the SAW propagation direction. Thus, a SAW filter having filtering characteristics and a balance-to-unbalance conversion function is achieved with high balance between the balanced signal terminals.
    Type: Application
    Filed: July 26, 2002
    Publication date: February 6, 2003
    Inventor: Yuichi Takamine
  • Publication number: 20030025577
    Abstract: A highly compact bandpass filter that has excellent mechanical strength is disclosed. A bandpass filter according to the present invention employs a dielectric block of substantially rectangular prismatic shape constituted of a first portion lying between a first cross-section of the dielectric block and a second cross-section of the dielectric block substantially parallel to the first cross-section and second and third portions divided by the first portion and metal plates formed on surfaces of the dielectric block. The first portion of the dielectric block and the metal plates formed thereon are enabled to act as an evanescent waveguide. The second portion of the dielectric block and the metal plates formed thereon are enabled to act as a first resonator. The third portion of the dielectric block and the metal plates formed thereon are enabled to act as a second resonator. The metal plates include an inductive stub formed on the surface of the first portion of the dielectric block.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 6, 2003
    Applicant: TDK Corporation
    Inventor: Arun Chandra Kundu