Abstract: A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, forming a first access conductor connecting to the first surface, forming a second access conductor connecting to the second surface, wherein N+1 access conductors are formed per number N of levels of magnetic memory cells. The structure comprises a plurality of levels of magnetic memory cells, each level including at least one magnetic memory having a number N of levels of magnetic memory cells, including a magnetic memory core structure having first and second surfaces, the first and second surfaces each connecting to an individual access conductor, wherein N+1 access conductors are employed per number N of levels of magnetic memory cells.

Abstract: A synchronized mirror delay circuit is used to generate an internal clock signal from an external clock signal applied to the synchronized mirror delay. The internal clock signal is then coupled through a clock tree, and a feedback signal is generated that is indicative of the propagation delay of the internal clock signal through the clock tree. The feedback signal is applied to the synchronized mirror delay to allow the synchronized mirror delay to delay the internal clock signal by a delay interval that compensates for the propagation delay in the clock tree. A lock detector may be used to initially generate the internal clock signal directly from the external clock signal. A fine delay circuit that delays the internal clock signal in relatively fine increments may be used to couple the internal clock signal to the clock tree.

Abstract: An MRAM memory integrated circuit is disclosed. Resistance, and hence logic state, is determined by discharging a first charged capacitor through an unknown cell resistive element to be sensed at a fixed voltage, and a pair of reference capacitors. The rate at which the parallel combination of capacitors discharge is between the discharge rate associated with a binary ‘1’ and ‘0’ value, and thus offers a reference for comparison.

Abstract: An electronic memory system includes a memory array including a plurality of memory cells each storing a bit of digital information. Each memory cell is from among a group of cells associated with a word address and communicates with a read enable line for activating the group of cells associated with the word address for data retrieval during a read operation. Further, each cell communicates with at least one data output line shared by other cells from among other word addresses for data retrieval from the group of cells associated with the enabled word address during a read operation. Logic is provided for logically OR-ing together bits of digital information retrieved from cells sharing the same data output line during a read operation in order to prevent damage to the memory array or corruption of data stored therein should enablement signals accidentally be sent simultaneously to a plurality of word addresses. Preferably, the system includes dynamic logic to perform the logical OR operation.

Abstract: There is provided a semiconductor memory device for preventing an increase of a cell area of a Shadow RAM comprising a portion of an SRAM memory cell and a ferroelectric capacitor connected to a storage node of the portion of the SRAM memory cell and achieving high capacitance formation of a storage capacitor. The Shadow RAM is provided with a relay wiring layer between a wiring layer corresponding to the storage node and a lower electrode of the ferroelectric capacitor, a wiring corresponding to the storage node is connected to a relay wiring via a first and a second opening portion arranged at a first interval and the lower electrode of the ferroelectric capacitor is connected to a relay wiring via a third and a fourth opening portion arranged at a second interval narrower than the first interval.

Abstract: A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to ground when a memory cell in the rowline is being written to and to a voltage source when a memory cell in the rowline is being read. A rowline stack select circuit is provided on the second side of each rowline and is connected to one rowline on each plane of memory. When a memory cell is being accessed, the rowline containing that memory cell as well as each other rowline connected to the same rowline stack select circuit are connected to a current source.

Abstract: A memory array is divided into a plurality of memory cell blocks in m rows and n columns. A write digit line for each of the memory cell blocks is independent of those for the other memory cell blocks, and is divided corresponding to the memory cell rows. Each write digit line is selectively activated in accordance with information transmitted through a main word line and a segment decode line arranged hierarchically with respect to write digit line and commonly to a plurality of sub-blocks neighboring in the row direction. A data write current in the row direction is supplied only by the write digit line corresponding to the selected memory cell so that erroneous data writing into unselected memory cells can be suppressed.

Abstract: Auto-tracking bit line reference schemes have common reference and normal word lines and generate a “½ cell current” reference by providing reference bit lines with pull-up devices having a different effective size from the pull-up devices for bit line or by programming reference cells to different levels. To provide a true “current mirror” connection of the pull-up devices of bit line and one or more reference bit lines, an additional bias bit line causes currents through the pull-up devices for the selected bit line and the reference bit lines to mirror current through the pull-up device for the bias bit line. Embodiments of the invention can be used with binary and multiple-bit-per cell memory and with a variety of sense amplifiers, memory array architectures, and memory cell structures.

Abstract: Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to one of the first and the second source/drain regions. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.

Abstract: This invention provides a nonvolatile semiconductor memory device including a novel memory core portion in which an influence of a parasitic element component in a memory cell information reading path is excluded in a reading operation, and novel sensing means accompanying this memory core structure, so as to achieve rapid sensing. In the memory core portion, a selected memory cell is selected by a global bit line through a local bit line and an adjacent global bit line is connected to a local bit line in a non-selected sector. A column selecting portion connects a pair of the global bit lines to a pair of data bus lines. A load portion having a load equivalent to a parasitic capacitance of a path leading from the memory cell and for supplying a reference current to a reference side is connected to a pair of the data bus lines. A current of the memory cell information is compared with the reference current by a current comparing portion and a differential current is outputted.

Abstract: A flash memory has an interface corresponding to a DDR DRAM. The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.

Abstract: Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 m are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.

Abstract: A flash memory receives an internal data transfer command from a memory controller which causes the flash memory to copy data from one sector of the flash memory to another sector of the flash memory without presenting any data traffic to the bus. The internal data transfer command may optionally include a count field which causes the flash memory to transfer a plurality of adjacent sectors starting from a source address to a corresponding plurality of adjacent sectors starting at a destination address. The internal data transfer command is particularly useful for backing up the contents of a block prior to an erase operation. The internal data transfer command may also be used, if necessary, to restore the data subsequent to the erase operation.

Abstract: A non-volatile semiconductor memory device of the present invention employs an acceleration technique for shortening a column scanning time. The acceleration technique can be realized by adjusting the width of an internal data bus, the adjusted width being selectively used according to an operation mode. When a normal read operation is executed, for example, a NAND-type flash memory device has an internal data bus width corresponding to the data input/output width. When an erase/program verify operation is executed, a NAND-type flash memory device has a wider internal data bus width than the data input/output width. According to the acceleration technique, it is possible to prevent any increase in the column scanning time in proportion to an increase in page size.

Abstract: In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.

Abstract: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: A non-volatile memory device, such as a Programmable Conductor Random Access Memory (PCRAM) device, having an exemplary memory stored state retention characteristic is disclosed. There is provided a method for retaining stored states in a random access memory device generally comprising the steps of programming a memory cell or an array of memory cells by applying a first voltage to the cells and stabilizing the cells by applying a second voltage to the cells, which is less than the first voltage. The second voltage, which acts as a stabilizing voltage, may be a read-out voltage. The second voltage may also be continuously applied to the cells. The second voltage may also be provided as a sweep voltage, a pulse voltage, or a step voltage.

Abstract: Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal-oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: A CPU calculates a logical block number (LBN) based on a logical sector address (LSA) given by a host and converts the logical block number into a physical address (PBN) of a nonvolatile memory using an address conversion table. Pieces of address conversion table information are dispersively stored in erase blocks (30), and logical block numbers are read from the erase blocks in a power-on state to create the address conversion table on a RAM. When writing data from the host, the data is written in a vacant erase block, and an address of the used vacant erase block is stored by a CPU.

Abstract: A method for erasing data of a nonvolatile memory includes adjusting a threshold voltage of a memory cell transistor to a first threshold voltage; adjusting the threshold voltage of the memory cell transistor to a second threshold voltage, the second threshold voltage being lower than the first threshold voltage; adjusting the threshold voltage of the memory cell transistor to a third threshold voltage, the third threshold voltage being higher than the second threshold voltage and being lower than the first threshold voltage; and adjusting the threshold voltage of the memory cell transistor to a fourth threshold voltage, the fourth threshold voltage being lower than the second threshold voltage.

Abstract: A flash memory has been described that can be coupled to an SDRAM controller that performs address scrambling. The flash memory includes a programmable address de-scrambler. The de-scrambler can be programmed to de-scramble primarily row addresses, including bank addresses, to maintain a common erase block location for sequential data. The present invention reduces the possibility of writing contiguous data to multiple erase blocks. The de-scrambler can be implemented as a programmable switch. The switch includes a routing circuit that can be programmed in a non-volatile manner.

Abstract: Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: A system and method are provided for adaptively allocating random access memory (RAM) in an multifunctional peripheral (MFP) device with a plurality of components. The method comprises: supplying an interface; and, in response to interface prompts, selecting the allocation of RAM for MFP features or components. Typically, the MFP device includes fax, scanner, printer, and copier components, and the method further comprises selecting the allocation of RAM for MFP components selected from the group including fax, scanner, printer, or copier. The method further comprises: selecting the allocation of RAM for MFP features selected from the group including post script (PS) documents, printer control language (PCL) documents, tagged image file format (TIFF) documents, or portable document format (PDF) documents.

Abstract: A buffer storage system is provided for storing groupings of data of varying size. The buffer storage system comprises a buffer storage section and a buffer management section. The buffer storage section has a first buffer subsection and a second buffer subsection. The first buffer subsection includes a plurality of buffer units of a first buffer unit size. The second buffer subsection includes a plurality of buffer units of a second buffer unit size wherein the second buffer unit size is larger than the first buffer unit size. The buffer management section is operable to determine the size of an incoming data grouping and to direct the incoming data grouping to one of the buffer subsections based on the size of the data grouping.

Abstract: Systems and methods are provided for a temperature-compensated threshold voltage VT. The stability problems associated with temperature changes are reduced for LL4TCMOS SRAM cells by providing a temperature-compensated VTN. According to one embodiment, a temperature-based modulation of a VBB potential back-biases a triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated VTN that is flat or relatively flat with respect to temperature. One embodiment provides a bias generator, including a charge pump coupled to a body terminal of the transistor(s), and a comparator coupled to the charge pump. The comparator includes a first input that receives a reference voltage, a second input that receives a VT-dependent voltage, and an output that presents a control signal to the charge pump and causes the charge pump to selectively charge the body terminal of the transistor to compensate for temperature changes.

Abstract: Input stage having increased input signal noise margin and method for generating an output signal having a predetermined logic level based on the voltage level of an input signal. The input stage includes an input buffer generating an output signal having a logic level based on the voltage of the input signal relative to the voltage of the reference voltage signal. A voltage generator provides a variable output voltage signal that is used as the reference voltage by the input buffer. The voltage of the output voltage signal provided by the voltage generator is dependent on the logic value of the output signal of the input buffer. In this manner, the reference voltage applied to the input buffer can be adjusted based on the logic level of the outputs signal in order to provide increased input signal noise margin.

Abstract: An apparatus and method for generating an elevated output voltage. The apparatus includes first and second boot nodes at which a respective elevated voltage is generated, first and second gate nodes, and an output node at which the elevated output voltage is provided. The apparatus further includes first and second switches, each having a gate terminal coupled to a respective gate node. The first switch couples the first boot node to the output node during a first portion of a first phase and the second switch couples the second boot node to the output node during a first portion of a second phase. A third switch couples to the first and second boot nodes for providing a conductive path through which charge can be shared between the first and second boot nodes during a second portion of the first and second phases.

Abstract: The preferred embodiments described herein provide a memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: An apparatus and method of operating an open digit line and a folded digit line DRAM memory array having a plurality of memory cells wherein, in a plan view, each memory cell, in one embodiment, has an area of 6F2. One method comprises, storing a first bit in a first memory cell and storing a second bit that is complementary to the first bit in a second memory cell. The first bit and the second bit form a data bit. The data bit is read by comparing a voltage difference between the first memory cell and the second memory cell.

Abstract: A detection circuit in a semiconductor memory device includes a first latch circuit and a second latch circuit. The first latch circuit latches a data strobe signal at a rise of a clock signal after a write latency passes. The second latch circuit receives an output signal of the first latch circuit at a rise of a clock signal to output a detection signal. Circuits in the semiconductor memory device are controlled by a detection signal. With such an operation applied, the semiconductor memory device grasps a correct phase difference between a data strobe signal and a clock signal, thereby enabling a normal operation.

Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.

Abstract: In a shift switch circuit for replacing a data line, a transmission gate circuit connecting node N2 corresponding to ith write data line to node N4 corresponding to ith read data line is provided. An operation of the shift switch circuit can be confirmed according to whether or not an output corresponding to provided data input signal D<i> is observed as data output signal Q<i>. Preferably, a transmission gate connecting i+1th write data line to an output data line is further provided, in order to further ensure operation confirmation. When a fuse circuit is set to replace a data line, ratio of successful chip repairing will be higher.

Abstract: An apparatus and associated method are provided to improve the programming of anti-fuse devices in an integrated circuit. A programming circuit capable of programming a plurality of anti-fuse devices in parallel permits a state-changing voltage to be applied to multiple anti-fuses substantially simultaneously using a common control signal.

Abstract: A multilayered memory device with a plurality of BGA packages laminated, which includes a first BGA package and a second BGA package each having ball bumps, a first multilayer board with a wiring pattern connected to the ball bumps on the first BGA package, a second multilayer board with a wiring pattern connected to the ball bumps on the second BGA package, a connecting board provided between the laminated first multilayer board and second multilayer board to connect the wiring pattern included in each of the multilayer boards, and ball bumps provided on the second multilayer board on the side opposite to the side on which said second BGA package is mounted, and connected to the wiring pattern included in the second multilayer board.

Abstract: A semiconductor storage device includes a main memory cell array and a redundancy memory cell array. The redundancy memory cell array is set to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area. Memory cells in the main memory cell array and the redundancy memory cell array are selected and driven by a memory selection circuit. A control section for controlling the memory selection circuit is set to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array.

Abstract: A programmed value determining circuit is provided in which both the area of the programmable element and the leak current are reduced. During the first period after power is turned on, both the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the storage node is disconnected from the power line VDD and the ground line VSS. During the second period after the first period, at least the NMOS transistor Qn1 is turned on, the storage node is connected to the ground line VSS via the program element 10, and the state of the storage node is detected by the detecting portion 11. During the third period after the second period, the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the state of the storage node is held by the latch portion 12.

Abstract: A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

Abstract: A method for accessing memory cells of a cell field of a DRAM module organized in rows and columns, in which an addressed row is addressed over a word line, and a desired column is addressed over a bit line pair, is described. For a write access, a stored charge is transferred to all bit line pairs, a column address is detected by a column decoder, the appertaining word line is activated, and a read amplifier amplifies the potential on the addressed bit lines. The write access is initiated simultaneously with an activation of the word line.

Abstract: An electrochromic molecular colorant and a plurality of uses as an erasably writeable medium. Multitudinous types of substrates, such as paper, are adaptable for receiving a coating of the colorant. Electrical fringe field or through fields are used to transform targeted pixel molecules between a first, high color state and transparent state, providing information content having resolution and viewability at least equal to hard copy document print. The scope of the invention includes both the liquid coating and the combination of coating on substrate.

Abstract: Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Such memory devices include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. A defect in one column of memory cells results in replacement of four or more columns of memory cells.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A negative differential resistance device is provided that includes a first barrier, a second barrier and a third barrier. A first quantum well is formed between the first and second barriers. A second quantum well is formed between the second and third barriers.

Abstract: A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.

Abstract: A sector synchronized test method and circuit for a memory, applicable for testing several electrically programmable or electrically erasable memory dies. The section synchronize test circuit has a read-write device, a selected switch, and a plurality of test interfaces. While programming or erasing the memory dies simultaneously, the selected switch connects the parallel output terminal, so that the memory dies are connected in parallel. Meanwhile, the read-write device receives a test signal to perform the program or erase operation on the memory dies according to the test signal.

Abstract: In a test circuit for testing an eDRAM provided with a write mask function, eight internal expected values are generated based on a prescribed read data signal among read data signals of one unit of write mask (i.e., eight). Determination is performed as to whether the eight read data signals and the eight internal expected values respectively match or not, and when they match, the eight memory cells are determined to be normal. Thus, a multi-bit test can be performed even when a test pattern is written using a write mask function.