Abstract: A molecular memory system that includes a protective layer that is disposed over a molecular recording layer is described. The protective layer enables a scanning probe to write information to and read information from a molecular memory element by direct electrical contact without substantial risk of damage to either the scanning probe or the molecular recording medium. In this way, the invention avoids the high emission currents, which may damage the probe electrode or the recording media, or both, and avoids other difficulties often associated molecular memory systems with non-contacting probe electrodes.

Abstract: An SRAM device of the present invention is an SRAM device, including: a plurality of bit line pairs that are arranged substantially parallel to one another and connected to different memory cells, respectively; selection means for selecting one bit line pair from among the plurality of bit line pairs; and potential holding means for holding a precharge potential of bit lines that are respectively on opposite sides of the one bit line pair with the one bit line pair being selected, wherein an interval between two adjacent bit line pairs is smaller than an interval between two bit lines of the same bit line pair.

Abstract: Folded bit line pairs are provided corresponding to the respective MTJ Magnetic Tunnel Junction) memory cell columns. Two bit lines forming each bit line pair are respectively coupled through a corresponding column selection gate to two data lines forming a data I/O line pair DI/OP. In the data write operation, an equalizing transistor provided corresponding to the respective bit line is turned ON to short-circuit the two bit lines. A data write current control circuit sets one of the two data lines to one of a high potential state and a low potential state as well as sets the other data line to the other potential state, whereby the direction of a data write current flowing though the bit line pair as reciprocating current can be easily controlled according to the write data level.

Abstract: A method of programming a memory cell includes generating a programming pulse with stepped portions and programming the memory cell with the programming pulse. The memory cell may have 2N voltage levels, where N>1 and represents the number of bits stored within the memory cell. At least two of the 2N voltage levels can be programmed with the programming pulse.

Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: A nonvolatile semiconductor memory device includes a plurality of first wordlines, a plurality of second wordlines coupled to memory cells, the second wordlines being assigned to each of memory sectors, a plurality of transistors each of which connects a first wordline to a second wordline, and a circuit for controlling the transistors in common. One of the first wordlines is connected to one of the second wordlines through one of the transistors. A circuit area for decoding is reduced and current consumption is minimized.

Abstract: Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the data of the subsequently programmed row elsewhere, the charge levels of its cells are driven to common level. The charge levels of the first row of cells then have a uniform influence from the charge levels of the second row, and, as a result, the chance of successfully reading the data stored in the first row is significantly increased.

Abstract: A memory system including an array of memory cells, a programming voltage node for receiving a first programming voltage, a memory controller which controls memory programming operations on the array of memory cells, and voltage detection circuitry, operably coupled to the memory controller and the programming voltage node, with the voltage detection circuitry being configured to enable the memory controller to initiate one of the programming operations if the first programming voltage exceeds a first voltage level and to continue the programming operation once the programming operation has been initiated if the first programming voltage drops to a second voltage level and to terminate the programming operation once the programming operation has been initiated if the first programming voltage drops below the second voltage level, with the first voltage level being greater than the second voltage level.

Abstract: System for generating a reference current in a semiconductor device. The reference current is compared to an internal device current generated by an internal device circuit to verify operation of the device. The system includes a current generator that generates the reference current and is located within the semiconductor device, and a bias generator that is coupled to the internal device circuit. The bias generator generates a back bias current to offset variations to the reference current.

Abstract: None of memory cells employed in a memory cell array 27 is not put into an overerased state even if erase pulse application for 300 ms is executed four times in a fast cell out of the memory cells. Accordingly, one block in the memory cell array 27 is divided into four regions, and the pre-erase written state of each region is written into an erase frequency storage memory 29 that has memory cells of 3-bit for storing an erase frequency. Then, by referring to the contents of the erase frequency storage memory 29, pre-erase write and write verify are executed in one region only once every four erase operations. Thus, the region of the pre-erase write executed during one erase operation is made to be one-fourth of the conventional region, shortening a pre-erase write pulse applying time and a write verify time and reducing an increase in the pre-erase write time ascribed to a reduction in operating voltage.

Abstract: A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.

Abstract: A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.

Abstract: A storage device is provided. The storage device includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers.

Abstract: To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

Abstract: A signal generator for generating a kickb signal used to reset a boost signal used to operate a memory device. The signal generator includes an address detector that receives one or more address lines and a clock signal to produce a detector output. A switch circuit is also included that receives the detector output, the clock signal and a feedback signal to produce a switch output. A delay circuit is coupled to receive the switch output to produce a delayed switch output, and an output circuit is coupled to receive the switch output and the delayed switch output to produce the kickb signal, where the kickb signal forms the feedback signal.

Abstract: Methods and arrangements are provided for use in memory devices, which allow column address strobe (CAS) timing to adjust to, and/or be adjusted by a controller to, have both minimal unloaded latency and optimal pipelined latency. A delay CAS (DC) period is only applied until a row-to-column delay (tRCD) has been satisfied. Once the tRCD has been satisfied, then the DC period is not enforced for subsequent CAS operations within the memory core associated with a page hit. When a subsequent read command is received at the input/output pins of the memory device and a corresponding RAS operation is performed in the memory core, then the tRCD will again need to be satisfied and a DC period will again be enforced. Consequently the methods and arrangements allow the CAS delay to be dynamically and selectively adjusted to best support the workload. This results in better performance and increased bandwidth.

Abstract: A semiconductor memory operates in a write mode and a read mode. The memory includes memory cells, pairs of bit lines connected to the memory cells, sense amplifiers having first and second I/O terminals connected to the bit lines, column selection gates connected to the associated sense amplifiers, and a control circuit. The control circuit controls the sense amplifiers and the column selection gate, so that selected column selection gate turns on before the sense amplifiers are activated during the write mode. The write data is applied to the first I/O terminals of the sense amplifiers. The semiconductor memory thus produced according to the present invention has a reduced circuit size.

Abstract: An integrated circuit memory structure includes a main array of memory elements having wordlines and bitlines and a redundant array of redundant memory elements external to and connected to the main array. Each of the redundant memory elements can replace either one of the wordlines or one of the bitlines.

Abstract: A fuse circuit 1 comprises an electrically programmable fuse 10 and a data latch circuit 11 to hold programmed fuse data. In the data latch circuit 11, prior to programming, a node FUADD is precharged to “H” by a precharge circuit 14 and preset at “H” as the result of the logical product of a fail address FAADD and a latch signal LATCHp by a preset circuit 12 when the fuse 10 needs to be programmed. A programming selecting circuit 13 monitors the node FUADD to select whether to perform or not to performance the programming of the fuse 10. Accordingly, efficient electric programming control becomes possible without using a dedicated register to hold a fuse address to be programmed.

Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

Abstract: This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.

Abstract: When an inputted column address CA and a defect address are compared with each other, an preset defect address and a defect conversion address obtained by inverse conversion of the defect address are both inputted to a comparison circuit. In the comparison circuit, coincidence determination operations are performed being switched between when address conversion is applied to the column address CA and when no address conversion is applied thereto, thereby coincidence comparison can be effected without using the column address CA after an address conversion operation; therefore, a delay in a determination operation accompanying a conversion operation is canceled to perform high speed data reading.

Abstract: A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.

Abstract: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.

Abstract: A refresh control circuit is provided for controlling refresh cycles according to values stored in a register. A related refreshing method is also provided. The refresh control circuit controls the refresh cycles so as to refresh data stored in memory cells. The refresh control circuit includes a refresh counter for generating a plurality of frequency division signals by dividing a clock signal in response to a refresh signal for directing a refresh operation. The refresh control circuit also includes a refresh activation signal generator for generating a refresh activation signal corresponding to the refresh cycle according to values stored in a register.

Abstract: Disclosed is a cell data protection circuit in a semiconductor memory device and a method of driving a refresh mode in the same. The method includes the steps of disabling a word line in a refresh mode faster than in a normal mode, and initiating a bit line equalizing using a same way of the normal mode, wherein the bit line equalizing is initiated after the word line is completely closed so as to prevent an influence of the bit line equalizing on cell data.

Abstract: A multiple power supply connection memory that prohibits initialization until each power supply connection is powered up. Requiring all power supply connections to be powered up before initialization greatly increases the reliability of the memory. In one embodiment, low sense circuits are coupled to each power supply connection to monitor voltage levels. The memory can prohibit initialization and/or prohibit access operations until each power supply connection has an appropriate voltage level.

Abstract: A column select gate of a semiconductor memory device includes read gate circuits. Each read gate circuit includes read gate transistors. Each read gate transistor connects a read column select line to a global I/O line pair in response to a potential level on a bit line pair received on its gate and the potential on the read column select line. A voltage drop caused on one of the paired global I/O lines by turn-on of the read gate transistor is amplified by a main read amplifier to obtain read data.

Abstract: A line memory control method for temporarily writing input image data into a line memory and reading out the image data written in the line memory on a block basis, comprising: a pre-processing step of reducing the data rate of the input image data; a writing step of successively writing the pre-processed image data into a line memory every line by using a first address; and a reading/writing step of reading out the image data on a line basis every block by using a second address different from the first address after said writing step is finished, and writing image data into a read-out block by using the second address.

Abstract: A memory configuration has at least two memories connected to one another. In the event of a memory cell access, it is ascertained in a comparison circuit of the first memory whether the address applied to a first communications interface of the memory corresponds to an address of data stored in the first memory. In the event of non-correspondence of the addresses, the address of the requested data is transferred by a control circuit via a second communications interface, which can be operated independently of the first communications interface, to the second identical memory. The requested data are received from the second memory via the second communications interface of the first memory and output via the first communications interface of the first memory. Point-to-point connections enable a high data transfer rate of the memory configuration and hence a high data throughput with good signal quality.

Abstract: A semiconductor memory device that reduces the time for conducting a multiple word line selection test and operates stably. The semiconductor memory device includes memory cell blocks, row decoders, sense amps, block control circuits, and sense amp drive circuits. Each block control circuit generates a reset signal. The reset signal is used to select the word lines with the row decoders at timings that differ between the blocks. Each block control circuit provides the reset signal to the associated row decoder. The block control circuit also provides the reset signal to the associated sense amp drive circuit so that the sense amps are inactivated at timings that differ between the blocks.

Abstract: A semiconductor memory device includes a plurality of main word lines. A plurality of sub word lines correspond to each one of the main word lines. A plurality of sub word line drivers are also included, wherein each sub word line driver corresponds to one of the sub word lines and connects the corresponding sub word line to the corresponding main word line. The sub word line drivers charge the sub word lines up to a boosting voltage regardless of an activation order between a sub word line selection signal and the main word line. The sub word line drivers can include a first transistor for transferring the sub word line selection signal to the sub word line in response to an activation of the main word line. A second transistor is configured to connect the main word line to the sub word line in response to an activation of the sub word line selection signal. A third transistor is configured to connect the main word line to a gate of the first transistor in response to a high voltage.

Abstract: There is provided a column address buffering circuit for use in memory devices such as a DDR DRAM for receiving column addresses and internally buffering the column addresses. In the buffering process, the column address buffering circuit generates specific internal address signals having different paths according to a burst length before an address strobe signal is inputted thereto. Such an arrangement synchronizes the generation time of the specific internal address signals with those of other internal address signals by positioning a bit transition detecting unit related to generating the specific internal address signals corresponding to an odd cell and an even cell in front of an address latch for generating internal address signals at the same time of the address strobe signal being coupled.

Abstract: A programmable self time circuit for controlling bit line separation in a memory includes multiple self time word lines, each of which is connected to at least one core cell of the memory for activating the cell. The self time word lines have enable signals that can either be programmed on/off, or can be externally controlled for variation of the amount of bit line separation developed during a memory access.

Abstract: A method and apparatus ensure equal address transition detection (ATD) pulse width for all address and chip enable transitions. Address buffer signals from one end of an integrated circuit are combined to form a first combined signal. Address buffer signals and a chip enable signal from a second end of the integrated circuit are combined to form a second combined signal. The two combined signals are logically combined to form a first edge of an ATD pulse. A feedback signal controls the second edge of the ATD pulse for all input signal transitions.

Abstract: A method and a device for detecting if an object is in proximity to the device, wherein sound (audio) transducers already found in the device are used to realize the proximity detection function, along with digital signal processing or equivalent means. The audio transducers are preferably those designed for use with human hearing and speaking capabilities in the range of about 20 Hz to about 20 kHz, and need not be specially designed transducers. The method includes steps of generating a measurement signal; driving an output acoustic transducer of the device with the measurement signal; monitoring an input acoustic transducer of the device to detect the measurement signal; and determining that an object is in proximity to the device based on a detected alteration of the measurement signal. The device may comprise a mobile telephone, such as a cellular telephone, or a personal communicator.

Abstract: A laser pointer with built-in accessories including an elongated housing having a first end, a second end, and a body disposed therebetween. A laser is disposed within the first end of the elongated housing. The laser has a window disposed within the first end for directing a beam outwardly therethrough. A pen is disposed within the second end of the elongated housing.

Abstract: A data transmitting/receiving system is configured so as to send data to an analog-type watch, without the need to make direct electrical contact thereto and without influencing the drive of the hands of the watch. When a timing signal that is sent from the watch is received, a data transmitting unit performs transmission. The watch does not receive data at other times, and this receiving operation is performed intermittently.

Abstract: An electronic timepiece with indicator hands having indicator hands capable of providing a variety of indications and capable of preventing unstable movement of the indicator hands, which comprises time hands (101, 102) for showing a time, first and second indicator hands (103, 104) provided separately from said time hands (101, 102), rotating means for reciprocally rotating said first and second indicator hands (103, 104) in directions opposite to each other within a predetermined range, and restricting means for restricting a movable range and capable of adjusting a restricting position of said first and second indicator hands (103, 104). Jumping of hands or the like of the first and second indicator hands (103, 104) due to impact or the like is restricted by the restricting means. Further, where there is a fear that the first and second indicator hands (103, 104) stop in a non-rotatable range, the restricting means is adjusted to change the movable range of the first and second indicator hand (103, 104).

Abstract: When the stem of an electronic watch such as one using a quartz oscillator circuit is pulled out, a switch operates so that the hands stop while the oscillation continues, thereby reducing the current consumption. The watch may be stored in this condition and, to achieve an even further power savings, a counting circuit is provided counts and, when a given amount of time has elapsed after the stem is pulled out, a signal is output, so as to stop both oscillation and frequency dividing. Additionally, a pull-down resistance connected to the switch is made by two transistors having a large and a small resistance values, with the above-noted signal being used to cause conduction through only the transistor with the large resistance value when in the power-saving condition, so that current in that part is small.

Abstract: A circular case battery hole is formed in the case back right below a battery accommodation hole, and in a portion of the outer surface around the battery hole is provided a battery cover detachment recess portion. A battery cover is formed of a disklike elastic sealing member having a large-diameter portion at its watch case interior side and a small-diameter portion at its outer side, and a disklike hard member made of a metal, a plastic, or the like joined to outer side of the elastic sealing member. The battery cover is attached to the case battery hole portion in such a manner that the small-diameter portion of the elastic sealing member has a horizontal fitting margin relative to the case battery hole. In the battery cover of this embodiment, the elastic sealing member has a fitting recess portion at its outer side while the hard member has an fitting projection portion at its internal side, and the elastic sealing member and the hard member are joined by projection-recess fitting.

Abstract: A scent emitting device incorporates a specially adapted prerecorded playback cassette and playback device, with the prerecorded cassette including one or more scent emitting cartridges and the playback device including scent dispersal apparatus. The recording includes inaudible and/or invisible signals which trigger the scent production mechanism of the player to actuate the scent emitting apparatus. Upon receiving an appropriate signal from the recording, the apparatus actuates a small pump which withdraws a small quantity of the desired scent from the appropriate scent cartridge and sprays the selected scent into a plenum, whereupon it is vaporized and dispersed into the ambient air by a fan or other suitable device. Each prerecorded cassette may include one or more (preferably several) scent cartridges, with the player preferably including a series of syringes for automatically penetrating each cartridge of the cassette as it is inserted into the player.

Abstract: A data storage system achieves improved bandwidth efficiency using a modulated recording signal, channel linearization, and a compressor circuit for compressing peak amplitude of the recording signal. In a preferred embodiment, quadrature amplitude modulation and demodulation is utilized. Another embodiment achieves improved bandwidth efficiency using a recording medium having a substantially rectangular magnetic flux versus magnetic field intensity hysteresis characteristic and a substantially rectangular Kerr rotation versus magnetic field intensity hysteresis characteristic. Yet another embodiment achieves improved bandwidth efficiency using a storage medium having a substantially abrupt flux transition.

Abstract: A data carrier and a method of making the data carrier. The data carrier includes a plastic body, at least one metal layer arranged in or on the plastic body for carrying information encoded in one of CD and DVD format, a semiconductor chip arranged in the plastic body, a communication device for connecting the semiconductor chip with an external apparatus, and a mechanism for balancing an unbalance caused by the semiconductor chip. The method includes providing a matrix carrying the encoded information in a relief, the matrix including at least one projection, casting a first part of the plastic body against the matrix, forming the metal layer on a side of the first part of the plastic body disposed adjacent the matrix, forming at least one recess in the plastic body with the projection, and coating the metal layer with a second part of the plastic body, wherein the recess in the plastic body is capable of receiving the semiconductor chip.

Abstract: A method and apparatus for reproducing a plurality of main data recorded on an insertable recording medium in the desired sequence specified as a playlist by the user. Main data is recorded on a record region of the recording medium and the user can select a playlist that is recorded in a management region of the recording medium.

Abstract: A portable optical disc apparatus made into a slim-type apparatus and an optical disc adapted for the portable optical disc apparatus are disclosed. In the portable optical disc apparatus, a pickup is secured onto a base, and a movable member in the pickup is operated to access only an area within a specific radius range that is a partial area of the optical disc.

Abstract: A magneto-optical pickup includes a light source for emitting a light beam, the light beam traveling to an information recording medium along a first optical path, a first light receiving element group for detecting an error signal, a second light receiving element group for detecting a magneto-optical signal, the first and second light receiving element groups being situated substantially on one plane, a diffraction grating for diffracting light returned along the first optical path from the information storage medium, the diffracted light being directed toward the first light receiving element group, a polarization beam splitter for separating a part of the return light from the information storage medium, a beam of the separated part of return light traveling to the second light receiving element group along a second optical path, a mirror for bending the second optical path, the light beam reflected thereby being directed toward the second light receiving element group, and an anisotropic optical crystal

Abstract: An information recording apparatus for recording information to an optical recording medium, including a disk-like substrate, a spiral or concentric-shaped groove structure along tracks formed on the disk-like substrate, each of the tracks being divided into a plurality of recording units, each of the recording units including a dropout portion in a circumferential direction of the groove structure, the dropout portion being a non-groove portion, the groove structure is formed with a wobble in a fixed cycle in a radial direction, the fixed cycle of the wobble continuing in the circumferential direction along the track; and each length of the recording units is an integer multiple of the cycle of the wobble. The information recording apparatus includes an irradiation source for irradiating a light spot on the optical recording medium, and a controller for controlling an irradiation position of an optical spot from the irradiation source.

Abstract: The present invention aims to provide a disk drive apparatus in which a pickup is prevented from being overheated. The disk drive apparatus includes a motor for rotating a disk-shaped storage medium, a pickup for reading/writing information from/onto the storage medium, a rotation controller for controlling the rotational speed of the storage medium, and an overheat detector for detecting overheating of the pickup. The pickup is cooled by using an airflow entailed by the rotating storage medium. In the disk drive apparatus, when the overheat detector detects overheating of the pickup, the rotation controller increases the rotational speed of the storage medium, thereby increasing the efficiency of cooling the pickup.